JPS6390215A - Continuous variable mode pll circuit - Google Patents

Abstract

PURPOSE:To more precisely cope with the lock state by applying a phase lock signal from a phase comparator to a terminal, which controls the value of the constant current of a charge pump driven with a constant current, through an integrator. CONSTITUTION:A phase lock signal 10 of a phase comparator 3 is obtained as a pulse signal whose pulse width is changed in accordance with the lock state of a PLL circuit. This signal is inputted to an integrator 15 through a buffer amplifier 14, and a part of the output of the integrator 15 is inverted by a polarity converting part 16 to obtain a pair of outputs (d) and (e). They are applied as the control input of a current variable charge pump to continuously change the driving current of the current variable charge pump 11, thus changing the loop characteristic of PLL.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to continuously variable mode PLL (phase locked loop) circuits used in frequency synthesizers and the like.

BACKGROUND OF THE INVENTION FIG. 4 shows the configuration of a conventional two-mode PLL circuit. In Fig. 4, 1 is the reference oscillator, and its output is 2
Further, the output of frequency divider 2 is added as a reference input to phase comparator 3. Two phase lag and lead outputs of the phase comparator 3 are input to a charge pump 4, and a phase lock signal 10 from the phase comparator serves as a control signal for the switch 5. The output of the charge pump 4 is input to a low-pass filter, and the characteristics of the low-pass filter are varied by a switch 5. The output of the low-pass filter is the voltage controlled oscillator 6
The output of the voltage controlled oscillator 6 is used as the output 9 and is simultaneously input to the frequency divider 8. Furthermore, the operation of the above-mentioned conventional example will be explained based on the phase of the output of the frequency divider 8. In Fig. y, except for the switch 5, it is a normally used phase-locked loop circuit. Then, the frequency of output 9 is ``0''.Also, if frequency dividers 2 and 8 are variable frequency dividers, N.

By changing the value of M, the output frequency rO can be changed. The characteristics of this loop can be expressed by the transfer characteristics of the loop key and the low-pass filter 7, and if an RC filter as shown in FIG. 1 is used as the low-pass filter 7, the loop becomes a second-order loop.

At this time, the power supply voltage of the charge pump is Vp, vc.

Let Kv be the modulation sensitivity of ωn, which determines the PLL response.
(natural frequency) and ζ (damping coefficient) are expressed by the following equation.

From this, if R2 is shorted with switch 5, ωn increases, and the natural frequency of the PLL increases, so that
System response becomes faster. Therefore, if the switch 5 is turned on by the phase lock signal 10 when the PLL is not locked, the PLL can be pulled into synchronization more quickly. Also, when locked, switch y-5 is open,
Since ωn becomes small, it is advantageous in terms of noise suppression and stability. By switching the filter characteristics in this way, it is possible to achieve both high-speed rise and high noise suppression characteristics.

Problems to be Solved by the Invention However, in the conventional two-mode PLL circuit described above, since the transfer function of the filter is changed by a switch depending on the mode, it is necessary to externally attach a switch when converting the above circuit into an IC. However, there was a drawback that it was difficult to miniaturize the circuit. Further, there is a drawback that the switch tends to cause disturbance to the voltage controlled oscillator.

The present invention solves these conventional drawbacks.I
It is an object of the present invention to provide an excellent continuously variable mode PLL circuit that is suitable for C conversion and is less susceptible to disturbance.

Means for Solving the Problems In order to achieve the above object, the present invention makes it possible to continuously vary the drive current of the charge pump, changes the drive current depending on the state of synchronous pull-in of the PLL circuit, and achieves an isometric loop gain. The loop characteristics at the time of pulling in and locking are changed by changing .

According to the present invention, the filter constant is not changed when changing the mode, but the loop gain is changed by continuously changing the drive current of the charge pump.
It has the advantage of being less likely to cause disturbance to the system, and since the switching circuit is a charge pump, it is suitable for IC implementation.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, 1 is a reference oscillator, the output of which is input to a frequency divider 2, and the output of frequency divider 2 is added as a reference input to a phase comparator 3. The two phase lag and lead outputs (a) and (bl) of the phase comparator 3 are input to the variable current charge pump 11, and the output of the variable current charge pump 11 is passed through the filter 12 to the voltage controlled oscillator 6.
has been entered. The output of voltage controlled oscillator 6 is used as output 9 and is simultaneously input to frequency divider 8 . Further, the output of the frequency divider 8 is input to the comparison input of the phase comparator 3. A pair of control signals (e) and (dj) for controlling the variable current charge pump 11 is a mode in which the phase lock signal 10 of the phase comparator 3 is connected in series with a buffer amplifier 14, an integrator 15, and a polarity converter 16. It is designed to be obtained as the output of the control generation signal circuit 13.The integrator 15 may be a simple connection of a resistor and a capacitor, or may have a more complicated configuration.Also, the polarity converter 16 obtains the output of the integrator 15 as it is or inverts it by the inverter 16a to obtain an output of opposite phase,
It is sufficient to take out the output (d) or (ei), respectively.

Next, the operation of the above embodiment will be explained. The basic operation as a PLL circuit is the same as the conventional example. The phase lock signal 10 of the phase comparator 3 is obtained as a pulse signal whose pulse width changes depending on the lock state of the PLL circuit. This is input to the integrator 15 via the buffer amplifier 14, and the output of the integrator 15 is partially inverted by the polarity converter 16 to obtain a pair of outputs (d) and (e), which can be changed with current. In addition to being added as a control input to the charge pump, the drive current of the variable current charge pump 11 is continuously changed depending on the lock state to change the loop characteristics of the PLL.

FIG. 2 shows a concrete structure of the variable current charge pump 11, which is a current mirror circuit as a pair of constant current sources, which are connected by two PNP or NPN transistors and a resistor. The current mirror circuit 14a is composed of transistors 15a l 16a and a resistor 17a, and the same current i flows through the transistor 13a when it is output from the terminal d. Similarly, the current mirror circuit 14b includes transistors 15b, 16b,
It is composed of a resistor 17b. Therefore, the two outputs of the phase comparator 3, phase lag and phase lead, are input to the terminals (a) and (b), and the charge pump output (C
1 is obtained.

FIG. 3 is an example using a pair of differential amplifiers as means for realizing another constant current source. 20a and 20b are differential amplifiers each using two PNP or NPN) transistors, and in the differential amplifier 20a, 213 to 2
4a is a resistor 25a that determines bias conditions.

26a is a pair of PNP transistors, similarly in the differential amplifier 20b, 21b to 24b are resistors, 25b, 2
6b is an NPN transistor, and 27.28 is a differential amplifier 20a.

20b. In the above configuration, one transistor 25a of the differential amplifiers 20a and 20b.

The output (d) of the mode signal generation circuit 13 is connected to the base of 25b.
.

(e) by connecting it to transistor 26a.

The current of 26b can be continuously and variably controlled.

Effects of the Invention As explained above with reference to the embodiments, according to the present invention, a phase lock signal from a phase comparator is applied via an integrator to a terminal that controls the constant current value of a charge pump driven with a constant current. Since it is configured to do this, it is possible to continuously change the drive current according to the synchronous pull-in state of the PLL circuit, and to continuously change the loop gain. It has the advantage of being able to respond more precisely. Further, since no external switch is required, it is suitable for IC implementation, and it has the advantage that it is less likely to cause disturbances because it does not switch the line directly connected to the voltage controlled oscillator.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional PLL circuit that is continuously variable according to an embodiment of the present invention. l... Reference oscillator, 3... Phase comparator, 6... Voltage controlled oscillator, 11... Variable current charge pump,
13...Mode control signal generation circuit, 15...Integrator, 16...Polarity converter.

Claims (1)

[Claims] It is used in a phase-locked loop circuit comprising a digital phase comparator, a charge pump driven by the output of the phase comparator, and a voltage controlled oscillator controlled by the output of the charge pump via a low-pass filter. , an integrator that integrates the phase lock signal of the phase comparator, and a pair of constant current sources whose current value is controlled by the output of the integrator, and the drive current of the charge pump is made to correspond to the lock state. Continuously variable mode PLL circuit for continuously variable control.