JPS6292521A - Two-mode pll circuit - Google Patents

Abstract

PURPOSE:To make high speed rise compatible with a high noise suppression characteristic by varying a drive current of a charge pump corresponding to the mode so as to change an equivalent loop gain. CONSTITUTION:An output of a reference oscillator 1 is frequency-divided (2), and the result is fed to a phase comparator 3 as a reference input. Then two phase lag/lead outputs of the comparator 3 are inputted to the charge pump 11, and its output is fed to a voltage controlled oscillator 6 via a filter 12, an output 9 is given from the oscillator 6 and fed to the comparator 3 via a frequency divider 8. In turning on/off a switch 5 of the pump 11, the drive current of the change pump 9 is changed. When the switch 5 is turned on by a phase lock signal 10, the pull-in locking of a phase locked loop PLL is realized quickly. When being locked, the switch 5 is opened and the natural frequency omegan is decreased, then the noise suppression and stability are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a two-mode PT,L (phase-locked loop) circuit for use in frequency synthesizers and the like.

BACKGROUND OF THE INVENTION FIG. 2 shows the configuration of a conventional two-moto PLL circuit. In Figure 2, (1) is a reference oscillator, the output of which is input to the frequency divider (2), and the output of the frequency divider (2) is added as the reference input to the phase comparator (3). There is.

Two outputs, phase lag and phase lead, of the phase comparator (3) are input to a charge pump (4), and a phase lock signal 00) from the phase comparator serves as a control signal for the switch (5). The output of the charge pump (, 4) is input to a low-pass filter (7), and the characteristics of the low-pass filter (7) can be varied by a switch (5). The output of the low-pass filter (7) is input to a voltage controlled oscillator (6), and the output of the voltage controlled oscillator (6) is used as an output (9) and simultaneously input to a frequency divider (8). Also, the output of the frequency divider (8) is sent to the phase comparator (3).
is entered in the comparison input of

Next, the operation of the above conventional example will be explained. In Fig. 1, except for the switch (5), it is a normally used phase-locked loop circuit. If the frequency division ratio of 8) is N, the frequency fO of the output (9) is expressed by fO-MfR.

Here, frequency dividers (2) and (8) are made variable frequency dividers, and N.

By changing the value of M, the output frequency fo can be changed. The characteristics of this loop can be expressed by the loop gain and the transfer characteristics of the low-pass filter (7), and if an RC filter as shown in FIG. 1 is used as the low-pass filter (7), the loop becomes a second-order loop.

At this time, the power supply voltage of the charge pump is Vp, Vc.

Let KV be the modulation sensitivity of ωn, which determines the PLL response.
(natural frequency) and ζ (dampink coefficient) are expressed by the following equation.

From this, if R2 is shorted with switch (5), ω
As n becomes larger and the natural frequency of the PLL increases, the response of the system becomes faster. Therefore, when the PLL is not locked, if the switch (5) is turned on by the phase lock signal α, the PLL can be pulled into synchronization more quickly. Furthermore, when locked, the switch (5) is open and ωn becomes small, which is advantageous in terms of noise suppression and stability. By switching the filter characteristics in this way, it is possible to achieve both high-speed rise and high noise suppression characteristics.

Problems to be Solved by the Invention However, in the conventional two-mode PLL circuit described above, since the transfer function of the filter is changed by a switch depending on the mode, it is necessary to externally attach a switch when converting the above circuit into an IC. Although the circuit was miniaturized, it had some serious drawbacks.

Further, there is a drawback that the switch tends to cause disturbance to the voltage controlled oscillator.

The present invention solves these conventional drawbacks.I
Excellent 2-mode PLL that is suitable for C conversion and does not easily cause disturbance.
The purpose is to provide a circuit.

Means for Solving the Problems In order to achieve the above object, the present invention makes it possible to vary the drive current of the charge pump, switches the drive current depending on the mode, and changes the isometric loop gain, thereby improving the power supply during pull-in. It is configured to change the loop characteristics when locked.

Therefore, according to the present invention, when switching the mode, the filter constant is not changed, but the loop cane is changed by switching the drive current of the charge pump. Since it is a pump, it has the advantage of being suitable for IC implementation.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In Figure 1, (1) is the reference oscillator, whose output is (
2), and the output of the frequency divider (2) is added as a reference input to a phase comparator (3). The two phase lag and lead outputs of the phase comparator (3) are input to a charge pump α]), and the output of the charge pump 01) is input to a voltage controlled oscillator (6) via a filter (13). The output of the voltage controlled oscillator (6) is the output (9
) and is simultaneously input to the frequency divider (8). Furthermore, the output of the frequency divider (8) is input to the comparison input of the phase comparator (3).

The charge pump α1) has a base and a phase comparator (
3) and has a resistance Rs between the ground and the ground. NPN and P
Consisting of a pair of NP transistors, a switch (5) is inserted between two ends of one of the two resistors Rx and Rz connected to the emitters of each, R2, and the switch (5) is phase-locked. It is controlled by signal 00).

Next, the operation of the above embodiment will be explained. This actual flow side is also the same as the conventional example except for the configuration of the charge pump 01) and the position of the switch (5), and the PLL of the secondary loop
The frequency divider (2) and the frequency divider (8) output a frequency determined by the division ratios of the frequency divider (2) and the frequency divider (8). Switch (5) is now OFF
, then the PLL loop characteristics ωna, ζa
is expressed by the following equation. However, the voltage across the base of the Tr is VBE.

yyofl At this time, the drive current of the charge pump is. (R□+R2)
It is. Furthermore, when the switch (5) is ON, ωn
b.

ζb is It is expressed as

Also, at this time, the drive current OF of the charge pump α1)
By changing F, the drive current of the charge pump changes,
As a result, it can be seen that the response of the system changes. Therefore, as in the conventional example, if the switch (5) is driven with the phase lock signal 00), ωn is small during synchronization and the noise band is narrow.
Further, at the time of synchronous pull-in, a two-mode PLL with a large ωn and a fast response speed can be realized.

When the synchronization time was actually measured using the above configuration, the synchronization time was 37m5 with a normal PLL, but the synchronization time was less than 25m5, which was an increase of more than 30 times.

Effects of the Invention As is clear from the above embodiments, the present invention has the advantage that the response of the system is varied by switching charge pumps, and that it can be easily integrated into an IC. Furthermore, since the line directly connected to the voltage controlled oscillator is not switched, it has the advantage of being less likely to cause disturbance. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of a two-mode filter according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional two-mode filter. (1)... Reference oscillator, (2)... Frequency divider, (3)...
・Phase comparator, (4) ・Charge pump, (5)...
Switch, (6)... Voltage controlled oscillator, (Katana... Low pass filter, (8)... Frequency divider, (9)... Output, 00)... Phase lock signal, (11) ...Charge pump, (12...Filter. Name of agent: Patent attorney Toshi Nakao, male, 1st person)
figure

Claims (2)

[Claims] (1) A phase-locked loop circuit comprising a digital phase comparator, a charge pump driven by the output of the phase comparator, and a voltage-controlled oscillator controlled by the output of the charge pump via a low-pass filter. A two-mode PLL circuit used in a 2-mode PLL circuit in which the drive current of the charge pump is made variable in accordance with the mode. (2) The charge pump is composed of a pair of NPN and PNP transistors whose collectors are connected together, and the NPN
and PNP transistors, the respective bases of which are connected to the output of the phase comparator, and the PNP and NPN
The two-mode PL according to claim 1, wherein the resistance value connected to each emitter of the transistor is switched in response to a phase lock signal of the phase comparator.
L circuit.