JPH04192625A - Pll frequency synthesizer - Google Patents
Pll frequency synthesizerInfo
- Publication number
- JPH04192625A JPH04192625A JP2318629A JP31862990A JPH04192625A JP H04192625 A JPH04192625 A JP H04192625A JP 2318629 A JP2318629 A JP 2318629A JP 31862990 A JP31862990 A JP 31862990A JP H04192625 A JPH04192625 A JP H04192625A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- current
- output
- charge pump
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007599 discharging Methods 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000003111 delayed effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＰＬＬ周波数シンセサイザに関し、特に出力の
周波数を高速で切換えるＰＬＬ周波数シンセサイザに関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PLL frequency synthesizer, and particularly to a PLL frequency synthesizer that switches the output frequency at high speed.
〔従来の技術］
従来のＰＬＬ周波数シンセサイザにおいて、周波数の切
り換えを高速に行い、かつ切り換え後の動作の安定化を
図る技術として、例えば第５図に示すようなものがある
（特開昭６１−１３４１２６号）。[Prior Art] In a conventional PLL frequency synthesizer, there is a technique shown in FIG. 5, for example, as a technique for performing frequency switching at high speed and stabilizing the operation after switching. No. 134126).
“すなわち、第５図はＰＬＬ周波数シンセサイザのルー
プフィルタの構成であり、入力端子４１と出力端子４２
との間に直列に抵抗４３を、並列に抵抗４４とコンデン
サ４５を接続している。そして、抵抗４３と並列に可変
抵抗４６と抵抗４７を接続し、抵抗４４と並列に可変抵
抗４８と抵抗４９を接続している。さらに、可変抵抗４
６．４８には抵抗値制御回路５０を接続し、制御端子５
１に入力される制御信号によって抵抗値制御回路５０が
可変抵抗４６．４８を制御するようになっている。"In other words, FIG. 5 shows the configuration of a loop filter of a PLL frequency synthesizer, with an input terminal 41 and an output terminal 42.
A resistor 43 is connected in series between the two, and a resistor 44 and a capacitor 45 are connected in parallel. A variable resistor 46 and a resistor 47 are connected in parallel with the resistor 43, and a variable resistor 48 and a resistor 49 are connected in parallel with the resistor 44. Furthermore, variable resistor 4
The resistance value control circuit 50 is connected to 6.48, and the control terminal 5
The resistance value control circuit 50 controls the variable resistors 46 and 48 according to the control signal input to the resistor 1.
この構成では、周波数が安定している場合には、制御端
子５１に入力される制御信号に応じて抵抗値制御回路５
０は可変抵抗４６．４８をオープンにし、ループフィル
タは抵抗４３，４４、コンデンサ４５にて構成される。In this configuration, when the frequency is stable, the resistance value control circuit 5
0, the variable resistors 46 and 48 are open, and the loop filter is composed of resistors 43 and 44 and a capacitor 45.
これは周波数が安定になる定数が選ばれる。A constant is selected that makes the frequency stable.
一方、周波数切換時には、抵抗値制御回路５゜は可変抵
抗４６．４８をショートにするように動作し、高速に周
波数を引込むように選ばれた抵抗４７．４９を抵抗４３
．４４に並列接続することで高速引込みを行う。そして
、引込み完了時には、抵抗値制御回路５０が可変抵抗４
６．４８の抵抗値を徐々にに大きくしていき、最終的に
オープになるよう制御する。これにより、高速な引込み
を可能とし、かつ引込み完了後は、安定に動作するＰＬ
Ｌ周波数シンセサイザを実現している。On the other hand, at the time of frequency switching, the resistance value control circuit 5° operates to short-circuit the variable resistor 46.48, and connects the resistor 47.49 to the resistor 43, which is selected to draw in the frequency at high speed.
．． 44 in parallel to perform high-speed retraction. Then, when the retraction is completed, the resistance value control circuit 50 controls the variable resistor 4.
The resistance value of 6.48 is gradually increased and controlled so that it finally becomes open. This enables high-speed retraction, and after the retraction is completed, the PL operates stably.
This realizes an L frequency synthesizer.
〔発明が解決しようとする課題〕
従来のＰＬＬ周波数シンセサイザにおいては、周波数の
引込みが完了した時点で、高抵抗に切換えを行うように
なっているが、チャージポンプからみた場合、軽い負荷
から重い負荷に変わるようになっている。[Problem to be solved by the invention] In conventional PLL frequency synthesizers, the switch is made to high resistance when frequency pull-in is completed, but when viewed from the charge pump, the load changes from light to heavy. It is set to change to
実際にチャージポンプを構成する場合、負荷によってチ
ャージポンプのドライブ能力が大幅に変わってしまう。When actually configuring a charge pump, the drive ability of the charge pump changes significantly depending on the load.
この場合、重い負荷がつく事でチャージポンプのドライ
ブ能力は落ちてしまい、デッドゾーンを生じてしまう可
能性が高い。In this case, the drive ability of the charge pump decreases due to the heavy load, and there is a high possibility that a dead zone will occur.
また、切換え時において、ループフィルタにチャージも
しくはディスチャージがなされていると、抵抗値を変え
ることで電圧制御発振器に与えられる電圧値が僅かなが
ら変化する。電圧制御発振器の変調怒度が高い場合、こ
の切換えにより周波数が変動してしまう。Further, if the loop filter is being charged or discharged at the time of switching, changing the resistance value slightly changes the voltage value applied to the voltage controlled oscillator. If the modulation intensity of the voltage controlled oscillator is high, the frequency will fluctuate due to this switching.
さらに、■ＣＯに電圧を与えるラインすなわちＬＦの出
力は通常高いインピーダンスを持っているため、このラ
インにスイッチング素子を入れると、そのコントロール
電圧がもれ込む可能性が高い。Furthermore, since the line that supplies voltage to CO, that is, the output of LF, usually has a high impedance, if a switching element is inserted into this line, there is a high possibility that the control voltage will leak into it.
本発明の目的は高速切換えを可能とする一方で、切換え
後の周波数の安定性を高めたＰＬＬ周波数シンセサイザ
を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a PLL frequency synthesizer that enables high-speed switching while improving frequency stability after switching.
本発明のＰＬＬ周波数シンセサイザは、電圧制御発振器
の出力と基準周波数発生器の出力の位相および周波数の
ずれを位相周波数比較器で検出し、その位相の進み、遅
れに応じた信号出力によって電流をチャージし、あるい
は電流をディスチャージするチャージポンプを備えたＰ
、Ｌ Ｌ周波数シンセサイザに、チャージポンプのチ
ャージ時およびディスチャージ時の電流を連続的に変化
させる電流量制御回路を設けている。The PLL frequency synthesizer of the present invention detects the phase and frequency deviation between the output of the voltage controlled oscillator and the output of the reference frequency generator using a phase frequency comparator, and charges a current by outputting a signal according to the lead or lag of the phase. or a P with a charge pump to discharge the current.
, L L frequency synthesizer is provided with a current amount control circuit that continuously changes the current during charging and discharging of the charge pump.
この場合、電流量制御回路は、周波数切換時に電流を増
大させ、その後徐々に電流を低減させるように構成され
る。In this case, the current amount control circuit is configured to increase the current at the time of frequency switching, and then gradually reduce the current.
本発明によれば、電流量制御回路によって周波数切換え
時にチャージポンプの電流を増加させることで引き込み
を速くし、また切換え後にチャージポンプの出力電流を
減少させることで安定化を確保する。According to the present invention, the current amount control circuit increases the current of the charge pump at the time of frequency switching to speed up the draw-in, and reduces the output current of the charge pump after switching to ensure stability.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例のプロ・ンク図である。FIG. 1 is a diagram of one embodiment of the present invention.
電圧制御発振器１の出力は出力端子１０に出力される一
方で一部は可変周波数分周器２に入力され、分周数入力
端子８に入力される分周数入力に応じて周波数分周器２
によって所要の周波数に分周される。分周された信号は
、基準周波数発生器３で発生される基準周波数信号と共
に位相周波数比較器４に入力されて位相および周波数が
比較され、比較結果として遅れ情報Ｓ１と進み情報Ｓ２
が出力される。チャージポンプ５は、進み情報Ｓ２がＨ
ｉｇｈの場合にディスチャージ状態となり、遅れ情報Ｓ
１が旧ｇｈの場合にチャージを行う。このとき、電流量
設定値入力端子９から入力された電流量設定値に応じて
電流量制御回路６により設定されるディスチャージ電流
量あるいはチャージ電流量にてチャージ、ディスチャー
ジを行う。このチャージポンプ５の出力はループフィル
タ７にて積分、平滑化され、前記電圧制御発振器１にフ
ィードバックされる。The output of the voltage controlled oscillator 1 is output to the output terminal 10, while a portion is input to the variable frequency divider 2, which divides the frequency according to the division number input to the division number input terminal 8. 2
The frequency is divided into the required frequency by The frequency-divided signal is input to the phase frequency comparator 4 together with the reference frequency signal generated by the reference frequency generator 3, and the phase and frequency are compared, and the comparison result is delay information S1 and advance information S2.
is output. The charge pump 5 has advance information S2 of H
If it is high, it becomes a discharge state and the delay information S
If 1 is the old GH, charge it. At this time, charging and discharging are performed with a discharge current amount or a charge current amount set by the current amount control circuit 6 according to the current amount setting value inputted from the current amount setting value input terminal 9. The output of this charge pump 5 is integrated and smoothed by a loop filter 7 and fed back to the voltage controlled oscillator 1.
このＰＬＬ周波数シンセサイザでは、周波数切換え時に
は分周数入力端子８より入力される分周数を変えると共
に、電流量制御回路６から出力されるディスチャージ電
流量あるいはチャージ電流量を増やすような電流量設定
値を電流量設定値入力端子９から入力する。In this PLL frequency synthesizer, when changing the frequency, the frequency division number input from the frequency division number input terminal 8 is changed, and the current amount setting value is set to increase the discharge current amount or charge current amount output from the current amount control circuit 6. is input from the current amount setting value input terminal 9.
その後、時間的に連続にチャージポンプ５の出力の電流
量を落とすように電流量設定値入力端子９より制御する
。これにより切換えで大幅に周波数がずれている時は、
高速に引込み、引込みが完了すると周波数を安定に出力
できる。Thereafter, the current amount set value input terminal 9 is used to control the current amount of the output of the charge pump 5 to be reduced continuously over time. As a result, when the frequency is significantly shifted due to switching,
It pulls in at high speed, and when the pull-in is completed, the frequency can be output stably.
第２図は前記電流量制御回路６の一例の回路図である。FIG. 2 is a circuit diagram of an example of the current amount control circuit 6.
同図において、１１は電流量設定値が入力される入力端
子（第１図の電流量設定値入力端子９に相当）であり、
ここにはスイ・７チング信号が加えられる。また、１２
は電源端子であり、オン状態の時には電圧ＶＤｌ＋が供
給される。さらに、１３は前記チャージポンプ５に対し
てディスチャージ電流量あるいはチャージ電流量を出力
する出力端子である。In the figure, 11 is an input terminal to which a current amount setting value is input (corresponding to the current amount setting value input terminal 9 in FIG. 1),
A switching signal is added here. Also, 12
is a power supply terminal, to which voltage VDl+ is supplied when in the on state. Furthermore, 13 is an output terminal for outputting a discharge current amount or a charge current amount to the charge pump 5.
この回路は、スイッチング素子１４と、オペアンプ１５
と、ｎチャンネルＭＯ３ＦＥＴ１６と、２個のｐチャン
ネルＭＯ５ＦＥＴ１７．１８と、抵抗１９，２０．２１
と、コンデンサ２２とで構成される。そして、抵抗２０
には電源電圧が加えられ、この電圧によりコンデンサ２
２はチャージアップされる。また、電源電圧はオペアン
プ１５の非反転入力に加えられる。ｎチャンネルＭＯ３
ＦＥＴ１６のソースがオペアンプ１５の反転入力に接続
されており、非反転入力の電源電圧は、ｎチャンネルＭ
Ｏ３ＦＥＴ１６のソース電圧と等しくなり、抵抗１９の
抵抗値をＲＩ、とおくと、ドレイン電流がＶｖｏ／Ｒｔ
ｑ流れる。This circuit includes a switching element 14 and an operational amplifier 15.
, n-channel MO3FET 16, two p-channel MO5FETs 17.18, and resistors 19, 20.21.
and a capacitor 22. And resistance 20
A power supply voltage is applied to the capacitor 2, and this voltage causes the capacitor 2 to
2 is charged up. Further, the power supply voltage is applied to the non-inverting input of the operational amplifier 15. n channel MO3
The source of the FET 16 is connected to the inverting input of the operational amplifier 15, and the power supply voltage of the non-inverting input is the n-channel M
If it becomes equal to the source voltage of O3FET 16 and the resistance value of resistor 19 is set as RI, then the drain current becomes Vvo/Rt.
q flows.
また、ｐチャンネルＭＯ３’ＦＥＴ１７．１Ｂは、カレ
ントミラー回路を構成しており、ｐチャンネルＭＯＳＦ
ＥＴ１Ｂのゲート幅はｐチャンネルＭＯ３ＦＥＴ１７の
Ｎ倍にされている。これにより、ｎチャンネルＭＯ３Ｆ
ＥＴ１６のドレイン電流はＮ倍され、ｐチャンネルＭＯ
ＳＦＥＴ１Ｂのドレイン電流となり、出力端子１３に出
力される。In addition, the p-channel MO3'FET17.1B constitutes a current mirror circuit, and the p-channel MOSFET17.1B constitutes a current mirror circuit.
The gate width of ET1B is N times that of p-channel MO3FET17. This allows n-channel MO3F
The drain current of ET16 is multiplied by N and the p-channel MO
This becomes the drain current of SFET 1B and is output to the output terminal 13.
オン状態からオフ状態に変化させると、オペアンプの非
反転入力の電圧は、抵抗２１の抵抗値が非常に大きい場
合、コンデンサ２２の電圧が抵抗２０を通ってディスチ
ャージされるため、指数関数的に低下し、抵抗２０の抵
抗値をＲ２゜、抵抗２１の抵抗値をＲ２ｌとおくと、（
Ｒ２゜／Ｒ，。＋Ｒ２１）・ＶＯＯに収束する。オン状
態と同し原理で出力端子３にはＮ／Ｒ１９倍された電流
値として伝わる。When changing from the on state to the off state, the voltage at the non-inverting input of the operational amplifier will drop exponentially because the voltage on the capacitor 22 will be discharged through the resistor 20 if the resistance value of the resistor 21 is very large. However, if the resistance value of the resistor 20 is R2° and the resistance value of the resistor 21 is R2l, then (
R2°/R,. +R21)・Converges to VOO. Based on the same principle as in the on state, a current value multiplied by N/R19 is transmitted to the output terminal 3.
第３図（ａ）ないしくＣ）に入力端子１１、ｎチャンネ
ルＭＯ３ＦＥＴ１６のドレイン電流、出力端子１３の各
電圧波形図を示す。FIGS. 3(a) to 3(c) show respective voltage waveform diagrams of the input terminal 11, the drain current of the n-channel MO3FET 16, and the output terminal 13.
なお、これはチャージアップする回路であるが、ディス
チャージする場合には第２図のｎチャンネルＭＯ３ＦＥ
Ｔ１６をＰチャンネルに、ｐチャンネルのＭＯ３ＦＥＴ
１７．１８をｎチャンネルに置換え、さらに抵抗１９の
グランド側を電源１２に、ＰチャネルＭＯ３ＦＥＴ１７
．１８のソースをグランドにそれぞれ接続すればよい。Note that this is a charge-up circuit, but when discharging, use the n-channel MO3FE shown in Figure 2.
T16 to P channel, p channel MO3FET
17. Replace 18 with an n-channel, and connect the ground side of the resistor 19 to the power supply 12, and connect the P-channel MO3FET 17.
．． It is sufficient to connect each of the 18 sources to ground.
第４図は前記チャージポンプの一例である。ここではｐ
チャンネルＭＯ５ＦＥＴ３６とｎチャンネルＭＯ３ＦＥ
Ｔ３７とでＣＭＯ３構造に構成し、これに遅れ位相入力
端子３１、進み位相入力端子３２、チャージアップ入力
端子３３、ディスチャージ出力端子３４、チャージ出力
端子３５を接続している。FIG. 4 shows an example of the charge pump. Here p
Channel MO5FET36 and n-channel MO3FE
T37 constitutes a CMO3 structure, and a delayed phase input terminal 31, an advanced phase input terminal 32, a charge up input terminal 33, a discharge output terminal 34, and a charge output terminal 35 are connected to this.
このチャージポンプでは、端子３１の遅れ位相入力が旧
ｇｈになると、ＰチャネルＭＯＳ Ｆ ＥＴ ３６を介
してチャージアンプ入力端子３３から電流が流込み、端
子３２の進み位相人力が旧ｇｈになると、ｎチャネルＭ
Ｏ３ＦＥＴ３７を介してディスチャージ出力３４から電
流が流れ出る。In this charge pump, when the delayed phase input at the terminal 31 becomes the old gh, a current flows from the charge amplifier input terminal 33 via the P channel MOS FET 36, and when the leading phase input at the terminal 32 becomes the old gh Channel M
Current flows out of the discharge output 34 via the O3FET 37.
以上説明したように本発明は、電流量制御回路を設けて
チャージポンプへの電流量を制御するように構成してい
るので、周波数切換え時にチャージポンプの電流を増加
させることで引き込みを速くし、また切換え後にチャー
ジポンプの出力電流を減少させることで安定化を確保す
ることができる効果がある。As explained above, the present invention is configured to include a current amount control circuit to control the amount of current to the charge pump, so that by increasing the current of the charge pump at the time of frequency switching, the drawing speed is increased. Further, by reducing the output current of the charge pump after switching, stabilization can be ensured.
第１図は本発明の一実施例のブロック図、第２図は電流
量制御回路の一例の回路図、第３図はその電圧波形図、
第４図はチャージポンプの回路図、第５図は従来のＰＬ
Ｌ周波数シンセサイザにおけるループフィルタの回路図
である。
１・・・電圧制御発振器、２・・・可変周波数分周器、
３・・・基準周波数発生器、４・・・位相周波数比較器
、５・・・チャージポンプ、６・・・電流制御回路、７
・・・ループフィルタ、８・・・分周数入力、９・・・
電流量設定値入力端子、１０・・・出力端子、１１・・
・電流量設定値入力端子、１２・・・電源端子、１３・
・・出力端子、１４・・・スイッチング素子、１５・・
・オペアンプ、１６−ｎチャンネルＭＯ３ＦＥＴ、１７
．１８・・・Ｐチャンネル間Ｏ３ＦＥＴ、１９，２０．
２１・・・抵抗、２２・・・コンデンサ、３１・・・遅
れ位相入力端子、３２・・・進み位相入力端子、３３・
・・チャージアップ入力端子、３４・・・ディスチャー
ジ出力端子、３５・・・チャージ出力端子、３６・・・
Ｐチャンネル間Ｏ３ＦＥＴ、３７− ｎチャンネルＭＯ
３ＦＥＴ、４１・・・入力端子、４２・・・出力端子、
４３．４４・・−抵抗、４５・・・コンデンサ４５．４
６・・・可変抵抗、４７・・・抵抗、４８・・・可変抵
抗、４９・・・抵抗、５０・・・抵抗値制御回路、５１
・・・制御端子。
第１図
電流量に泡省入カ＃＃ｐ＋
第２図
第３図
ｔ（−す＾ｎ）FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of an example of a current amount control circuit, and FIG. 3 is a voltage waveform diagram thereof.
Figure 4 is the circuit diagram of the charge pump, Figure 5 is the conventional PL
FIG. 3 is a circuit diagram of a loop filter in an L frequency synthesizer. 1... Voltage controlled oscillator, 2... Variable frequency divider,
3... Reference frequency generator, 4... Phase frequency comparator, 5... Charge pump, 6... Current control circuit, 7
...Loop filter, 8...Divide number input, 9...
Current amount setting value input terminal, 10... Output terminal, 11...
・Current amount setting value input terminal, 12...Power supply terminal, 13・
...Output terminal, 14...Switching element, 15...
・Operational amplifier, 16-n channel MO3FET, 17
．． 18...P-channel O3FET, 19,20.
21... Resistor, 22... Capacitor, 31... Lagging phase input terminal, 32... Leading phase input terminal, 33...
...Charge up input terminal, 34...Discharge output terminal, 35...Charge output terminal, 36...
P-channel O3FET, 37-n channel MO
3FET, 41...input terminal, 42...output terminal,
43.44...-Resistor, 45...Capacitor 45.4
6... Variable resistor, 47... Resistor, 48... Variable resistor, 49... Resistor, 50... Resistance value control circuit, 51
...Control terminal. Figure 1: Bubbles are added to the current amount ##p+ Figure 2: Figure 3 t(-su^n)
Claims (1)
周する可変周波数分周器と、基準周波数信号を出力する
基準周波数発生器と、この基準周波数出力と分周出力の
位相および周波数のずれを検出し、位相の進み、遅れに
応じた信号を出力する位相周波数比較器と、この位相周
波数比較器の出力を遅れの場合には電流をチャージし、
進みの場合には電流をディスチャージするチャージポン
プと、このチャージポンプの出力を積分し、平滑化する
ループフィルタと、前記チャージポンプのチャージ時お
よびディスチャージ時の電流を連続的に変化させる電流
量制御回路を備えたことを特徴とするＰＬＬ周波数シン
セサイザ。２、電流量制御回路は、周波数切換時に電流
を増大させ、その後徐々に電流を低減させるように構成
される特許請求の範囲第１項記載のＰＬＬ周波数シンセ
サイザ。1. A voltage controlled oscillator, a variable frequency divider that divides the output of this voltage controlled oscillator, a reference frequency generator that outputs a reference frequency signal, and a phase and frequency shift between the reference frequency output and the divided output. A phase frequency comparator that detects the phase and outputs a signal according to the phase lead or lag, and charges a current to the output of this phase frequency comparator in the case of a lag,
A charge pump that discharges the current in the case of a lead, a loop filter that integrates and smoothes the output of this charge pump, and a current amount control circuit that continuously changes the current of the charge pump during charging and discharging. A PLL frequency synthesizer characterized by comprising: 2. The PLL frequency synthesizer according to claim 1, wherein the current amount control circuit is configured to increase the current at the time of frequency switching and then gradually reduce the current.
Priority Applications (12)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2318629A JP2927937B2 (en) | 1990-11-24 | 1990-11-24 | PLL frequency synthesizer |
| DE69130046T DE69130046T2 (en) | 1990-10-22 | 1991-10-17 | Frequency synthesizer with PLL, which enables a frequency change of the output at high speed |
| EP91309560A EP0482823B1 (en) | 1990-10-22 | 1991-10-17 | PLL frequency synthesizer capable of changing an output frequency at a high speed |
| EP97204136A EP0840457A3 (en) | 1990-10-22 | 1991-10-17 | PLL frequency synthesizer capable of changing an output frequency at a high speed |
| EP97204137A EP0840456A3 (en) | 1990-10-22 | 1991-10-17 | PLL frequency synthesizer capable of changing an output frequency at a high speed |
| CA002053748A CA2053748C (en) | 1990-10-22 | 1991-10-18 | Pll frequency synthesizer capable of changing an output frequency at a high speed |
| CA002122637A CA2122637C (en) | 1990-10-22 | 1991-10-18 | Pll frequency synthesizer capable of changing an output frequency at a high speed |
| CA002122643A CA2122643C (en) | 1990-10-22 | 1991-10-18 | Pll frequency synthesizer capable of changing an output frequency at a high speed |
| AU86021/91A AU642536B2 (en) | 1990-10-22 | 1991-10-21 | PLL frequency synthesizer capable of changing an output frequency at a high speed |
| US07/781,093 US5173665A (en) | 1990-10-22 | 1991-10-22 | Pll frequency synthesizer capable of changing an output frequency at a high speed |
| US07/933,990 US5247265A (en) | 1990-10-22 | 1992-08-21 | PLL frequency synthesizer capable of changing an output frequency at a high speed |
| US07/933,988 US5276408A (en) | 1990-10-22 | 1992-08-21 | PLL frequency synthesizer capable of changing an output frequency at a high speed |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2318629A JP2927937B2 (en) | 1990-11-24 | 1990-11-24 | PLL frequency synthesizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04192625A true JPH04192625A (en) | 1992-07-10 |
| JP2927937B2 JP2927937B2 (en) | 1999-07-28 |
Family
ID=18101272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2318629A Expired - Fee Related JP2927937B2 (en) | 1990-10-22 | 1990-11-24 | PLL frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2927937B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5831483A (en) * | 1996-01-30 | 1998-11-03 | Nec Corporation | PLL frequency synthesizer having circuit for controlling gain of charge pump circuit |
| KR100907001B1 (en) * | 2007-07-11 | 2009-07-08 | 주식회사 하이닉스반도체 | PLL Circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5941327A (en) * | 1982-09-01 | 1984-03-07 | Teijin Ltd | Polyester electrical insulating material |
| JPS6390215A (en) * | 1986-10-03 | 1988-04-21 | Matsushita Electric Ind Co Ltd | Continuous variable mode pll circuit |
| JPH02113726A (en) * | 1988-10-24 | 1990-04-25 | Fujitsu Ltd | Pll circuit |
-
1990
- 1990-11-24 JP JP2318629A patent/JP2927937B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5941327A (en) * | 1982-09-01 | 1984-03-07 | Teijin Ltd | Polyester electrical insulating material |
| JPS6390215A (en) * | 1986-10-03 | 1988-04-21 | Matsushita Electric Ind Co Ltd | Continuous variable mode pll circuit |
| JPH02113726A (en) * | 1988-10-24 | 1990-04-25 | Fujitsu Ltd | Pll circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5831483A (en) * | 1996-01-30 | 1998-11-03 | Nec Corporation | PLL frequency synthesizer having circuit for controlling gain of charge pump circuit |
| KR100907001B1 (en) * | 2007-07-11 | 2009-07-08 | 주식회사 하이닉스반도체 | PLL Circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2927937B2 (en) | 1999-07-28 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |