KR100233275B1 - Charge pump of phase locked loop - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump of a phase locked loop that can prevent unstable operation caused by noise from outside or inside itself after a fixed frequency, and includes a pull-up transistor for passing a current of a power supply by a voltage applied to a gate. A pull-down transistor for passing a current through a voltage applied to the gate and applying it to ground; voltage control means for controlling the distribution of the voltage applied to the gate of the pull-up transistor and the pull-down transistor and the magnitude of the voltage; A first switching means connected between the transistors, the first switching means for outputting a predetermined current applied to the output terminal by being turned on / off by an up signal and an inverting up signal to the output terminal; Connected between transistors, on / off by down signal and inverted down signal It is a second switching means for applying a predetermined electric current flows to the output terminal to ground.

Description

Charge pump in phase locked loop

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (PLL), and more particularly to a charge pump of a phase locked loop capable of preventing unstable operation due to noise from outside or inside itself after a frequency is fixed.

In general, the phase-locked loop divides a reference frequency input from the outside and fixes the frequency to a desired frequency. For example, the phase locked loop divides a frequency of 10 MHz input from the outside and fixes it at a frequency of 100 MHz. Therefore, phase locked loops have been mainly used in semiconductor devices that require high-speed synchronous operation.

A general phase locked loop will be described with reference to FIG.

Referring to FIG. 1, a general phase-locked loop compares a phase of a frequency returned from a voltage controlled oscillator 4 to a reference frequency inputted to a reference frequency oscillator (not shown) and a type force stage to one input stage. A phase frequency detector 1 for outputting an error signal of a charge, a charge pump 2 for charging and discharging according to an error signal output from the phase frequency detector 1, and outputting a current from the charge pump 2; The charge amount is controlled according to the output current amount, and the low pass filter 3 outputs a stable bias voltage value according to the charge amount, and a voltage controlled oscillator for varying the frequency according to the bias voltage value input from the low pass filter 3 and outputting it. It consists of (4).

The operation of a general phase locked loop having the structure as described above is as follows.

The phase frequency detector 1 outputs a down signal DOWN indicating an error if the phase of the frequency fed back from the voltage controlled oscillator 4 is faster than the phase of the reference frequency input from the reference frequency oscillator (not shown). If slow, an up signal UP indicating an error is outputted to the charge pump 2.

When the charge pump 2 receives the down signal DOWN from the phase frequency detector 1, the charge pump 2 is discharged so that a small amount of current is transferred to the low pass filter 3 and the voltage controlled oscillator 4. The low pass filter 3 applies a small amount of voltage to the voltage controlled oscillator 4 according to the amount of current input from the charge pump 2. The voltage controlled oscillator 4 then oscillates and outputs a frequency whose phase is slower than the frequency previously oscillated to the phase frequency detector 1.

In contrast to the above, when the up pump UP is input from the phase frequency detector 1, the charge pump 2 is charged so that a large amount of current is supplied to the low pass filter 3 and the voltage controlled oscillator. The low pass filter 3 applies a large amount of voltage to the voltage controlled oscillator 4 in accordance with the amount of current input from the charge pump 2. The voltage controlled oscillator 4 then oscillates and outputs a frequency whose phase is earlier than the frequency previously oscillated to the phase frequency detector 1.

On the other hand, the feedback operation is repeatedly performed until the phases of the reference frequency and the feedback frequency coincide. When the phases of the frequencies coincide, the frequency oscillated from the voltage controlled oscillator 4 is fixed.

A charge pump of a conventional phase locked loop will be described with reference to FIG.

Referring to FIG. 2, a conventional charge pump includes a pull-up transistor PM1 for applying a current of a power supply to a node N1 at turn-on and a pull-down transistor NM1 for applying a current of the node N2 to ground at a turn-on. ), A voltage divider 5 connected between a power supply and a ground to control gate applied voltages of the PMOS transistor PM1 and the NMOS transistor NM1, respectively, and an up signal output from the phase frequency detector 1 of FIG. A switch PMOS transistor PM2 connected to node N1 and an output terminal OUT and a down signal DOWN output from the phase frequency detector 1 of FIG. 1 are applied to the gate. And a switching NMOS transistor NM2 applied and connected between the node N2 and the output terminal OUT.

The voltage divider 5 is composed of a diode PMOS transistor PM3 whose gate is commonly connected to the gate of the PMOS transistor PM1, and a diode NMOS transistor NM3 whose gate is commonly connected to the gate of the NMOS transistor NM1. .

Referring to the operation of the conventional charge pump having the structure as described above is as follows.

The gate voltage values of the NMOS transistor NM1 and the PMOS transistor PM1 are respectively controlled by the voltage divider 5 to control the current values of the nodes N1 and N2.

When the up signal UP in the low state is applied to the gate of the switching PMOS transistor PM2, and the down signal DOWN in the high state is applied to the gate of the NMOS transistor NM2, the output terminal OUT is applied. When a large amount of current is output, on the contrary, a high up signal UP is applied to the gate of the switching PMOS transistor PM2, and a low signal DOWN is applied to the gate of the NMOS transistor NM2. A large amount of current is output through (OUT).

FIG. 3 shows the characteristics of current flowing in accordance with the voltage applied to the gates of the conventional pass transistor PM1 and pass transistor NM1.

However, the above-described conventional charge pump can adjust the magnitude of the amount of current flowing through the PMOS transistor PM1 and the NMOS transistor NM1 by the voltage divider 5 to some extent, but the PMOS transistor PM1 and the like. Since the NMOS transistors NM1 are physically different from each other, complete symmetry cannot be achieved, and accordingly, a conventional phase locked loop has a problem in that a stable frequency cannot be obtained.

Accordingly, the present invention is to solve the above problems, by controlling the flow of the current amount to minimize the output change caused by the noise of the outside or inside itself after the frequency is fixed, the phase-locked loop that can supply a stable frequency The purpose is to provide a charge pump.

1 is a block diagram of a typical phase locked loop.

2 is a circuit diagram of a charge pump of a conventional phase locked loop.

3 is a characteristic diagram of a charge pump of a conventional phase locked loop.

4 is a circuit diagram of a charge pump of a phase locked loop according to an embodiment of the invention.

5 is a characteristic diagram of a charge pump of a phase locked loop according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1: phase frequency detector 2: charge pump

3: low pass filter 4: voltage controlled oscillator

10,20: first and second switching unit 30: voltage control unit

The charge pump of the phase locked loop of the present invention for achieving the above object comprises a pull-up transistor for passing the current of the power supply by the voltage applied to the gate;

A pull-down transistor for applying a current to the ground by passing a current by a voltage applied to the gate; Voltage control means for controlling the voltage applied to the gate and the magnitude of the voltage so that the amount of current flowing in each channel of the pull-up transistor and the pull-up transistor flows symmetrically with each other; First switching means connected between an output terminal and a pull-up transistor, the first switching means being turned on / off by an up signal and an inverted up signal to output a predetermined current applied through the pull-up transistor to the output terminal; And second switching means connected between the first switching means and the pull-down transistor to which the output terminal is commonly connected, and applying a predetermined current flowing to the output terminal on / off by a down signal and an inverted down signal to ground. Include.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 4 and 5.

Referring to FIG. 4, a charge pump of a phase locked loop according to the present invention includes a pull-up transistor PM10, an up signal UP, and an inverted up signal (P10) for passing a current of a power supply, which is sequentially connected between a power supply voltage and a ground. / UP) is turned on / off by the first switching means 10, the down signal DOWN and the inverted down signal / DOWN for outputting a predetermined current applied to the output terminal by being turned on / off by the pull-up transistor. And a second switching means 20 for applying a predetermined current flowing to the output terminal OUT to ground and a pull-up transistor NM10 for applying a current to ground.

In addition, the charge pump of the phase locked loop of the present invention further includes voltage control means 30 for controlling the voltage distribution and the voltage distribution applied to the gates of the pull-up transistor PM10 and the pull-down transistor NM10, respectively. .

The first switching means 10 is connected in parallel between the pull-up transistor PM10 and the output terminal OUT, and the PMOS transistor PM20 and the NMOS to which the up signal UP and the inverted up signal / UP are applied to the gate, respectively. It consists of a transistor NM20.

The second switching means 20 is connected in parallel between the pull-down transistor NM10 and the output terminal OUT, and a PMOS transistor PM30 and an NMOS to which a down signal DOWN and an inverted down signal / DOWN are respectively applied to a gate. It consists of a transistor NM30.

The voltage control means 30 comprises a diode PMOS transistor PM40, a diode PMOS transistor PM50, a diode NMOS transistor NM40 and a diode NMOS transistor NM50, which are sequentially connected between a power supply voltage and ground. Is done.

Referring to the operation of the phase locked loop of the present invention having the above structure as follows.

The voltage control means 30 applies a predetermined voltage applied to the gate of the pull-up transistor PM10 and the gate of the pull-down transistor NM10 to ground, so that a current flowing through the pull-up transistor PM10 and the pull-down transistor NM10 is applied. As shown in Fig. 5, the current amount flowing through the pull-up transistor PM10 and the pull-down transistor NM10 is further increased by adding a diode PMOS transistor PM50 and a diode NMOS transistor NM40 unlike the conventional ones. Can be reduced.

FIG. 5 illustrates characteristics of current flowing according to voltages applied to the gates of the pull-up transistor PM10 and the pull-down transistor NM10, respectively.

When the first and second switching means 10 and 20 are applied with the up signal UP in the low state and the down signal DOWN in the high state from the phase frequency detector 1 of FIG. PMOS transistor PM20 and NMOS transistor NM20 are turned on and PMOS transistor PM30 and NMOS transistor NM30 of the second switching means 20 are turned off to output a large amount of current to the output terminal OUT. Let's do it.

On the contrary, when the first and second switching means 10 and 20 receive the up signal UP in the high state and the down signal DOWN in the low state from the phase frequency detector 1 of FIG. The PMOS transistor PM20 and the NMOS transistor NM20 of the means 10 are turned off, and the PMOS transistor PM30 and the NMOS transistor NM30 of the second switching means 20 are turned on to apply a predetermined current to ground. Thus, a small amount of current is output to the output terminal OUT.

In addition, since the PMOS transistor PM20 and the NMOS transistor NM20 of the first switching means 10 and the PMOS transistor PM30 and the NMOS transistor NM30 of the second switching means 20 are symmetrically configured, the first The amount of current flowing through the switching means 10 to the output terminal OUT and the amount of current flowing through the second switching means 20 to ground are the same.

Therefore, the same amount of current flows to the pull-up transistor PM10 and the pull-down transistor NM10 by the voltage control means 30, and the amount of current flowing through the first switching means 10 to the output terminal OUT and By making the amount of current flowing to the ground through the two switching means 20 equal, the phase locked loop of the present invention can supply a stable frequency.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

As described above, the charge pump of the phase-lock loop of the present invention has a fixed frequency by controlling the amount of current flowing to the output terminal and the ground by symmetrically connecting the PMOS transistor and the NMOS transistor used for the clutch. After minimizing the output change caused by the noise of outside or inside itself, it provides the effect of supplying stable frequency.

Claims (4)

A pull-up transistor for passing a current of the power supply by a voltage applied to the gate; A pull-down transistor for applying a current to the ground by passing a current by a voltage applied to the gate; Voltage control means for controlling the voltage applied to the gate and the magnitude of the voltage so that the amount of current flowing in each channel of the pull-up transistor and the pull-up transistor flows symmetrically with each other; First switching means connected between an output terminal and a pull-up transistor, the first switching means being turned on / off by an up signal and an inverted up signal to output a predetermined current applied through the pull-up transistor to the output terminal; And And a second switching means connected between the first switching means and the pull-down transistor having the output terminal commonly connected, and applying a predetermined current flowing to the output terminal on / off by a down signal and an inverted down signal to ground. Charge pump in one phase locked loop. The method of claim 1, wherein the first switching means And a PMOS transistor and an NMOS transistor connected in parallel between the pull-up transistor and the output terminal and to which the up signal and the inverted up signal are applied to a gate, respectively. The method of claim 1, wherein the second switching means And a PMOS transistor and an NMOS transistor connected in parallel between the pull-down transistor and the output terminal and to which the down signal and the inverted down signal are applied to a gate, respectively. The method of claim 1, wherein the voltage control means Difference in phase locked loop comprising a PMOS transistor for a first diode, a PMOS transistor for a second diode, an NMOS transistor for a first diode, and an NMOS transistor for a second diode sequentially connected in series between a power supply voltage and a ground Aji pump.

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