JP2001085996A - High-speed lockup circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high-speed lockup circuit for a PLL that can attain a lockup operation at high speed with a comparatively simple configuration without causing deterioration in characteristic. SOLUTION: The PLL circuit is provided with a phase comparator 5 that compares the phase of a reference signal fREF with the phase of a comparison signal f0 and provides the output in response to its phase difference, a charge pump 6 that receives the output of the phase comparator 5, a low-pass filter that integrates the output of the charge pump 6, a voltage controlled oscillator 8 that receives the output of the low-pass filter 7 and a programmable divider 4 that frequency-divides the output of the voltage controlled oscillator 8 and gives the result to the phase comparator 5 as the comparison signal f0. In this case, pre-charging that adds a reference signal VREF 1 to a tuning signal VT of the voltage controlled oscillator 8 is conducted in response to set data SI to the programmable divider 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a communication PLL.
The present invention relates to a high-speed lock-up circuit in a (Phase Locked Loop) circuit or the like.

[0002]

2. Description of the Related Art In a mobile communication, as a digitalization has progressed, a PLL for a frequency synthesizer has been required to have a faster lock-up time. Further, in a PHS, a mobile phone, or the like, the number of frequency channels is large, and switching between the channels naturally requires high-speed lockup. In a frequency synthesizer PLL, when switching between channels is considered, a low-pass filter is designed on the assumption that the number of channels can be changed to the maximum.

A specific example will be described. First, FIG.
FIG. 0 shows an overall configuration diagram of a conventional PLL circuit. In the figure, 1 is a reference oscillator, 2 is a reference divider, 3 is a prescaler, 4 is a programmable divider, 5 is a phase comparator, 6 is a charge pump, 7 is a low-pass filter, and 8 is a voltage controlled oscillator.

The operation of the PLL circuit includes a reference signal fREF obtained by dividing the reference signal by the reference divider 2, and a signal fO obtained by dividing the output signal fVCO of the voltage controlled oscillator 8 by the prescaler 3 and the programmable divider 4. Is compared in a phase comparator 5, a quantity proportional to the phase difference is sourced or sinked (pump operation) in a charge pump 6, integrated by a low-pass filter 7, converted into a DC voltage, and tuned. Feedback is applied to the voltage controlled oscillator 8 as the voltage VT. For a programmable divider, the desired fVCO
Is input.

[0005] Now, as shown in FIG.
The frequency corresponding to the minimum of the frequency channel is fVCOmin, the frequency corresponding to the maximum of the frequency channel is fVCOmax,
The tuning voltages VT of the voltage controlled oscillators that generate these frequencies are VTmin and VTmax, respectively. Normally, regarding the lock-up between the channels, the lock-up time at a frequency corresponding to the tuning voltage difference that can be changed to the maximum in the voltage controlled oscillator 8 is the longest.
Here, it is between fVCOmin and fVCOmax in terms of frequency, and between VTmin and VTmax in terms of the tuning voltage VT of the voltage controlled oscillator 8.

As shown in FIG. 12, fVCOm is converted to fVCOm.
ax, ie, the voltage controlled oscillator 8
When the tuning voltage VT is switched from VTmin to VTmax, the low-pass filter 7 must be designed so that the lock-up time t10 falls within the maximum allowable time in the system. In designing a low-pass filter of a PLL for a frequency synthesizer, a direction in which the lock-up time is increased and a direction in which other characteristics such as a carrier / noise ratio (C / N) characteristic and a spurious characteristic of a reference signal fREF component are improved. Means that the advantages and disadvantages of the characteristics obtained by implementing these designs are contradictory. Therefore, conventionally, in a frequency synthesizer PLL, by increasing the lock-up time,
The C / N characteristics and spurious characteristics were undesirably deteriorated.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed lock-up circuit in a PLL capable of performing a lock-up operation at a high speed with a relatively simple configuration without deteriorating characteristics.

[0008]

According to a first aspect of the present invention, there is provided a high-speed lockup circuit for comparing a phase of a reference signal with a phase of a comparison signal, and deriving an output corresponding to the phase difference. A charge pump receiving an output of the means, an integrating means for integrating an output of the charge pump,
A PCO comprising: a voltage-controlled oscillating means for receiving an output of the integrating means; and a variable frequency-dividing means for dividing the output of the voltage-controlled oscillating means and applying the divided signal to the phase comparing means.
The LL circuit performs a precharge operation of adding a reference signal to a tuning signal of the voltage controlled oscillator in accordance with data set in the variable frequency divider.

In the high-speed lockup circuit according to a second aspect of the present invention, a phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output corresponding to the phase difference, and a charge receiving the output of the phase comparison means A pump, integrating means for integrating the output of the charge pump, voltage-controlled oscillating means receiving the output of the integrating means, and dividing the output of the voltage-controlled oscillating means and applying the frequency-divided signal to the phase comparing means as the comparison signal In a PLL circuit having variable frequency dividing means, an operational amplifier controlled in accordance with data set to the variable frequency dividing means is provided, and a tuning signal of the voltage controlled oscillator is referred to in accordance with an output of the operational amplifier. A precharge operation for applying a signal is performed.

In the high-speed lock-up circuit according to a third aspect of the present invention, a phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output corresponding to the phase difference, and a charge receiving the output of the phase comparison means A pump, an integrating means including a low-pass filter for integrating the output of the charge pump, a voltage-controlled oscillating means receiving an output of the integrating means,
A variable frequency divider for dividing the output of the voltage controlled oscillator and applying the divided signal to the phase comparator as the comparison signal, wherein the variable frequency divider is applied with the output of the charge pump as an input. A precharge operation of adding a reference signal to a tuning signal of the voltage controlled oscillator by applying an output of the operational amplifier to an integrating means comprising the low-pass filter by providing an operational amplifier controlled according to setting data to the means. Is what you do.

According to a fourth aspect of the present invention, there is provided a high-speed lockup circuit for comparing a phase of a reference signal with a phase of a comparison signal and deriving an output corresponding to the phase difference, and a charge receiving an output of the phase comparison means. A pump, an integrating means including a low-pass filter for integrating the output of the charge pump, a voltage-controlled oscillating means receiving an output of the integrating means,
A PLL circuit comprising a variable frequency divider comprising a programmable divider for dividing the output of the voltage controlled oscillator and applying the divided signal as the comparison signal to the phase comparator, wherein a reference signal is applied to a + input terminal; ,
An output of the charge pump is applied to an-input terminal, an operational amplifier, control means controlled according to setting data to a variable frequency dividing means comprising the programmable divider, and a control signal from the control means. Reference signal generating means for generating a predetermined reference signal and applying the signal to a + input terminal of the operational amplifier; wherein the control means outputs the output of the operational amplifier in accordance with setting data to a variable frequency dividing means comprising the programmable divider Is turned on / off, negatively fed back to the-input terminal of the operational amplifier, and applied to an integrating means comprising the low-pass filter, thereby performing a precharge operation of adding a reference signal to a tuning signal of the voltage controlled oscillator. Is what you do.

According to a fifth aspect of the present invention, there is provided a high-speed lockup circuit for comparing a phase of a reference signal with a phase of a comparison signal and deriving an output corresponding to the phase difference, and a charge receiving an output of the phase comparison means. A pump, an integrating means including a low-pass filter for integrating the output of the charge pump, a voltage-controlled oscillating means receiving an output of the integrating means,
A PLL circuit comprising: a prescaler that divides the output of the voltage-controlled oscillator; and a variable divider that includes a programmable divider that further divides the output of the prescaler and applies the output to the phase comparator as the comparison signal. A control in which a reference signal is applied to a positive input terminal and an output of the charge pump is applied to a negative input terminal, and control is performed in accordance with setting data to a variable frequency dividing means including the programmable divider. Means, and a reference signal generating means for generating a predetermined reference signal in accordance with a control signal from the control means and applying the generated reference signal to a + input terminal of the operational amplifier, wherein the control means comprises a variable component comprising the programmable divider. According to the setting data for the Output and ON / OFF control of,
A negative charge is fed back to the negative input terminal of the operational amplifier, and is applied to an integrating means comprising the low-pass filter, thereby performing a precharge operation of adding a reference signal to a tuning signal of the voltage controlled oscillator.

According to a sixth aspect of the present invention, in the high-speed lockup circuit according to the first to fifth aspects, the control means generates a control signal having a predetermined control number in accordance with data set to the variable frequency dividing means. A desired reference signal is selected from the reference signals to be performed, and a precharge operation of adding the reference signal to the tuning signal of the voltage controlled oscillator is performed.

According to a seventh aspect of the present invention, in the high-speed lock-up circuit according to the first to fifth aspects, the reference signal generating means generates a reference signal corresponding to the setting data to the variable frequency dividing means. A precharge operation for adding a reference signal to the tuning signal of the voltage controlled oscillator is performed.

According to an eighth aspect of the present invention, in the high-speed lock-up circuit according to the first to fifth aspects, the reference signal generating means comprising a D / A converter corresponds to the reference data corresponding to the setting data to the variable frequency dividing means. A precharge operation of generating a signal and adding a reference signal to a tuning signal of the voltage controlled oscillator is performed.

In the high speed lock-up circuit according to the ninth aspect, the phase comparison means for comparing the phases of the reference signal and the comparison signal to derive an output according to the phase difference, and a charge receiving the output of the phase comparison means A pump, an integrating means including a low-pass filter for integrating the output of the charge pump, a voltage-controlled oscillating means receiving an output of the integrating means,
A PLL circuit comprising a variable frequency divider comprising a programmable divider for dividing the output of the voltage controlled oscillator and applying the divided signal as the comparison signal to the phase comparator, wherein a reference signal is applied to a + input terminal; ,
An operational amplifier for applying the output of the charge pump to a negative input terminal, control means controlled in accordance with setting data to a variable frequency dividing means comprising the programmable divider, and a variable frequency dividing means comprising the programmable divider And a reference signal generating means comprising a D / A converter for generating a predetermined reference signal in accordance with the setting data to be applied to the operational amplifier and applying the reference signal to the + input terminal of the operational amplifier. The output of the operational amplifier is ON / OFF-controlled in accordance with the frequency setting data to the frequency dividing means, and negatively fed back to the negative input terminal of the operational amplifier, and is applied to the integrating means comprising the low-pass filter, whereby the voltage is reduced. Variable frequency divider for tuning signal of control oscillator Add a reference signal corresponding to a set frequency and performs the precharge operation.

According to a tenth aspect of the present invention, there is provided a high-speed lockup circuit for comparing a phase of a reference signal with a phase of a comparison signal to derive an output corresponding to the phase difference, and a charge receiving the output of the phase comparison means. A pump, an integrating means comprising a low-pass filter for integrating the output of the charge pump, a voltage controlled oscillator receiving the output of the integrating means, a prescaler for dividing the output of the voltage controlled oscillator, and an output of the prescaler And a variable frequency divider comprising a programmable divider for applying the reference signal to the phase comparator as the comparison signal, wherein the reference signal is applied to the + input terminal;
The output of the charge pump is applied to an-input terminal, an operational amplifier, control means controlled in accordance with setting data to a variable frequency divider comprising the programmable divider, and a variable divider comprising the programmable divider. Reference signal generating means comprising a D / A converter for generating a predetermined reference signal corresponding to the setting data to the peripheral means and applying the reference signal to the + input terminal of the operational amplifier; and the control means comprising the programmable divider. ON / O the output of the operational amplifier according to the frequency setting data to the variable frequency dividing means
By performing FF control and applying negative feedback to the negative input terminal of the operational amplifier and applying the same to the integrating means comprising the low-pass filter, the tuning signal of the voltage controlled oscillation means is adjusted according to the set frequency of the variable frequency dividing means. A precharge operation for applying a reference signal is performed.

In the high-speed lock-up circuit according to the eleventh aspect, a phase comparison means for comparing the phases of the reference signal and the comparison signal to derive an output corresponding to the phase difference, and a charge receiving the output of the phase comparison means A pump, integrating means for integrating the output of the charge pump, voltage-controlled oscillating means receiving the output of the integrating means, and dividing the output of the voltage-controlled oscillating means and applying the frequency-divided signal to the phase comparing means as the comparison signal In a PLL circuit provided with a variable frequency dividing means,
A precharge operation of adding a reference signal to a tuning signal of the voltage controlled oscillator in accordance with setting data to the variable frequency dividing means is performed, and the reference signal is inputted in response to setting data input to the variable frequency dividing means. A timing generator for synchronizing a signal and the comparison signal is provided.

In the high-speed lockup circuit according to the twelfth aspect, a phase comparison means for comparing the phases of the reference signal and the comparison signal to derive an output according to the phase difference, and a charge receiving the output of the phase comparison means A pump, an integrating means comprising a low-pass filter for integrating the output of the charge pump, a voltage controlled oscillator receiving the output of the integrating means, a prescaler for dividing the output of the voltage controlled oscillator, and an output of the prescaler And a variable divider comprising a programmable divider for applying the comparison signal as the comparison signal to the phase comparator, wherein the voltage controlled oscillation is performed in accordance with the setting data to the variable divider. Performing a precharge operation of adding a reference signal to the tuning signal of the means, The prescaler in response to the constant data input in synchronization with the reference signal, is provided with a timing generation means for synchronizing the said comparison signal and said reference signal by controlling the programmable divider and phase comparator means.

In the high-speed lockup circuit according to the thirteenth aspect, a phase comparison means for comparing the phases of the reference signal and the comparison signal to derive an output corresponding to the phase difference, and a charge receiving the output of the phase comparison means A pump, an integrating means comprising a low-pass filter for integrating the output of the charge pump, a voltage controlled oscillator receiving the output of the integrating means, a prescaler for dividing the output of the voltage controlled oscillator, and an output of the prescaler And a variable frequency divider comprising a programmable divider for applying the reference signal to the phase comparator as the comparison signal, wherein the reference signal is applied to the + input terminal;
The output of the charge pump is applied to an-input terminal, an operational amplifier, control means controlled in accordance with setting data to a variable frequency divider comprising the programmable divider, and a variable divider comprising the programmable divider. Reference signal generating means comprising a D / A converter for generating a predetermined reference signal corresponding to the setting data to the peripheral means and applying the reference signal to the + input terminal of the operational amplifier; and the control means comprising the programmable divider. By controlling ON / OFF of the output of the operational amplifier in accordance with the setting data to the variable frequency dividing means, negatively feeding back the negative input terminal of the operational amplifier, and applying the negative feedback to the integrating means comprising the low-pass filter, A reference signal is used as the tuning signal of the voltage controlled oscillator. The reference signal and the comparison signal are controlled by controlling the prescaler, the programmable divider, and the phase comparison means in synchronization with the reference signal in response to setting data input to the variable frequency dividing means, while performing an additional precharge operation. And a timing generating means for synchronizing the timings.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 shows a configuration diagram of a PLL circuit according to the first embodiment of the present invention. FIG. 1A is an overall configuration diagram of a PLL circuit, and FIG.
FIG. 3 is a configuration diagram of a reference potential generation circuit. In the figure, 1 is a reference oscillator, 2 is a reference divider, 3
Is a prescaler, 4 is a programmable divider, 5 is a phase comparator, 6 is a charge pump, 7 is a low-pass filter, 8 is a voltage controlled oscillator, 9 is a control circuit, 10
Reference numeral denotes an operational amplifier provided between the output of the charge pump and the low-pass filter, reference numeral 11 denotes a switch for controlling the output of the operational amplifier, and reference numeral 12 denotes a reference potential generating circuit for applying a reference potential VREF1 to the (+) side of the operational amplifier.
The connection and operation of the reference oscillator 1 to the voltage controlled oscillator 8 are the same as those of the prior art shown in FIG.

The connection and operation of the control circuit 9, operational amplifier 10, switch 11, and reference potential generation circuit 12 will be described in detail. The division ratio setting data SI is input to the control circuit 9, and the control signal 9 generates control signals CTL1 to CTLk (k is an integer of 2) and a control signal SC based on the value.

The operational amplifier 10 has the (−) terminal side of the operational amplifier input connected to the output of the charge pump 6,
The (+) terminal side is connected to the potential VREF1 obtained by the reference potential generation circuit 12. Further, the output of the operational amplifier 10 is connected to the low-pass filter 7 via a switch 11 for negative feedback which can be connected to the (−) terminal side of the operational amplifier input.

The switch 11 is controlled by a control signal SC generated by the control circuit 9, and controls whether or not to charge the output of the operational amplifier 10 to the low-pass filter 7. Reference potential generation circuit 12
Is a control signal C obtained from the control circuit 9.
Controlled by TL1 to CTLk, (+) of the operational amplifier 10
A reference potential VREF1 applied to the terminal is generated.

FIG. 2 shows a specific example of the reference potential generating circuit 12. As for the control signal obtained from the control circuit 9, the control number k is set to 4 here. The circuit is composed of the minimum value of VREF1 VREF1mi
n, constant current sources I1 to I4 for determining the setting steps of the resistor R and VREF1, and control signals CTL1 to CTL generated by the control circuit 9.
4 to turn on / off the constant current sources I1 to I4
N-channel MOS transistors T1 to T4 serving as switches for switching.

As shown in FIG. 2, each constant current source is connected in parallel, and one is connected to a power supply Vcc. Constant current sources I1 to I4
The other is connected to the sources of N-channel MOS transistors T1 to T4 serving as a switch function, and is connected to each of N-channel MOS transistors T1 to T4.
The drains of the OS transistors T1 to T4 are connected to a constant current source I0.
Are connected in parallel with the other side of the power supply Vcc (this connection point is point A). This connection point (point A) is further connected to a resistor R
, And the other end of the resistor R is connected to GND. The gates of the N-channel MOS transistors T1 to T4 are connected to the control circuit 9. The potential obtained at point A is output from the reference potential generating circuit 12 to the (+) terminal side of the operational amplifier 10 as VREF1.

The setting of the reference potential VREF1 will be described using specific values (see FIG. 3). Vcc = 3
V, Io = 500 μA, R = 2 KΩ, I1 = 50 μA,
I2 = 2I1 = 100 μA, I3 = 3I1 = 150 μ
A, I4 = 4 Assuming that I1 = 200 μA, VREF1min =
1.0V, VREF1mid = 1.5V, VREF1max = 2.0
V, VREF1step = 0.1V is obtained.

In order to obtain VREF1 = 1.8V at the time of the above setting, control signals CTL1, CTL3, CT
The serial data SI is input such that L4 has the “Hi” potential and CTL2 has the “Low” potential. This turns on the N-channel MOS transistors T1, T3, T4,
The current flowing at point A is 500 + 50 + 150 + 200 + 9
00 μA, and VREF1 = 900 μA × 2 KΩ = 1.8 V is obtained. As described above, the setting range and the step voltage of the reference potential VREF1 can be freely changed by arbitrarily setting the constant current sources Io, I1 to Ik and the resistor R.

Next, the operation timing of the switch 11 and the effect of shortening the lock-up time will be described. The basic operation of the switch 11 is as described above.
Control signal SC generated by control circuit 9
To control whether or not to charge the low-pass filter 7 with the reference potential VREF1 obtained by the reference voltage generation circuit 12 via the operational amplifier 10.

FIG. 4 shows the relationship between switch operation timing and lock-up. As soon as the data of the frequency change is input by the serial data SI, the control circuit controls the control signals CTL1 to CTLk for generating the reference potential VREF1 and the switch 11 to be turned on so as to obtain the frequency closest to the changed frequency. Generate a signal SC. This switch control signal SC is ON only during the time when the reference potential VREF1 is completely charged in the low-pass filter 7.
However, it is controlled to be turned off after charging is completed.

When the switch 11 is turned on, data of frequency change is input from the serial data SI,
This occurs before the L loop begins to lock to the new frequency. That is, when the switch 11 is turned on and the low-pass filter 7 is completely charged with the reference potential VREF1, and the switch 11 is turned off again (time for precharging the low-pass filter 7 with the reference potential VREF1; tsc1), the PLL loop switches the frequency. Start lock operation.

As described above, in the conventional circuit configuration, when frequency switching is performed, particularly when switching from the minimum channel to the maximum channel, the change in the output of the low-pass filter 7, that is, the tuning voltage VT input to the voltage controlled oscillator 8 is (VTmin). However, in the present invention, since the reference potential VREF1 is precharged before the loop operation, the voltage change can be reduced to (VREF1-VTmax). Since the voltage change can be reduced, damping during the lock operation is also reduced, and high-speed lock-up becomes possible.

Further, in the present invention, the low-pass filter 7 can be designed not in the frequency band corresponding to the tuning voltages VT1min to VT1max as in the conventional circuit but in a narrower frequency band corresponding to VREF1 to VTmax (or VTmin). , C / N characteristics and spurious characteristics can also be improved.

According to the first embodiment of the present invention, the phase comparison means comprising the phase comparator 5 for comparing the phases of the reference signal fREF1 and the comparison signal f0 and deriving an output according to the phase difference, A charge pump 6 receiving the output of the phase comparing means comprising the filter 5, an integrating means comprising a low-pass filter 7 for integrating the output of the charge pump 6, and a voltage-controlled oscillator 8 receiving the output of the integrating means comprising the low-pass filter 7. A voltage-controlled oscillating means, a prescaler 3 for dividing the output of the voltage-controlled oscillating means composed of the voltage-controlled oscillator 8, and an output of the prescaler 3 which is further frequency-divided and applied as a comparison signal f0 to the phase comparing means composed of the phase comparator 5 In a PLL circuit provided with a variable frequency dividing means including a programmable divider 4 for
REF1 is applied to the + input terminal and the charge pump 6
And an control amplifier 9 which is controlled in accordance with setting data SI to a variable frequency dividing means comprising a programmable divider 4.
And control signals CTL1 to CTL from the control means including the control circuit 9.
and a reference signal generating means including a reference potential generating circuit 12 for generating a predetermined reference signal VREF1 according to k and applying the generated reference signal to the + input terminal of the operational amplifier 10.
The output of the operational amplifier 10 is turned on in accordance with the setting data SI to the variable frequency dividing means including the programmable divider 4
/ OFF control, negative feedback to the-input terminal of the operational amplifier 10 and application to the integrating means comprising the low-pass filter 7 to apply the reference signal VREF1 to the tuning signal VT of the voltage controlled oscillator comprising the voltage controlled oscillator 8. Since the additional precharge operation is performed, by generating the reference signal VREF1 in accordance with the setting data SI of the programmable divider 4, the lockup operation can be performed at a high speed with a relatively simple configuration without characteristic deterioration. A high-speed lockup circuit in a possible PLL can be obtained.

Embodiment 2 FIG. 5 shows an overall configuration diagram of a PLL circuit according to a second embodiment of the present invention. In the figure, 1 is a reference oscillator, 2 is a reference divider, 3 is a prescaler, 4 is a programmable divider, 5 is a phase comparator, 6 is a charge pump, 7 is a low-pass filter, 8 is a voltage controlled oscillator, 9 is a control circuit, 10 Is an operational amplifier provided between the charge pump output and the low-pass filter, 11 is a switch for controlling the output of the operational amplifier, 12 is a reference potential generating circuit for applying a reference potential VREF2 to the (+) terminal side of the operational amplifier 10, and 13 is a D / A converter It is.

In the second embodiment, the overall configuration is almost the same as that of the first embodiment, but a block for generating a reference potential VREF2 applied to the (+) terminal side of the operational amplifier 10 is provided by a D / A converter 13. The feature is that it is done.

The D / A converter 13 is controlled by frequency setting data SI, and outputs a voltage corresponding to each frequency to V
Output as REF2. In the first embodiment, the reference voltage generation circuit arbitrarily sets VREF1min, VREFmax,
Set VREF1step etc. and set VREF1 close to the changing frequency.
Although the control is performed by the control signal so as to obtain the potential, in the second embodiment, each frequency data has a one-to-one correspondence.
VREF2 potential corresponding to VREF2
The potential can be made substantially the same as the VT potential (tentatively VTmax) when the frequency changes (VREF2 ≒ VTmax). Therefore, a faster lock-up characteristic can be obtained.

FIG. 6 shows a simple example of the D / A converter 13.
(Here, an 8-bit configuration is assumed.) The D / A converter 13 includes a shift register, a latch circuit,
And a reference potential generator. Here, when input data “10010011” for setting a certain frequency is input, the data is first input to the shift register, and when 8 bits are input, the data is stored in the latch circuit. The latch output controls switches SW1 to SW8 of the current circuit corresponding to the weight of each bit. Assuming that the switch is turned on when the input data is "1" and turned off when the input data is "0", in the case of the above data,
Since SW1, SW4, SW7, and SW8 are turned on, 12
A current corresponding to 8I + 16I + 2I + I = 147I flows, and a reference potential VREF2 corresponding to each frequency of VREF2 = 147I × R is obtained. As described above, the reference potential VREF2 corresponding to the frequency setting data SI to the programmable divider 4 can be obtained, and the reference potential VREF2 corresponding to each frequency setting data on a one-to-one basis.
Is what you can get

FIG. 7 shows a lock-up waveform in the second embodiment. Compared with FIG. 4 showing the lock-up waveform in the first embodiment, the tuning voltage when the frequency of the reference potential VREF2 obtained in the second embodiment is changed more than that of the reference potential VREF1 obtained in the first embodiment. It is close to VTmax. Also, the damping of the waveform of the transition time (lock-up time) of the frequency change is smaller in the second embodiment. Therefore, lockup is also faster in the second embodiment (t12 <
t11).

In the second embodiment, the reference voltage VREF2 corresponding to the changed frequency is precharged to lock the tuning voltage, but is actually input to the phase comparator 5. Since there is a phase shift between the reference signal fREF2 and the signal f0 obtained by the PLL loop, it takes a lock-up time t12 to eliminate the phase difference.

According to the second embodiment of the present invention, the phase comparison means comprising the phase comparator 5 for comparing the phases of the reference signal fREF and the comparison signal f0 and deriving an output corresponding to the phase difference, A charge pump 6 receiving the output of the phase comparing means comprising the filter 5, an integrating means comprising a low-pass filter 7 for integrating the output of the charge pump 6, and a voltage-controlled oscillator 8 receiving the output of the integrating means comprising the low-pass filter 7. A voltage-controlled oscillating means, a prescaler 3 for dividing the output of the voltage-controlled oscillating means composed of the voltage-controlled oscillator 8, and an output of the prescaler 3 which is further frequency-divided and applied as a comparison signal f0 to the phase comparing means composed of the phase comparator 5 In a PLL circuit provided with a variable frequency dividing means including a programmable divider 4 for
REF2 is applied to the + input terminal and the charge pump 6
And an control amplifier 9 which is controlled in accordance with setting data SI to a variable frequency dividing means comprising a programmable divider 4.
And a D / A converter 13 for generating a predetermined reference signal VREF2 corresponding to the setting data SI to the variable frequency dividing means consisting of the programmable divider 4 and applying it to the + input terminal of the operational amplifier 10. Signal generating means, and a control means comprising a control circuit 9 controls ON / OFF of an output of the operational amplifier 10 in accordance with the frequency setting data SI to the variable frequency dividing means comprising the programmable divider 4, and controls the operation of the operational amplifier 10. The negative feedback to the input terminal and the application to the integrating means comprising the low-pass filter 7 allow the tuning signal VT of the voltage controlled oscillating means comprising the voltage controlled oscillator 8 to be applied to the variable frequency dividing means comprising the programmable divider 4 Reference signal according to set frequency Since the precharge operation for adding REF2 is performed, the lock-up operation can be performed at a higher speed with a relatively simple configuration using the reference signal generation means including the D / A converter 13 without deteriorating characteristics. A high-speed lockup circuit in a PLL can be obtained.

Embodiment 3 FIG. 8 shows an overall configuration diagram of a PLL circuit according to a third embodiment of the present invention. In the figure, 1 is a reference oscillator, 2 is a reference divider, 3
Is a prescaler, 4 is a programmable divider, 5 is a phase comparator, 6 is a charge pump, 7 is a low-pass filter, 8 is a voltage controlled oscillator, 9 is a control circuit, 10
Is an operational amplifier provided between the charge pump output and the low-pass filter, 11 is a switch for controlling the output of the operational amplifier, 12 is a reference potential generating circuit for applying the reference potential VREF2 to the (+) terminal side of the operational amplifier, and 13 is D
A / A converter 14 is a timing generation circuit.

In the third embodiment, the overall configuration is almost the same as that of the second embodiment, but the prescaler 3 and the programmable divider are based on the reference frequency fREF obtained by dividing the frequency of the reference oscillator 1 by the reference divider 2. 4 and a timing generator 14 for controlling the phase comparator 5 is added. The block operations other than the timing generation circuit 14 are as described above.

The operation of the timing generation circuit 14 will be described. First, frequency division ratio setting data SI, that is, data of frequency change is input. The timing generation circuit 14 is controlled by the latch control signal, that is, the load enable signal LE among the data. When the LE signal is “Hi”, the timing generation circuit 14 is turned on, and when the LE signal is “Low”, the timing generation circuit 14 is turned on.
FF. When data is input, the LE signal always changes from “Low” to “Hi” to “Low”. The rising edge at which the LE signal changes from "Low" to "Hi" activates the timing generation circuit 14 and outputs a control signal SD synchronized with the timing of the reference signal fREF.

The control signal SD controls the prescaler 3 and the programmable divider 4, resets the counter and controls the phase comparator 5 to bring the output of the charge pump 6 into the "HiZ" state. When the LE signal changes from “Hi” to “Low”, the timing generation circuit 14 releases the counters of the prescaler 3 and the programmable divider 4 (latch them to data of a new frequency), and further returns to the normal PLL loop state. However, since the operation of the phase comparator 5 is synchronized with the reference signal fREF by the control signal SD, the signal f0 obtained by dividing the frequency fVCO of the voltage controlled oscillator 8 by the prescaler 3 and the programmable divider 4 is the reference signal f0.
REF and phase almost match.

Since the operation of the other blocks is as described above, the tuning voltage is changed to the potential VREF2 corresponding to the frequency.
And the reference signals fREF and f
The high-speed lockup can be stably realized by the timing generation circuit 14 which operates so as to match the phase of the O signal. FIG. 9 shows a lock-up waveform according to the third embodiment of the present invention. It can be seen from this waveform that the lock-up speed has been increased.

According to the third embodiment of the present invention, the phase comparison means comprising the phase comparator 5 for comparing the phases of the reference signal fREF and the comparison signal f0 and deriving an output corresponding to the phase difference, A charge pump 6 receiving the output of the phase comparing means comprising the filter 5, an integrating means comprising a low-pass filter 7 for integrating the output of the charge pump 6, and a voltage-controlled oscillator 8 receiving the output of the integrating means comprising the low-pass filter 7. A voltage-controlled oscillating means, a prescaler 3 for dividing the output of the voltage-controlled oscillating means composed of the voltage-controlled oscillator 8, and an output of the prescaler 3 which is further frequency-divided and applied as a comparison signal f0 to the phase comparing means composed of the phase comparator 5 In a PLL circuit provided with a variable frequency dividing means including a programmable divider 4 for
REF2 is applied to the + input terminal and the charge pump 6
And an control amplifier 9 which is controlled in accordance with setting data SI to a variable frequency dividing means comprising a programmable divider 4.
And a D / A converter 13 for generating a predetermined reference signal VREF2 corresponding to the setting data SI to the variable frequency dividing means consisting of the programmable divider 4 and applying it to the + input terminal of the operational amplifier 10. Signal generating means, and the control means comprising the control circuit 9 is provided with a setting data SI for the variable frequency dividing means comprising the programmable divider 4.
The ON / OFF control of the output of the operational amplifier 10 is performed in response to the negative feedback to the negative input terminal of the operational amplifier 10 and the output is applied to the integrating means including the low-pass filter 7, whereby the voltage-controlled oscillation of the voltage-controlled oscillator 8 is performed. In addition to performing a precharge operation of adding the reference signal VREF2 to the tuning signal VT of the means, the prescaler 3 synchronizes with the reference signal fREF in response to the input of the setting data SI to the variable frequency dividing means comprising the programmable divider 4.
Since a timing generating means comprising a timing generating circuit 14 for synchronizing the reference signal fREF and the comparison signal f0 by controlling the phase comparing means comprising the programmable divider 4 and the phase comparator 5 is provided, the reference signal fRE
By securing the timing between F and the comparison signal fo, it is possible to obtain a high-speed lock-up circuit capable of performing the lock-up operation accurately and stably at a high speed.

[0048]

According to the first aspect of the present invention, there is provided a phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output according to the phase difference, and a charge pump receiving the output of the phase comparison means. Integrating means for integrating the output of the charge pump, voltage-controlled oscillating means for receiving the output of the integrating means, and a variable type for dividing the output of the voltage-controlled oscillating means and applying the divided signal to the phase comparing means as the comparison signal. In the PLL circuit having frequency dividing means, a precharge operation of adding a reference signal to a tuning signal of the voltage controlled oscillator is performed in accordance with setting data to the variable frequency dividing means. By generating a reference signal according to the setting data to the peripheral means, the lockup operation can be performed at a high speed with a relatively simple configuration without deterioration in characteristics. It is possible to obtain a high-speed lock-up circuit in the PLL.

According to the second aspect, the phase comparison means for comparing the phases of the reference signal and the comparison signal to derive an output according to the phase difference, the charge pump receiving the output of the phase comparison means, Integrating means for integrating the output of the charge pump; voltage-controlled oscillating means for receiving the output of the integrating means; variable frequency dividing for dividing the output of the voltage-controlled oscillating means and applying the divided signal to the phase comparing means as the comparison signal And an operational amplifier controlled in accordance with the setting data to the variable frequency dividing means, and a reference signal is added to a tuning signal of the voltage controlled oscillating means in accordance with an output of the operational amplifier. Since the charging operation is performed, the reference signal is generated by the operational amplifier controlled according to the setting data to the variable frequency dividing means. Therefore, without characteristic deterioration,
With a relatively simple configuration, it is possible to obtain a high-speed lock-up circuit in a PLL that can perform a lock-up operation at high speed.

In the third invention, a phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output according to the phase difference, a charge pump receiving the output of the phase comparison means, Integrating means comprising a low-pass filter for integrating the output of the pump; voltage-controlled oscillating means receiving the output of the integrating means; and a variable for dividing the output of the voltage-controlled oscillating means and applying the divided signal to the phase comparing means as the comparison signal. And an operational amplifier which is applied with an output of the charge pump as an input and is controlled in accordance with setting data to the variable frequency dividing means, and outputs the output of the operational amplifier to the low-pass filter. A reference signal is added to the tuning signal of the voltage-controlled oscillating means by applying the reference signal to the integrating means. By applying the reference signal generated by the operational amplifier controlled according to the setting data to the variable frequency dividing means to the integrating means including the low-pass filter, the characteristic is not deteriorated. It is possible to obtain a high-speed lock-up circuit in a PLL that can perform a lock-up operation at high speed with a relatively simple configuration.

According to the fourth aspect, the phase comparison means for comparing the phases of the reference signal and the comparison signal to derive an output corresponding to the phase difference, the charge pump receiving the output of the phase comparison means, Integrating means comprising a low-pass filter for integrating the output of the charge pump; voltage-controlled oscillating means receiving the output of the integrating means; dividing the output of the voltage-controlled oscillating means and applying the frequency-divided signal to the phase comparing means as the comparison signal In a PLL circuit provided with a variable frequency divider composed of a programmable divider, an operational amplifier that applies a reference signal to a + input terminal and applies an output of the charge pump to a − input terminal, and the programmable divider Control means controlled according to the setting data to the variable frequency dividing means, and Reference signal generating means for generating a predetermined reference signal in accordance with a control signal and applying the generated reference signal to a positive input terminal of the operational amplifier, wherein the control means responds to setting data to a variable frequency dividing means comprising the programmable divider. The ON / OFF control of the output of the operational amplifier causes negative feedback to the negative input terminal of the operational amplifier, and the application of the reference signal to the integrating means comprising the low-pass filter, thereby providing a reference signal to the tuning signal of the voltage controlled oscillator. Since the added precharge operation is performed, the reference signal generated by the operational amplifier controlled according to the setting data to the variable frequency dividing means is applied to the integrating means composed of the low-pass filter and negatively fed back to the operational amplifier. The ratio without deteriorating the characteristics. In specific simple configuration,
It is possible to obtain a high-speed lock-up circuit in a PLL that can perform a lock-up operation at high speed.

According to the fifth aspect, the phase comparison means for comparing the phases of the reference signal and the comparison signal to derive an output corresponding to the phase difference, the charge pump receiving the output of the phase comparison means, Integrating means comprising a low-pass filter for integrating the output of the charge pump; voltage-controlled oscillating means for receiving the output of the integrating means; a prescaler for dividing the output of the voltage-controlled oscillating means; and further dividing the output of the prescaler And a variable frequency dividing means comprising a programmable divider for applying the comparison signal to the phase comparing means, wherein a reference signal is applied to a + input terminal, and an output of the charge pump is applied to a-input terminal. And an operational amplifier applied to the variable frequency dividing means comprising the programmable divider. And a reference signal generating means for generating a predetermined reference signal in accordance with a control signal from the control means and applying the generated reference signal to a + input terminal of the operational amplifier, wherein the control means comprises the programmable divider. By controlling ON / OFF of the output of the operational amplifier in accordance with the setting data to the variable frequency dividing means, negatively feeding back the negative input terminal of the operational amplifier, and applying the result to the integrating means comprising the low-pass filter, Since a precharge operation of adding a reference signal to the tuning signal of the voltage controlled oscillator is performed, a reference signal generated by an operational amplifier controlled according to setting data to the variable frequency divider is integrated by a low-pass filter. Operational amplifier applied to the means By negative feedback, without characteristic deterioration, a relatively simple configuration, it is possible to obtain a fast lock-up circuit in the PLL capable of lockup operation at high speed.

According to the sixth invention, a desired reference signal is selected from the reference signals generated by the control signal having a predetermined control number by the control means in accordance with the setting data to the variable frequency dividing means. Since a precharge operation of adding a reference signal to the tuning signal of the voltage controlled oscillator is performed, a desired reference signal is selected in accordance with the setting data to the variable frequency divider, thereby deteriorating characteristics. And a high-speed lock-up circuit in a PLL capable of performing a high-speed lock-up operation with a relatively simple configuration.

According to the seventh aspect, the reference signal generating means generates a reference signal corresponding to the setting data to the variable frequency dividing means, and adds the reference signal to the tuning signal of the voltage controlled oscillation means. Since the charging operation is performed, the reference signal is generated in accordance with the setting data to the variable frequency dividing means, so that the lockup operation can be performed at a higher speed with a relatively simple configuration without characteristic deterioration. A high-speed lock-up circuit in a PLL can be obtained.

According to the eighth aspect, a reference signal is generated by the reference signal generating means comprising a D / A converter in accordance with the setting data to the variable frequency dividing means, and a tuning signal of the voltage controlled oscillating means is generated. , A precharge operation of adding a reference signal to the D / A corresponding to the setting data to the variable frequency dividing means is performed.
By generating a reference signal by the converter, a relatively simple configuration without deterioration of characteristics
It is possible to obtain a high-speed lock-up circuit in a PLL capable of further increasing the lock-up operation.

According to the ninth aspect, the phase comparison means for comparing the phases of the reference signal and the comparison signal to derive an output according to the phase difference, the charge pump receiving the output of the phase comparison means, Integrating means comprising a low-pass filter for integrating the output of the charge pump; voltage-controlled oscillating means receiving the output of the integrating means; dividing the output of the voltage-controlled oscillating means and applying the frequency-divided signal to the phase comparing means as the comparison signal In a PLL circuit provided with a variable frequency divider composed of a programmable divider, an operational amplifier that applies a reference signal to a + input terminal and applies an output of the charge pump to a − input terminal, and the programmable divider Control means controlled in accordance with setting data to the variable frequency dividing means; And a reference signal generating means comprising a D / A converter for generating a predetermined reference signal in accordance with the setting data to the variable frequency dividing means comprising the D / A converter and applying the reference signal to the + input terminal of the operational amplifier. An on / off control of an output of the operational amplifier in accordance with frequency setting data to a variable frequency dividing means comprising the programmable divider, to provide a negative feedback to a negative input terminal of the operational amplifier, and an integrating means comprising the low-pass filter; To perform a precharge operation of adding a reference signal corresponding to the set frequency of the variable frequency divider to the tuning signal of the voltage controlled oscillator, so that the frequency setting data to the variable frequency divider is By generating a reference signal by a D / A converter corresponding to Without characteristic deterioration, a relatively simple configuration, it is possible to obtain a fast lock-up circuit in the PLL capable of lockup operation even faster.

According to the tenth aspect, the phase comparison means for comparing the phases of the reference signal and the comparison signal to derive an output corresponding to the phase difference, the charge pump receiving the output of the phase comparison means, Integrating means comprising a low-pass filter for integrating the output of the charge pump; voltage-controlled oscillating means for receiving the output of the integrating means; a prescaler for dividing the output of the voltage-controlled oscillating means; and further dividing the output of the prescaler And a variable frequency dividing means comprising a programmable divider for applying the comparison signal to the phase comparing means, wherein a reference signal is applied to a + input terminal, and an output of the charge pump is applied to a-input terminal. And an operational amplifier applied to the variable frequency dividing means comprising the programmable divider. A reference signal generator comprising a control means to be controlled and a D / A converter for generating a predetermined reference signal corresponding to the setting data to the variable frequency dividing means comprising the programmable divider and applying the reference signal to the + input terminal of the operational amplifier. Means for controlling ON / OFF of an output of the operational amplifier according to frequency setting data to a variable frequency dividing means comprising the programmable divider, and negatively feeds back to a negative input terminal of the operational amplifier. At the same time, by applying to the integrating means comprising the low-pass filter, a precharge operation of adding a reference signal corresponding to the set frequency of the variable frequency dividing means to the tuning signal of the voltage controlled oscillating means is performed. D / A corresponding to the frequency setting data to the formula frequency dividing means By generating a reference signal by inverter, without characteristic deterioration, a relatively simple configuration, it is possible to obtain a fast lock-up circuit in the PLL capable of lockup operation even faster.

According to the eleventh aspect, the phase comparison means for comparing the phases of the reference signal and the comparison signal to derive an output corresponding to the phase difference, the charge pump receiving the output of the phase comparison means, Integrating means for integrating the output of the charge pump; voltage-controlled oscillating means for receiving the output of the integrating means; variable frequency dividing for dividing the output of the voltage-controlled oscillating means and applying the divided signal to the phase comparing means as the comparison signal Means for performing a precharge operation of adding a reference signal to a tuning signal of the voltage-controlled oscillating means in accordance with the setting data to the variable frequency dividing means. Timing generating means for synchronizing the reference signal and the comparison signal in response to the setting data input is provided. It is possible to obtain a high-speed lock-up circuit that can quickly and accurately lock-up operation in stable operation by ensuring timing between No. and the comparison signal.

According to the twelfth aspect, the phase comparison means for comparing the phases of the reference signal and the comparison signal to derive an output corresponding to the phase difference, the charge pump receiving the output of the phase comparison means, Integrating means comprising a low-pass filter for integrating the output of the charge pump; voltage-controlled oscillating means for receiving the output of the integrating means; a prescaler for dividing the output of the voltage-controlled oscillating means; and further dividing the output of the prescaler And a variable frequency divider comprising a programmable divider to be applied to the phase comparator as the comparison signal, wherein a tuning signal of the voltage controlled oscillator is adjusted in accordance with data set to the variable frequency divider. Performs a precharge operation of adding a reference signal to the input signal, and responds to a setting data input to the variable frequency dividing means. Timing generating means for synchronizing the reference signal and the comparison signal by controlling the prescaler, the programmable divider and the phase comparing means in synchronization with the reference signal is provided. As a result, a high-speed lock-up circuit capable of accurately performing the lock-up operation at a high speed with a stable operation can be obtained.

According to the thirteenth aspect, phase comparing means for comparing the phases of the reference signal and the comparison signal to derive an output corresponding to the phase difference, a charge pump receiving the output of the phase comparing means, Integrating means comprising a low-pass filter for integrating the output of the charge pump; voltage-controlled oscillating means for receiving the output of the integrating means; a prescaler for dividing the output of the voltage-controlled oscillating means; and further dividing the output of the prescaler And a variable frequency dividing means comprising a programmable divider for applying the comparison signal to the phase comparing means, wherein a reference signal is applied to a + input terminal, and an output of the charge pump is applied to a-input terminal. And an operational amplifier applied to the variable frequency dividing means comprising the programmable divider. A reference signal generator comprising a control means to be controlled and a D / A converter for generating a predetermined reference signal corresponding to the setting data to the variable frequency dividing means comprising the programmable divider and applying the reference signal to the + input terminal of the operational amplifier. Means for controlling ON / OFF of an output of the operational amplifier in accordance with setting data to a variable frequency dividing means comprising the programmable divider, and a negative feedback to a negative input terminal of the operational amplifier; In addition, by applying the voltage to the integrator comprising the low-pass filter, a precharge operation of adding a reference signal to the tuning signal of the voltage controlled oscillator is performed, and in response to setting data input to the variable frequency divider. The prescaler and the programmable data are synchronized with the reference signal. Is provided with the timing generating means for synchronizing the said comparison signal and said reference signal by controlling the divider and the phase comparing means,
By ensuring the timing between the reference signal and the comparison signal by the timing generation means, it is possible to obtain a high-speed lock-up circuit capable of performing the lock-up operation accurately and stably with a stable operation.

[Brief description of the drawings]

FIG. 1 shows a PLL according to a first embodiment of the present invention.
FIG. 1 is an overall configuration diagram showing a circuit.

FIG. 2 is a circuit diagram illustrating a reference voltage generation circuit unit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing specific numerical examples for explaining a reference voltage generation circuit unit according to the first embodiment of the present invention;

FIG. 4 is a waveform chart showing switch operation timing and lock-up according to the first embodiment of the present invention.

FIG. 5 is a PLL according to a second embodiment of the present invention.
FIG. 1 is an overall configuration diagram showing a circuit.

FIG. 6 shows a D / A according to a second embodiment of the present invention.
FIG. 2 is a configuration diagram illustrating a converter unit.

FIG. 7 is a waveform chart showing switch operation timing and lock-up according to a second embodiment of the present invention.

FIG. 8 is a PLL according to a third embodiment of the present invention.
FIG. 1 is an overall configuration diagram showing a circuit.

FIG. 9 is a waveform chart showing switch operation, operation timing of a timing generation circuit, and lock-up in a third embodiment according to the present invention.

FIG. 10 is an overall configuration diagram showing a conventional PLL circuit.

FIG. 11 is a characteristic diagram showing the relationship between the frequency of the voltage controlled oscillator and the tuning voltage.

FIG. 12 is a waveform chart showing lockup in a conventional PLL circuit.

[Explanation of symbols]

1 reference oscillator, 2 reference divider, 3 prescaler, 4 programmable divider, 5 phase comparator, 6 charge pump, 7 low-pass filter,
8 voltage controlled oscillator, 9 control circuit, 10 operational amplifier, 11 switch, 12 reference potential generation circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 CC01 CC15 CC24 CC38 CC41 CC52 CC53 DD06 DD08 EE10 EE18 GG01 GG07 HH03 KK03 PP03 QQ09 RR12 RR17 RR20

Claims (13)

[Claims] 1. A phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output according to the phase difference, a charge pump receiving the output of the phase comparison means, and integrating the output of the charge pump. And a variable frequency dividing means for dividing the output of the voltage controlled oscillating means and applying the divided signal to the phase comparing means as the comparison signal. A high-speed lock-up circuit in the circuit, wherein a precharge operation of adding a reference signal to a tuning signal of the voltage controlled oscillator is performed in accordance with data set in the variable frequency divider. 2. A phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output according to the phase difference, a charge pump receiving the output of the phase comparison means, and integrating the output of the charge pump. And a variable frequency dividing means for dividing the output of the voltage controlled oscillating means and applying the divided signal to the phase comparing means as the comparison signal. In the circuit, an operational amplifier controlled in accordance with setting data to the variable frequency divider is provided, and a precharge operation of adding a reference signal to a tuning signal of the voltage controlled oscillator in accordance with an output of the operational amplifier is performed. Characterized high-speed lock-up circuit. 3. A phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output corresponding to the phase difference, a charge pump receiving the output of the phase comparison means, and integrating the output of the charge pump. Integrating means comprising a low-pass filter, a voltage-controlled oscillating means for receiving an output of the integrating means, a variable frequency-dividing means for dividing the output of the voltage-controlled oscillating means and applying the divided signal to the phase comparing means as the comparison signal. In the PLL circuit, there is provided an operational amplifier which is applied with an output of the charge pump as an input and is controlled in accordance with setting data to the variable frequency dividing means, and outputs an output of the operational amplifier to an integrating means comprising the low-pass filter. By applying the precharge operation, a precharge operation of adding a reference signal to the tuning signal of the voltage controlled oscillator is performed. High-speed lock-up circuit. 4. A phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output corresponding to the phase difference, a charge pump receiving the output of the phase comparison means, and integrating the output of the charge pump. Variable means comprising an integrating means comprising a low-pass filter, a voltage-controlled oscillating means for receiving the output of the integrating means, and a programmable divider for dividing the output of the voltage-controlled oscillating means and applying the frequency-divided signal as the comparison signal to the phase comparing means. PLL provided with frequency dividing means
In the circuit, a reference signal is applied to a + input terminal, and an output of the charge pump is applied to an-input terminal, and the operational amplifier is controlled in accordance with setting data to a variable frequency dividing means including the programmable divider. Control means, and a reference signal generating means for generating a predetermined reference signal in accordance with a control signal from the control means and applying the generated reference signal to a + input terminal of the operational amplifier, wherein the control means is a variable signal comprising the programmable divider. The output of the operational amplifier is ON / OFF controlled in accordance with the setting data to the formula frequency dividing means, and the negative feedback to the negative input terminal of the operational amplifier is performed. The reference signal is used as the tuning signal for the control oscillator. Fast lock-up circuit and performs a precharge operation to add. 5. A phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output corresponding to the phase difference, a charge pump receiving the output of the phase comparison means, and integrating the output of the charge pump. Integrating means comprising a low-pass filter, a voltage-controlled oscillating means for receiving the output of the integrating means, a prescaler for dividing the output of the voltage-controlled oscillating means, and further dividing the output of the prescaler as the comparison signal. Variable frequency dividing means comprising a programmable divider to be applied to the phase comparing means
In the L circuit, a reference signal is applied to a + input terminal and an output of the charge pump is applied to an-input terminal, and is controlled in accordance with setting data to a variable frequency dividing means including the programmable divider and the programmable divider. And a reference signal generating means for generating a predetermined reference signal in accordance with a control signal from the control means and applying the generated reference signal to a + input terminal of the operational amplifier, wherein the control means comprises the programmable divider. By controlling ON / OFF of the output of the operational amplifier in accordance with the setting data to the variable frequency dividing means, negatively feeding back the negative input terminal of the operational amplifier, and applying the result to the integrating means comprising the low-pass filter, Reference to tuning signal of voltage controlled oscillator Fast lock-up circuit and performs a precharge operation for adding items. 6. The voltage control circuit according to claim 1, wherein the control means selects a desired reference signal from reference signals generated by a control signal having a predetermined control number in accordance with setting data to the variable frequency dividing means. 6. The high-speed lockup circuit according to claim 1, wherein a precharge operation for adding a reference signal to a tuning signal of the oscillation unit is performed. 7. A precharge operation in which a reference signal is generated by a reference signal generating means in accordance with setting data to said variable frequency dividing means and a reference signal is added to a tuning signal of said voltage controlled oscillating means. 6. The high-speed lockup circuit according to claim 1, wherein: 8. A reference signal generating means comprising a D / A converter, generates a reference signal corresponding to setting data to said variable frequency dividing means, and adds a reference signal to a tuning signal of said voltage controlled oscillating means. 6. The high-speed lock-up circuit according to claim 1, wherein a charge operation is performed. 9. A phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output according to the phase difference, a charge pump receiving the output of the phase comparison means, and integrating the output of the charge pump. Variable means comprising an integrating means comprising a low-pass filter, a voltage-controlled oscillating means for receiving the output of the integrating means, and a programmable divider for dividing the output of the voltage-controlled oscillating means and applying the frequency-divided signal as the comparison signal to the phase comparing means. PLL provided with frequency dividing means
In the circuit, a reference signal is applied to a + input terminal, and an output of the charge pump is applied to an-input terminal, and the operational amplifier is controlled in accordance with setting data to a variable frequency dividing means including the programmable divider. A reference signal generating means comprising a D / A converter for generating a predetermined reference signal corresponding to the setting data to the variable frequency dividing means comprising the programmable divider and applying the reference signal to the + input terminal of the operational amplifier. And the control means turns on the output of the operational amplifier in accordance with frequency setting data to a variable frequency dividing means comprising the programmable divider.
/ OFF control to apply negative feedback to the negative input terminal of the operational amplifier and to apply it to the integrating means comprising the low-pass filter, so that the tuning signal of the voltage-controlled oscillating means can be adjusted according to the set frequency of the variable frequency dividing means. A high-speed lock-up circuit for performing a precharge operation of adding a reference signal. 10. A phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output according to the phase difference, a charge pump receiving the output of the phase comparison means, and integrating the output of the charge pump. Integrating means comprising a low-pass filter, a voltage-controlled oscillating means for receiving the output of the integrating means, a prescaler for dividing the output of the voltage-controlled oscillating means, and further dividing the output of the prescaler as the comparison signal. A variable frequency dividing means comprising a programmable divider to be applied to the phase comparing means.
In the LL circuit, a reference signal is applied to a + input terminal and an output of the charge pump is applied to an-input terminal, and control is performed in accordance with setting data to a variable frequency dividing means including the programmable divider and the programmable divider. And a predetermined reference signal corresponding to the setting data to the variable frequency dividing means comprising the programmable divider.
A reference signal generating means comprising a D / A converter to be applied to an input terminal;
The output of the operational amplifier is ON / OFF controlled in accordance with frequency setting data to the variable frequency divider comprising the programmable divider, and negatively fed back to the negative input terminal of the operational amplifier. A high-speed lock-up circuit for performing a precharge operation of applying a reference signal according to a set frequency of a variable frequency divider to a tuning signal of the voltage controlled oscillator by applying the voltage. 11. A phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output according to the phase difference, a charge pump receiving the output of the phase comparison means, and integrating the output of the charge pump. And a variable frequency dividing means for dividing the output of the voltage controlled oscillating means and applying the divided signal to the phase comparing means as the comparison signal. The circuit performs a precharge operation of adding a reference signal to a tuning signal of the voltage controlled oscillator in accordance with setting data to the variable frequency dividing means, and responds to setting data input to the variable frequency dividing means. And a timing generating means for synchronizing the reference signal and the comparison signal. 12. A phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output according to the phase difference, a charge pump receiving the output of the phase comparison means, and integrating the output of the charge pump. Integrating means comprising a low-pass filter, a voltage-controlled oscillating means for receiving the output of the integrating means, a prescaler for dividing the output of the voltage-controlled oscillating means, and further dividing the output of the prescaler as the comparison signal. A variable frequency dividing means comprising a programmable divider to be applied to the phase comparing means.
The LL circuit performs a precharge operation of adding a reference signal to a tuning signal of the voltage controlled oscillator in accordance with setting data to the variable frequency dividing means, and responds to setting data input to the variable frequency dividing means. And a timing generating means for synchronizing the reference signal and the comparison signal by controlling the prescaler, the programmable divider and the phase comparing means in synchronization with the reference signal. 13. A phase comparison means for comparing the phases of a reference signal and a comparison signal to derive an output according to the phase difference, a charge pump receiving the output of the phase comparison means, and integrating the output of the charge pump. Integrating means comprising a low-pass filter, a voltage-controlled oscillating means for receiving the output of the integrating means, a prescaler for dividing the output of the voltage-controlled oscillating means, and further dividing the output of the prescaler as the comparison signal. A variable frequency dividing means comprising a programmable divider to be applied to the phase comparing means.
In the LL circuit, a reference signal is applied to a + input terminal and an output of the charge pump is applied to an-input terminal, and control is performed in accordance with setting data to a variable frequency dividing means including the programmable divider and the programmable divider. And a predetermined reference signal corresponding to the setting data to the variable frequency dividing means comprising the programmable divider.
A reference signal generating means comprising a D / A converter to be applied to an input terminal;
The output of the operational amplifier is turned ON / OFF in accordance with the setting data to the variable frequency divider comprising the programmable divider.
A precharge operation of adding a reference signal to a tuning signal of the voltage controlled oscillation unit by performing OFF control, performing a negative feedback to a negative input terminal of the operational amplifier, and applying the same to an integration unit including the low pass filter, Timing generating means for synchronizing the reference signal and the comparison signal by controlling the prescaler, the programmable divider and the phase comparing means in synchronization with the reference signal in response to the setting data input to the variable frequency dividing means A high-speed lock-up circuit characterized by providing: