KR100569878B1 - The Structure of PLL Having Performance Property Through Wide Frequency Bandwidth - Google Patents

Abstract

The present invention provides a D / A converter for converting a digital signal for controlling a power supply voltage of a delay circuit in a voltage controlled oscillator (VCO) into an analog voltage, and the output voltage of the D / A converter with an output voltage having the same potential in the VCO. A phase locked loop (PLL) structure including a VCO power supply voltage control device including a regulator applied to a delay circuit portion is provided. The present invention preferably provides a PLL structure further comprising a bias array circuit for providing the N bias currents controlled by the N-bit digital input signal by the delay circuit in the VCO.

D / A Converters, Regulators, PLLs, Bias

Description

Phase Synchronous Loop Structure Operates over Wide Frequency Bands {The Structure of PLL Having Performance Property Through Wide Frequency Bandwidth}             

1 is a structural diagram of a typical PLL according to the prior art

2 is a structural diagram of a PLL using a D / A converter according to the prior art

3 is a structural diagram of a PLL using a regulator according to the prior art

4 is a schematic ring-oscillator structure of a conventional VCO

5 is a structural diagram of a PLL capable of operating in a wide frequency band according to the present invention

6 is a structural diagram of a ring-oscillator structure of a VCO according to the present invention and a delay circuit according to the first aspect of the present invention.

7 is a configuration diagram of a delay circuit according to the second side of the VCO according to the present invention;

8 shows an example in which a control signal is input to a D / A converter and a delay circuit presented as a preferred embodiment of the present invention.

<Code Description of Main Parts of Drawing>

1: D / A converter 2: regulator

3: PFD 4: CP circuit

5: loop filter 6: VCO

7: 1 / N divider 8: N binary array

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop (hereinafter referred to as PLL) structure including a delay circuit in a voltage controlled oscillator (hereinafter referred to as VCO), and more particularly to a digital / analog converter. (Hereinafter referred to as D / A converter), it controls the power supply voltage of delay circuit in VCO and supplies bias current supplied in delay circuit according to each power supply voltage potential as needed. It relates to a PLL structure capable of operating in a wider frequency band from lower frequencies to more than a few GHz.

Recently, optical disc recording and reproducing apparatus such as compact disk (CD) and digital versatile disk (DVD) have to satisfy various standards at the same time, so the PLL used for this requires a wide frequency operating range. In addition, PLLs used for high-speed communication must be designed and changed at each time in order to meet various specifications, but there is an advantage that a quick application can be made when designing a PLL that supports a wide operating range.

The most typical type of PLL that can be found in many published articles and patent texts is shown in FIG. 1. The Phase Frequency Detector (hereinafter referred to as PFD) compares the reference clock with the output clock of the frequency down by 1 / N. The result is an up / down signal with charge-pump (CP). It is delivered to the circuit) and outputs the control voltage to control the frequency of VCO from CP circuit by supplying or removing current by the pulse width of up signal or down signal. At this time, the control signal is supplied to the VCO through a loop filter to ensure stable operation of the entire PLL circuit. In this case, the VCO gain needs to be increased to operate the PCO's VCO over a wide frequency range. However, in this case, there is a problem in that it is sensitive to noise in the voltage for controlling the frequency of the VCO, so that the jitter characteristic of the entire PLL becomes worse and the variation in the VCO gain according to the process increases.

2 illustrates a conventionally proposed structure for operating a PLL in a wide frequency region without increasing the VCO gain as a PLL structure applied to an optical disk. In this case, the operation of the VCO is controlled by utilizing the output signal of the D / A converter as another control signal to the VCO in addition to the control voltage supplied to the VCO from the existing CP circuit. That is, the D / A converter output serves as a control signal equivalent to the output signal of the CP circuit, which is a control signal used to control the operation of the VCO in a PLL of a typical structure. In the PLL circuit, the D / A converter output serves to select the operating area of the VCO, and the output of the CP circuit serves to finely control the operation of the VCO in the operating area. However, applying the D / A output directly to the VCO may affect the stability of the PLL operation. Therefore, a loop filter (hereafter referred to as LF) that acts as a separate low pass filter (LPF) is added. As needed. Finally, in this structure, a large capacity capacitor, a passive element, is attached to the output of the D / A converter with LF. In this case, there is a disadvantage that a separate pin must be used for this purpose. In addition, since the swing-width of the delay circuit in the VCO is always fixed, the PLL structure has a limitation in that it is widely applied to general applications as well as high-speed operation.

FIG. 3 is a structure previously disclosed in the paper. In order to control the VCO in the PLL, the operating frequency of the VCO is controlled by changing the power supply voltage supplied to the VCO without using a separate bias voltage or current. . As shown in FIG. 4, the VCO has a general ring-oscillator structure composed of inverters, and a circuit in a dotted line circle shows a detailed circuit diagram of each delay circuit. The capacitor in the detailed circuit diagram shows an equivalent capacitor of passive element components acting as a load on the output terminal of each delay circuit. In the case of using the ring oscillator of FIG. 4 as the VCO of FIG. 3, the current driving the equivalent capacitor acting as a load of each delay circuit due to the characteristics of the ring oscillator in which the input and the output are reversed is determined by the PMOS and NMOS transistors constituting the delay circuit. Since the voltage difference between the gate and source terminals is determined by the VDD-VSS value, the lower the power supply voltage, the lower the operating frequency of the ring oscillator. Since the VCO's operating range is affected by the minimum voltage at which the delay circuits can operate and the actual supply voltage, the VCO operating range is greatly limited in the structure using low supply voltage due to process development. It has a structural drawback.

The present invention has been made to overcome the limitations of the prior art, and an object thereof is to provide a PLL structure capable of controlling a power supply voltage of a delay circuit in a VCO through a D / A converter.

Another object of the present invention is to provide a function of supplying the bias current supplied in the delay circuit constituting the VCO corresponding to each power supply voltage potential so that operation in a wider frequency band from a low frequency of several MHz to a few GHz or more is possible. To provide a possible PLL structure.

 Another object of the present invention is to reduce the swing-width of the delay circuit causing the most noise when operating at high frequency in the control method of the VCO additionally minimizes the effect of noise components caused in the PLL itself. To provide a PLL structure that can be obtained.

It is still another object of the present invention to provide a PLL structure which can be applied to an optical disc recording and reproducing apparatus related to a CD or a DVD, and is widely applicable to communication applications and microprocessor fields requiring high frequencies of gigabit or more. .

In order to achieve the above object, the present invention provides a D / A converter for converting a digital signal for controlling a power supply voltage of a delay circuit in a VCO into an analog voltage, and an output voltage having the same potential as an output voltage of the D / A converter. Provided is a PLL structure including a VCO supply voltage control device including a regulator applied to a delay circuit in a VCO.

The present invention preferably provides a PLL structure further comprising a bias array circuit for providing the N bias currents controlled by the N-bit digital input signal by the delay circuit in the VCO.

The present invention preferably provides a PLL structure in which the N-bit digital input signal is interlocked with the input signal of the D / A converter.

The present invention preferably provides a PLL structure in which the N-bit digital input signal is a signal obtained by converting a complementary signal of an input signal of a D / A converter into a thermometer code.

The present invention preferably provides a PLL structure in which the N bias current values are the same or have a binary weighted relationship.

Hereinafter, the content of the present invention will be described in more detail with reference to preferred embodiments.

5 is a block diagram of the overall PLL structure including the VCO control technique presented as a preferred embodiment according to the present invention. The PLL according to the present embodiment includes a D / A converter 1, a regulator 2, a PFD 3, a CP circuit 4, an LF 5, a VCO 6 and a 1 / N divider 7. It is configured by. The control technique of the VCO according to the present invention takes a manner in which the output of the CP circuit 4 is supplied with a bias voltage through the LF 5 to control the VCO 6 in a typical manner. However, in order to operate the VCO in a wide frequency range, the VCO is configured and the power voltage of the delay circuit that generates the frequency can be changed by using a D / A converter. Conventionally invented circuits tend to lower the operating frequency of the VCO according to a general tendency when the power supply voltage is lowered. However, in the present invention, a separate bias is supplied through the CP circuit into the delay circuit to operate even when the power supply voltage is lowered. It can compensate for the decrease of current. Therefore, when the output terminal of the delay circuit is driven with the same current, as the power supply voltage is lowered, the swing-width of the VCO stage is reduced, so that the VCO can be operated at high speed.

Figure 6 shows an example implemented by applying the VCO control technology presented as a preferred embodiment according to the present invention. The delay circuit used in FIG. 6 is a delay circuit generally used in a conventional PLL. However, the conventional structure is different from the method proposed by the present invention in that all the fixed power supply voltage is used. In FIG. 6, the triangular shape shows a delay circuit constituting the VCO, and the detailed structure of the delay circuit is shown in a large dotted circle below. In the delay circuit shown in detail, VBP and VBN represent control signals passing through the loop filter, and the same bias voltage is jointly input to all delay circuits in the VCO to control the VCO.

When operating the VCO in the low frequency band, the digital code is inputted to output high analog voltage to the D / A converter, and the swing-width of the circuit in the VCO is increased by increasing the power supply voltage in the delay circuit of the VCO. In addition, when the bias current values supplied through the VBP and the VBN are applied with a small value, the operation of the delay circuit of the final VCO may be performed in a low frequency band. On the contrary, when operating the VCO in the high frequency band, input a digital code so that a small analog voltage is output to the D / A converter, so that the power supply voltage in the delay circuit of the VCO becomes a small value, thereby reducing the swing-width of the circuit in the VCO. Reduce it small. In addition, if the bias current values supplied through VBP and VBN are made large, fast swinging with a small swing-width is possible, and the delay circuit in the VCO can operate at high speed.

However, applying the typical delay circuit of FIG. 6, when the VCO is operating in the high frequency band, the VBP voltage can be expected to operate only near the low voltage, and the VBN voltage can guarantee the valid operation only at the high voltage. Can be. In addition, if the VCO operates in the lower frequency band, the intended operation can be expected near the high voltage, and near the low voltage. Therefore, although it can be expected to operate up to a higher frequency range than the general structure, the upper limit is limited by the VBP voltage and VBN voltage range.

7 is a conceptual diagram of a delay circuit applicable to a VCO further proposed in the present invention to overcome this limitation. A bias array circuit that provides N bias currents controlled by the N-bit digital input signal to allow an additional bias supply by an external N-bit digital code as well as a method of supplying a bias to a conventional general delay circuit. (8) is complemented. Such a circuit is preferably designed in conjunction with the input signal of the D / A converter 1. The operation process is as follows.

When the VCO operates at a low frequency, the D / A converter 1 receives a digital code having a high binary value of a previously set N-bit corresponding to the corresponding frequency band. As a result, an analog signal of high potential is output to the output of the D / A converter 1, and this value is applied as an input signal of the regulator 2 so that the regulator 2 outputs an output voltage having the same potential. The stage is supplied with a power supply voltage so that a high power supply voltage is applied to the VCO stage 6 as a result. At this time, N-bit digital signals D0,... For bias adjustment input to each of the delay circuits in the VCO 6. , Dn-1, Dn preferably allow a signal converted from a complementary signal of an N-bit digital signal input to a D / A converter to a thermometer code is applied. That is, for example, when "10" is applied to the D / A converter as a 2-bit digital signal, the delay circuit has the digital signal of "001", the thermometer code of "01", its complementary signal, respectively, D2, D1, D0. It must be applied as a signal. For reference, when the digital signal input to the delay circuit is "1", the switch is turned on and an additional bias current is supplied to the circuit. When the digital signal input is "0", the switch is turned off and the supply of additional bias current is cut off. . Therefore, in the above example, when "111" is applied as the digital input signal of the delay circuit, the bias current having the largest magnitude is additionally supplied in the delay circuit in addition to the bias current supplied to the delay circuit by the VBP and VBN voltages. In the case of 000 ”, there is no bias current supplied in addition to the bias current supplied to the delay circuit by the VBP and VBN voltages. In summary, the digital input signal applied to the D / A converter and the delay circuit in the VCO when the D / A converter is controlled by the 2-bit digital signal is summarized in the table of FIG. 8. However, additional bias current i0,... Which is additionally supplied to the delay circuit. The, In-1, In values may all have the same value or may have a binary-weighted value. That is, it includes all cases that are applied by a combination of several possible values by the user's application.

In addition, the proposed structure of the present invention, in addition to the functional advantages that can operate in a wide range of frequency bands described above, in addition to the swing-width is reduced in high speed operation, in general, the high frequency of the PLL output When a clock output is required, it has the advantage of generating less noise than the noise generated at the VCO stage. Therefore, when applied to a system with many analog circuits, it is possible to obtain a high frequency output clock while minimizing the influence on the peripheral analog circuit operation when it is necessary to apply a high speed PLL. .

The PLL according to the present invention is provided with a function of controlling the power supply voltage of the delay circuit in the VCO through the D / A converter and supplying the bias current supplied in the delay circuit to correspond to the respective supply voltage potentials as necessary. It is possible to provide a PLL that can operate in a wider frequency band from a lower frequency to more than a few GHz.

In addition, the PLL according to the present invention, when operating at a high frequency in the control method of the VCO, by reducing the swing-width of the delay circuit that causes the most noise additionally minimizes the noise component caused in the PLL itself You can get

The PLL according to the present invention can be applied to an optical disc recording and reproducing apparatus related to a CD or a DVD, and can be widely applied to a communication application and a microprocessor that require a high frequency of more than a gigabit.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and modified within the scope of the present invention without departing from the spirit and scope of the present invention described in the claims below. It will be appreciated that it can be changed.

Claims (5)

A digital / analog converter for converting a digital signal for controlling the power supply voltage of the delay circuit in the voltage controlled oscillator into an analog voltage, and applying the output signal of the digital / analog converter to the delay circuit in the voltage controlled oscillator with an output voltage having the same potential. A phase synchronous loop structure comprising a power supply voltage control device of a voltage controlled oscillator including a regulator 2. The phase locked loop structure as claimed in claim 1, wherein the delay circuit portion in the voltage controlled oscillator includes a bias array circuit for providing N bias currents controlled by an N-bit digital input signal. 3. The phase-locked loop structure according to claim 2, wherein the N-bit digital input signal is interlocked with the input signal of the digital / analog converter. 4. The phase locked loop structure as claimed in claim 3, wherein the N-bit digital input signal is a signal obtained by converting a complement signal of an input signal of a digital / analog converter into a thermometer code. 3. The phase locked loop structure of claim 2, wherein the N bias current values are the same or have a binary weighted relationship.

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