JPH01238222A - Digital phase locked loop circuit - Google Patents

Abstract

PURPOSE:To obtain a digital phase locked loop small in a circuit scale by providing a digital phase difference detector, an LPF and a voltage controlled oscillator, and supplying the output signal of the voltage controlled oscillator to the phase difference detector as a comparing clock. CONSTITUTION:The output signal of the voltage controlled oscillator 3 is fed back to the phase difference detector 1, compared with a digital input signal and the detector generates a pulse with a pulse duration proportional to a phase difference. The pulse is passed through an LPF 2 to obtain an average direct current voltage as an error voltage, and this voltage controls the oscillator 3 to a direction for reducing a frequency difference and the phase difference between the output signal of the oscillator 3 and the input signal. When the oscillator 3 starts to change the frequency, it is continued until the frequency coincides with the phase, when they coincide, a loop is brought into a synchronizing state, thereafter, the output signal of the oscillator 3 follows the various changes of the frequency and the phase. In such a way, a circuit corresponding to the LPF part and the oscillating part of the conventional circuit is formed in an analog constitution, the circuit scale is made compact and a mounting area is reduced.

Description

[Detailed Description of the Invention] [Summary] Regarding a digital phase-locked loop circuit suitable for application to PCM equipment etc. that performs slave synchronization, the purpose of this invention is to reduce the circuit scale and improve the efficiency of the mounting area. A digital phase difference detector that detects the phase difference between an input signal and a comparison clock signal and outputs a signal with a pulse width corresponding to the size difference between the signals as a phase difference detection signal, and removes high frequency components from the detection signal. and a low-pass filter that outputs a voltage signal according to the phase difference, and a voltage controlled oscillator whose oscillation frequency changes using the voltage signal as a control voltage, and the output signal of the voltage controlled oscillator is used as the comparison clock signal. The signal is configured to be supplied to the phase difference detector as the phase difference detector.

[Industrial application field]

The present invention relates to a digital phase-locked loop circuit suitable for application to PCM equipment and the like that performs dependent synchronization.

[Conventional technology]

The phase-locked loop circuit (hereinafter referred to as PLL circuit) is
It has been widely used in fields such as communication equipment, measuring instruments, and various control equipment, and recently, digitally configured PLL circuits (hereinafter referred to as D
Various types of PLL circuits have been proposed.

FIG. 4 is a block diagram showing the configuration of such a PLL circuit, which includes a feedback loop consisting of a phase difference detector 20, a retiming circuit 21, a counter 22, a variable ring counter 23, and a frequency divider 24, and a variable ring counter 23. and an oscillator 25 that supplies a clock signal of a constant frequency to the oscillator 25.

The phase difference detector 20 detects the phase difference between the digital input signal Sa and the comparison clock signal sb supplied from the frequency divider 24, and generates a signal with a pulse width corresponding to the phase difference between both signals Sa and sb. It is output as a phase difference detection signal SC.

The retiming circuit 21 synchronizes the detection signal Sc with the clock signal Sd supplied from the frequency divider 24 and the clock signal Se supplied from the oscillator 25, and further outputs a pulse signal Sf of the number of pulses according to the phase difference. . The counter 22 counts the number of pulses of the pulse signal Sf, and when it reaches a constant value, outputs the pulse signal Sg to control the frequency division ratio of the variable ring counter 23. The ring counter 23 frequency-divides the clock signal Se from the oscillator 25 using a selected frequency division ratio, and outputs the frequency-divided output to the outside as an output signal sh, and also supplies it to the frequency divider 24.

The frequency divider 24 forms a comparison clock signal sb and a retiming clock signal Sd from the signal sh, and outputs them to the phase difference detector 20 and the retiming circuit 21, respectively.

According to such a configuration, the frequency division ratio of the variable ring counter 230 is controlled according to the phase difference between the digital input signal Sa and the comparison clock signal sb, and if the phases of both signals are not matched, the frequency division of the variable ring counter 23 is controlled. The comparison clock signal sb is adjusted to match the phase of the input signal Sa by changing the ratio.
control.

[Problem that the invention seeks to solve]

By the way, since the PLL circuit needs to be configured to have a function suitable for each device to which it is applied, conventional DPLL circuits are usually configured by combining several general-purpose ICs.

For this reason, the mounting area of the circuit becomes large, and for example,
When mounted on devices such as M devices for which miniaturization is desired, there is a problem in that it impedes miniaturization of these devices.

In this case, it may be possible to improve the efficiency of the mounting area by converting the entire DP/LL circuit into an LSI, but this is not the case when producing large quantities of circuits with the same function, and if this is not the case, there will be costs such as development costs. Problems arose, and it was practically impossible to incorporate all DPLL circuits into LSI.

SUMMARY OF THE INVENTION An object of the present invention is to obtain a digital phase-locked loop circuit that can reduce the circuit scale and improve the efficiency of the mounting area.

[Means for solving problems]

As shown in the principle diagram in Figure 1, a digital phase difference detector detects the phase difference between a digital input signal and a comparison clock signal and outputs a signal with a pulse width corresponding to the phase difference between both signals as a phase difference detection signal. 1, a low-pass filter 2 that removes high frequency components from the detection signal and outputs a voltage signal according to the phase difference, and a voltage-controlled oscillator 3 whose oscillation frequency changes using the voltage signal as a control voltage. , the output signal of the voltage controlled oscillator 3 is supplied to the phase difference detector 1 as a control comparison clock signal.

[For production]

The output signal of the voltage controlled oscillator 3 is fed back to the phase difference detector 1, where it is compared with the digital input signal. This phase difference detector 1 outputs a pulse signal with a pulse width proportional to the phase difference between the input signal and the output signal of the oscillator 3.

When this pulse signal is passed through a low-pass filter 2 and high frequency components are removed, an average DC voltage is obtained as an error voltage.
This error voltage controls the oscillator 3 in a direction that reduces the frequency and phase differences between the input signal and the output signal of the oscillator 3. Once the oscillator 3 starts changing its frequency, it continues this operation until the output signal of the oscillator 3 matches the frequency and phase of the input signal, at which point the loop enters a synchronized state.

Once in the synchronized state, the output signal of the oscillator 3 can follow any changes in frequency and phase of the input signal.

In addition, in the DPLL circuit, a low-pass filter section (counter 22) and a variable oscillation section (variable ring counter 232 oscillator 25) of a digital configuration have a relatively large mounting area.
By configuring the circuit with analog circuits, the circuit scale is miniaturized and the mounting area is made more efficient.

〔Example〕

FIG. 2 is a block diagram showing an embodiment of the present invention, which is composed of a feedback loop consisting of a phase difference detector 1, a low-pass filter 2, a voltage controlled oscillator 3, and a frequency divider 4, and a disconnection detector 5. has been done.

The phase difference detector 1 consists of switches 10 and 11 and a D-type flip-flop (hereinafter referred to as DFF) 12,
During normal operation, the digital input signal S1 is supplied to the CK input terminal of the DFF 12 via the switch 11, and the comparison clock signal S2 from the frequency divider 4 is supplied to the DFF via the switch IO.
12 D input terminals. When the switches 10 and 11 are switched, the ◇ output signal of the DFF 12 is supplied to the D input terminal via the switch 10, and the comparison clock signal S2 from the frequency divider 4 is supplied to the CK input terminal via the switch 11. Switching of the switches 10 and 11 is performed when the disconnection detector 5 detects a stop or abnormality in the input signal S1.

Both the low-pass filter (hereinafter referred to as LPF) 2 and the voltage-controlled oscillator (hereinafter referred to as VCOl) 3 are constructed of well-known analog circuits; for example, LPF2 is an active R
The C filter and VCO3 are each composed of an RC multi-by-break.

Next, the operation of the above embodiment will be explained with reference to the waveform diagram in FIG.

When the digital input signal 31 (FIG. 3A) is inputted manually, the switches 10 and 11 of the phase difference detector l enter the state shown in the figure, the input signal 31 is supplied to the CK input terminal of the DFF 12, and the comparison clock from the frequency divider 4 is input. Signal 32 (Figure 3B)
is supplied to the D input terminal. When the phases of both signals S1 and S2 are almost the same as shown in the figure, the DFF12
The Q output signal S3 becomes a 50% duty signal that changes to logic "1" or "0" with a probability of 1/2 at the rising edge of the input signal S1 (FIG. 3C).

When this signal 83 is input to the LPF2, the voltage level of the output signal S4 of the LPF2 becomes almost the center value (Fig. 3D
), therefore, the frequency of the output signal S5 of the VCO 3 is set to the center frequency, and after being divided by the frequency divider 4, it is supplied to the above-mentioned phase difference detector 1 as the comparison clock signal S2.

On the other hand, if the phase between the input signal S1 and the clock signal 82 is shifted, the probability that the Q output signal S3 of the DFF 12 changes to logic "L" or "0" at the rising edge of the input signal S1 becomes low. The signal S3 is a signal in which the logic "1" or "0" continues longer. Therefore, the voltage level of the output signal S4 of LPF2 becomes a value shifted from the center value, and therefore the frequency of the output signal S5 of VC○3 also shifts upward or downward with respect to the center frequency, following the change in the input signal S1. I'll go.

Whether the input signal S1 stops or remains logic “1” or “ for a certain period of time
If the state of "0" continues, the disconnection detection circuit 5 outputs the disconnection detection signal S6 and switches the switches IO and 11 of the phase difference detector 1. Therefore, the Q output signal is input to the D input terminal of the DFF 12. The comparison clock signal S2 is fed back to the CK input terminal via the switch 11. Therefore, the DFF 12 operates as a T-type flip-flop whose output signal is inverted every time a pulse signal arrives at the clock terminal. , outputs a Q output signal S3 that is inverted at every rising edge of the clock signal S2. Since this signal S3 is a signal with a duty of 50%, the voltage level of the output signal S4 of the LPF 2 is the center value, and the output of the VCO 3 is also Set to center frequency.

Therefore, even if the human powered unit 3 S1 is stopped or in an abnormal state, the output frequency of the VCO 3 will not reach the upper limit value or the lower limit value, but will be automatically set to the center frequency.

〔Effect of the invention〕

As explained in detail above, according to the DPLL circuit of the present invention, the circuits corresponding to the low-pass filter section and the oscillator section of the conventional DPLL circuit have an analog configuration, so the circuit scale can be reduced and the mounting area can be reduced. This made it possible to improve efficiency. Therefore, it has become possible to provide a DPLL circuit that does not impede the miniaturization of these devices even when applied to devices that require miniaturization, such as PCM devices that perform slave synchronization.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of a digital phase-locked loop circuit according to the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining the operation of FIG. 2. , Figure 4 is
FIG. 1 is a block diagram showing a conventional digital phase-locked loop circuit. 1... Phase difference detector, 2... Low pass filter, 3
...Voltage controlled oscillator.

Claims (1)

[Claims] (1) A digital phase difference detector that detects a phase difference between a digital input signal and a comparison clock signal and outputs a signal with a pulse width corresponding to the phase difference between both signals as a phase difference detection signal, and a high frequency component from the detection signal. and a voltage controlled oscillator whose oscillation frequency changes using the voltage signal as a control voltage, the output signal of the voltage controlled oscillator being compared with the output signal of the voltage controlled oscillator. A digital phase-locked loop circuit, characterized in that the clock signal is supplied to the phase difference detector.