JP2855612B2 - PLL circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a synthesizer oscillator using a phase locked loop.

[Prior Art] Conventionally, a frequency synthesizer using a PLL has been known.

FIG. 3 shows a conventional example. In FIG. 3, the output of the VCO 1 is applied to a phase comparator 3 via a programmable frequency divider 2, and the phase comparator 3 detects a phase difference from a reference frequency signal of a reference oscillator 4, VCO1
Give feedback to

The operation as a PLL is basically equivalent to that except for the programmable frequency divider 2 as shown in FIG.
The fact that the oscillation frequency _OSC of VCO1 in the figure becomes the reference frequency r means that the oscillation frequency of VCO1 in FIG.
_{The OSC} indicates that _OSC = N × r where N is the frequency division number of the programmable frequency divider 2.

Therefore, by switching the frequency division number N of the programmable frequency divider 2, a frequency N times the reference frequency r could be obtained.

[Problems to be solved by the invention]

In the conventional example shown in FIG. 3, the phase comparison operation is performed only in the cycle of the reference frequency r. Therefore, the reference frequency r
In order to obtain an output that is an integral multiple of 100 Hz as 100 Hz, for example, a phase error signal can be taken out only every 10 msec.
The filter must be sufficiently filtered to keep the control voltage of VCO1 constant. In other words, the natural frequency of the PLL is 100Hz
Must be much smaller. For this reason, even when phase jitter occurs in the oscillation output of the VCO 1 due to disturbance or the like, there is a disadvantage that the effect of suppressing the phase jitter by the loop operation is lost.

This problem will be described with reference to FIG. FIG. 5 is an equivalent circuit of FIG. 4 for explaining the operation of the conventional example shown in FIG. In FIG. 5, the output phase jitter component Φn (S) is superimposed on the output of VCO1. The equivalent phase jitter emphasis Φn (S) is an equivalently concentrated display of noise generated by all the blocks in the loop and induced noise from the outside.

From FIG. 5, Φ _OUT (S) = Φ _OSC (S) + Φn (S) And the control input of VCO1 is expressed as follows.

(VCO1 control input) = -K _D · F (S) · Φ _OUT (S) Therefore, the output phase of VCO1 is (K _OSC : Conversion gain of VCO1 (red / sec-V) Substituting this into Assuming that a typical active RC filter is used as the loop filter 5, Substituting this into Is represented In other words, It is expressed.

The equation shows that the cutoff frequency is ωn and the diping is a high-pass filter with ξ. That is,
The equation shows that low frequency components of the equivalent phase jitter Φn (S) in the loop are sufficiently suppressed, but high frequency components are output as they are.

Moreover, as described above, since the natural frequency ωn must be selected sufficiently smaller than the reference frequency r, only a very limited low frequency component can be suppressed in the equivalent phase jitter Φn (S) in the loop. There is a disadvantage that phase jitter remains in the output.

[Means for solving the problem]

The PPL circuit of the present invention divides the output of the voltage controlled oscillator by a frequency divider, detects a phase difference from a frequency reference signal by a phase comparator, and feeds back the same as a control input signal of the voltage controlled oscillator via a loop filter. In the PLL circuit,
Connect the input of the FM detector to the output of the voltage-controlled oscillator,
The output of the FM detector is added to the output of the loop filter via a high-pass filter, and is fed back as a control input signal of the voltage controlled oscillator.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the oscillation circuit according to the present invention. The FM detector 6 is connected to the output of the VCO 1, and the output of the FM detector 6 is applied to a second input of the adding circuit 10 via a high-pass filter 9 including a capacitor 7 and a resistor 8.
The first input of the adder circuit 10 is connected to the output of the loop filter 5, and the output of the adder circuit 10 is connected to the control input of VCO1.

FIG. 6 shows the equivalent circuit of FIG. The equation also holds in FIG. The output of the FM detector 6 is expressed by the following equation.

(Output of FM detector 6) = − ASΦ _OUT (S) (A: Conversion gain of FM detector 6 (V · sec / rad) Further, the transfer function F ′ (S) of the high-pass filter 9 is Therefore, the control input to VCO1 is expressed as follows (control input of VCO1) = − F ′ (S) · A · S · Φ _OUT (S) −K _D · F (S) · Φ _OUT ( S) Therefore, the output phase of VCO1: Φ _OSC (S) is Than this That is, when S is smaller than jωc On the other hand, when S is larger than jωc, That is, the relationship between the expressions indicates that even in the application example of the oscillation circuit according to the present invention shown in FIG. 1, even in the equivalent phase jitter Φn (S) in the loop, low frequency components are sufficiently suppressed. From the equation, the high frequency component of the equivalent phase jitter Φn (S) in the loop is also (1 + K _OSC ·
A) It was shown to be suppressed by a factor of one.

FIG. 2 shows a second applied example of the oscillation circuit according to the present invention. In configuration, a switch 11 is added before the second input of the adding circuit 10 as compared with the example shown in FIG. In the example shown in FIG. 2, the switch 11 is conducting during the normal operation,
The operation is exactly the same as in the example of FIG. However, in order to prevent the time required for switching the frequency division number N of the programmable frequency divider 2 to be changed once the PLL lock is lost and locked again, the present invention is applied only when the frequency division number N is switched. The feedback loop is opened.

FIG. 7 shows a third embodiment of the present invention. In this embodiment, a third input of the adder circuit 10 is provided, and the output of the variable DC voltage source 11 is connected to this input. A variable DC voltage source while the frequency division number N of the programmable frequency divider 2 is kept constant
The output 11 takes a constant value, and its magnitude is set so that the oscillation frequency of the VCO 1 becomes a predetermined frequency. Furthermore, although the voltage cannot be accurately controlled only by the variable DC voltage source 11, the circuit operates also as a PLL, and the output of the loop filter 5 is further applied to the VCO 1 to lock the PLL. As a specific example of the variable DC voltage source 11, a D / A converter can be used.

In this embodiment, the pull-in time of the PLL can be shortened.
That is, since the variable DC voltage source 11 applies a substantially predetermined voltage to the control input of the VCO 1 when the frequency division number N of the programmable frequency divider 2 is switched, the output of the loop filter 5 can handle only the remaining error. Since it is sufficient, the pull-in time can be easily reduced to 1/10 or less.

FIG. 8 shows a fourth embodiment according to the present invention. In the example shown in FIG. 7, the FM detector 6 is of a tuning type, and the voltage of the DC voltage source 11 is applied as a tuning voltage. That is, to suppress the phase jitter of the output of the frequency synthesizer oscillator, it is necessary to increase the gain A of the FM detector 6 according to the equation. However, the gain A of the FM detector 6 that attempts to increase the frequency change width of the frequency synthesizer oscillator becomes small. To avoid this, the center frequency of the operation of the FM detector 6 is always set near the oscillation frequency by the voltage from the power supply 11.

〔The invention's effect〕

As described above, according to the present invention, there is an effect that a synthesizer oscillator having a small output phase jitter can be configured. In particular, a great effect can be expected in applications where the reference frequency is lowered.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of another embodiment, FIG. 3 is a diagram of a conventional example, FIG. FIG. 6 is an equivalent circuit diagram for analyzing the operation of the conventional example, FIG. 6 is an equivalent circuit diagram for explaining the effect of the oscillator of the present invention, FIG. 7 is a third embodiment diagram, and FIG. FIG. 4 is an embodiment diagram of FIG. 1 VCO 2 Programmable frequency divider 3 Phase comparator 4 Reference oscillator 5 Loop filter
6 ... FM detector, 7 ... Capacitor, 8 ... Resistance, 9 ...
... High pass filter, 10 ... Addition circuit.

Claims (1)

(57) [Claims] An output of a voltage controlled oscillator is frequency-divided by a frequency divider, a phase difference from a frequency reference signal is detected by a phase comparator, and is fed back as a control input signal of the voltage controlled oscillator via a loop filter. In the PLL circuit, the input of the FM detector is connected to the output of the voltage-controlled oscillator, and the output of the FM detector is added to the output of the loop filter via a high-pass filter as a control input signal of the voltage-controlled oscillator. A PLL circuit characterized by feedback.