JPH0418306Y2 - - Google Patents

Description

[Detailed description of the invention] A. Industrial field of application The present invention relates to an external synchronization circuit for a color television camera, and in particular to a video camera which synthesizes video signals based on a reference signal with a frequency four times that of the subcarrier. The present invention is suitable for application to an external synchronization circuit of a color television camera having a signal synthesis circuit.

B. Summary of the invention The present invention oscillates a reference signal with a frequency four times that of the subcarrier signal in a color television camera that has a video signal synthesis circuit that synthesizes a video signal using a reference signal whose frequency is four times that of the subcarrier signal. do
Using two oscillation circuits with PLL circuit configuration, one
By synchronizing the output of the 1/4 frequency division of the oscillation output with the external subcarrier in the PLL circuit, and synchronizing the burst signal of the video signal with the 1/4 frequency division output in one PLL circuit, A video signal having a color subcarrier based on the subcarrier is obtained.

C. Prior Art Conventionally, in a video signal synthesis circuit of a color television camera, a color subcarrier signal is synthesized using a subcarrier signal _SC and a signal having a phase different from this by 90 degrees.

As a first means of obtaining a signal having a phase difference of 90° with respect to the subcarrier signal _SC , the subcarrier signal
A method is used in which _{the SC} is input to a phase shift circuit consisting of an inductance and a capacitor to obtain outputs with a 90° phase difference.

However, because the phase shift circuit must be constructed from discrete components such as capacitors and inductances, it is difficult to miniaturize the circuit and integrate it into ICs.
Another problem is that it requires consideration of the temperature characteristics of the phase shift circuit and adjustment work due to variations in inductance and the like.

On the other hand, a second method is used, which uses the configuration of flip-flops F1, F2 and F3 as shown in FIG. 3, for example. In this case, first, a reference signal 4 _SC having a frequency four times that of the subcarrier signal _SC is created.

After the reference signal 4 _SC (FIG. 4A) is frequency-divided by 1/2 in flip-flop F1 (FIG. 4B), it is further frequency-divided by 1/2 in flip-flop F2.

On the other hand, the inverted output ₁ (FIG. 4D) of flip-flop F1 is frequency-divided by 1/2 in flip-flop F3.

From the outputs Q ₂ (FIG. 4C) and Q ₃ (FIG. 4E) of flip-flops F2 and F3, a subcarrier signal _SC and a signal having a phase difference of 90° from this are obtained.

According to the configuration shown in Fig. 4, it is possible to implement the IC relatively easily, and to adjust the phase difference of a signal with a 90° phase difference with respect to the subcarrier signal _SC with high precision and stability, without any adjustment work. Obtainable.

Accordingly, in recent camera television cameras, the second means is adopted, and in order to reduce the size, an encoder is used in which the entire video signal synthesis circuit, including the circuit section concerned, is integrated into an IC.

D Problems to be solved by the invention However, when applying external synchronization to a color television camera using such an encoder, the _subcarrier is
Since _{the SC} is created, it is difficult to directly compare the subcarrier EXT-SC of the external synchronization signal and the subcarrier _SC in the encoder to achieve synchronization.

That is, it is the reference signal 4 _SC that can be directly compared with the external subcarrier EXT-SC, and therefore, as shown in FIG. 5, the reference signal 4 _SC A and the external subcarrier EXT-SCB are Comparing and synchronizing, even if the frequency of the subcarrier _SC inside the encoder is synchronized with the external subcarrier EXT-SC,
0°C, 90°D, 180°E and
It will have a phase relationship of either 270°F.

Therefore, the phase of the color subcarrier signal of the video signal synthesized based on the subcarrier _SC is also 0°, 90°, 180°, and 270° with respect to the external subcarrier EXT−SC.
Therefore, it is difficult to reliably synchronize the phase of the color subcarrier with the externally synchronized subcarrier EXT-SC.

The present invention was developed in consideration of the above points, and it is possible to reliably synchronize with the external subcarrier EXT-SC in a color television camera that synthesizes video signals using the reference signal _4SC . It attempts to provide an external synchronization circuit.

E. Means for solving the problem In order to solve the problem, in the present invention, the color subcarrier signal is synthesized based on the video signal synthesis reference signal 4 _SC having a frequency four times that of the subcarrier signal. Using the video signal synthesis circuit 2 that outputs the signal VBS1, the external synchronization circuit 1 that outputs the video signal VBS1 based on the subcarrier signal EXT-SC supplied from the outside, uses the video signal synthesis circuit 2 that outputs the signal VBS1 to output the video signal VBS1. a first oscillation circuit 1 that generates a reference signal 4 _SC1 with a frequency four times that of the subcarrier signal;
0, a frequency dividing circuit 11 that divides the frequency of the reference signal 4 _SC1 and outputs the frequency-divided signal SC1, and compares the phase of the frequency-divided signal SC1 and the subcarrier signal EXT-SC supplied from the outside. The first phase comparison circuit 12 outputs a phase comparison result S1 of the reference signal 4, and adjusts the phase of the reference signal _4SC1 so that the phase of the frequency-divided signal SC1 is locked to the subcarrier signal EXT-SC supplied from the outside. a first phase-locked loop circuit 3 for controlling;
A second oscillation circuit 15 generates a video signal synthesis reference signal 4 _SC2 based on the second phase comparison result S2 and outputs it to the video signal synthesis circuit 2, and a burst signal SB1 and a frequency-divided signal SC1 of the video signal VBS1. and a second phase comparison circuit 18 that compares the phase with the frequency-divided signal and outputs a second phase comparison result S2.
A second phase-locked loop circuit 4 controls the phase of the video signal synthesis reference signal 4 _SC2 so that the phase of the burst signal SB1 is locked to SC1, and the subcarrier signal EXT-
Outputs video signal VBS1 synchronized with SC.

F Effect Synchronizes the first signal with the external subcarrier signal by comparing the phases of the first signal obtained by dividing the first reference signal with a frequency four times that of the subcarrier signal by 1/4 and the external subcarrier signal. Let them do it.

A second reference signal having a frequency four times that of the subcarrier signal is input to the video signal synthesis circuit, and the phase of the burst signal obtained based on this is compared with the first signal, thereby converting the burst signal into the first signal. Make sure to synchronize with.

Thus, the subcarrier components within the video signal synthesis circuit become synchronized to the external subcarriers.

G Example Embodiments of the present invention will be described in detail below with reference to the drawings.

Figure 1 shows an embodiment in which the present invention is applied to a PAL color television camera.
The output signal _4SC and the horizontal synchronization signal HD1 are supplied to the encoder 2, and the color difference signals RY and B- are synthesized in a signal processing circuit (not shown).
Y and the luminance signal Y are converted by the encoder 2 and output as a video signal VBS1.

The external synchronization circuit 1 includes a VCO 10, a 1/4 frequency divider circuit 11, a phase comparator circuit 12, and a low-pass filter that synchronizes the subcarrier signal SC1 with the subcarrier signal EXT-SC input in the form of a burst of an external synchronization signal. A video signal is transmitted to a PLL (phase locked loop) circuit 3 consisting of 13 and a subcarrier signal SC1.
VCO1 synchronizes the burst signal SB1 of VBS1
5, selection circuit 16, encoder 2, gate circuit 1
7. A PLL circuit 4 consisting of a phase comparator circuit 18 and a low-pass filter 19 configured as an amplifier circuit, and a VCO 20 and 1/2 frequency division for synchronizing the horizontal synchronizing signal HD1 with the horizontal synchronizing signal EXT-HD of the external synchronizing signal. The PLL circuit 5 includes a circuit 21, a frequency divider circuit 22, a phase comparator circuit 23, and a low-pass filter 24.

The 1/4 frequency divider circuit 11 and the frequency divider circuit 22 are provided in an IC-configured synchronization signal synthesis circuit that synthesizes other PAL synchronization signals such as clamp pulses. Moreover, the phase comparator circuits 12 and 23 are similarly ICs.
31.

When external synchronization is applied to the PLL circuit 3, the phase comparator circuit 12 uses an external subcarrier EXT.
-SC is input together with the output SC1 of the 1/4 frequency divider circuit 11, and its phase comparison output S1 is outputted to the VCO 10 via the low-pass filter 13.

On the other hand, when external synchronization is not applied, the external subcarrier EXT-SC is not input and the 1/4 frequency divider 11
The phase comparison output S1 based on the output SC of VCO10
is input.

VCO10 outputs PAL based on phase comparison signal S1.
Reference signal with a frequency four times that of the subcarrier signal of the system
4 _SC1 (≒17 [MHz]) is oscillated and output to the 1/4 frequency divider circuit 11.

The 1/4 frequency divider circuit 11 divides the reference signal 4 _SC1 by 1/4 to create a subcarrier signal SC1 (≒4.43 [MHz]),
It is output to the phase comparator circuit 12.

Thus, the output signal SC1 of the 1/4 frequency divider circuit 11 of the PLL circuit 3 is
This is the free-running frequency of the circuit 3 itself, and when external synchronization is applied, the phase and frequency are synchronized with the externally synchronized subcarrier signal EXT-SC.

On the other hand, in the PLL circuit 4, the phase comparison circuit 18
The subcarrier signal SC1 output from the 1/4 frequency divider circuit 11 is input to the subcarrier signal SC1. On the other hand, the output of the encoder 2 is input to the gate circuit 17.
extracts only the burst signal SB1 of the video signal VBS1 and outputs it to the phase comparison circuit 18. The phase comparison circuit 18 compares the phases of the signal SC1 and the burst signal SB1, and outputs the phase comparison output S2 to the VCO 15 via a low-pass filter 19 having an amplifier circuit configuration.

The VCO 15 oscillates a second reference signal 4 _SC2 (≈17 [MHz]) based on the phase comparison output S2 and outputs it to the selection circuit 16.

When applying external synchronization, the selection circuit 16 is switched to the contact 16a, and the reference signal of the VCO 15 is switched to the contact 16a.
4 Input _SC2 to encoder 2.

On the other hand, if external synchronization is not applied, the selection circuit 16
is switched to the contact 16b, and inputs the reference signal 4 _SC1 of the VCO 10 to the encoder 2.

Thus, when applying external synchronization, the PLL circuit 4 configures a PLL loop consisting of the VCO 15, the selection circuit 16, the encoder 2, the gate circuit 17, the phase comparison circuit 18, and the low-pass filter 19, and synchronizes the external subcarrier EXT-SC. A video signal VBS1 having a burst signal SB1 whose phase and frequency are synchronized with the subcarrier signal SC1 of the 1/4 frequency divider circuit 11 is output.

On the other hand, when external synchronization is not applied, the PLL loop is not configured and the encoder 2 outputs a burst signal obtained by dividing the free-running frequency reference signal 4 _SC of the PLL circuit 3.
A video signal VBS1 having SB1 is output.

When applying external synchronization to PLL circuit 5,
The phase comparator circuit 23 receives an external horizontal synchronizing signal.
EXT-HD is the horizontal synchronization signal HD of the frequency divider circuit 22
1 and its phase comparison output S3 is output to the VCO 20 via the low-pass filter 24.

On the other hand, if external synchronization is not applied, the frequency divider circuit 20
Only the horizontal synchronizing signal HD1 is input, and the phase comparison output S3 based on this is input to the VCO 20.

The VCO 20 oscillates a third reference signal 2 _CL1 (≈28 [MHz]) based on the phase comparison signal S3 and outputs it to the 1/2 frequency divider circuit 21.

The 1/2 frequency divider circuit 21 divides the frequency of the reference signal 2 _CL1 by 2 to create a signal CL1, and outputs the signal _CL1 to the synchronization signal synthesis circuit.

The synchronization signal synthesis circuit synthesizes a vertical synchronization signal, etc. based on the signal _CL1 NI, and also divides the frequency of the signal _CL1 in a frequency dividing circuit 22 to generate a horizontal synchronization signal HD1.
Create.

The horizontal synchronization signal HD1 is sent to the phase comparison circuit 23 and also to the encoder 2.

Thus, in the PLL circuit 5, when external synchronization is applied, the output horizontal synchronization signal HD1 is synchronized in frequency and phase with the external horizontal synchronization signal EXT-HD, and the video signal VBS1 of the encoder 2 is also synchronized with the external horizontal synchronization signal EXT-HD. It will be synchronized with the synchronization signal EXT-HD.

In addition, if external synchronization is not applied, the horizontal synchronization signal
HD1 becomes the free running frequency of the PLL circuit 5, and a video signal VBS1 synchronized with this is obtained.

In the above configuration, when applying external synchronization, the selection circuit 16 is switched to the contact 16a, and the phase comparison circuits 12 and 23 are supplied with the external subcarrier signal EXT-SC and the horizontal synchronization signal EXT-SC.
HD is input.

The subcarrier signal SC1 output from the 1/4 frequency divider circuit 11 of the PLL circuit 3 is an external subcarrier signal EXT−SC.
synchronized to the phase and frequency of

In the PLL circuit 4, the burst signal SB1 of the video signal VBS1 is synchronized with the phase and frequency of the subcarrier SC1.

Thus, the burst signal SB of the video signal VBS1
1 will be synchronized with the phase and frequency of the subcarrier signal EXT-SC of the external synchronization signal, and thus the phase and frequency of the subcarrier in encoder 2 will be synchronized with and based on the external subcarrier signal EXT-SC. The color subcarriers are then combined.

On the other hand, in the PLL circuit 5, the horizontal synchronizing signal HD1 of the frequency dividing circuit 22 is used as the external horizontal synchronizing signal EXT-
Synchronized to HD phase and frequency. encoder 2
, video signal VBS1 is synthesized based on horizontal synchronization signal HD1.

In this way, the horizontal synchronizing signal of the video signal VBS1 is synchronized with the horizontal synchronizing signal EXT-HD of the external synchronizing signal.

Next, if external synchronization is not applied, select circuit 16
is switched to contact 16B, and the external horizontal synchronizing signal EXT-HD and subcarrier signal EXT-SC are no longer input.

Therefore, the PLL circuit 3 oscillates at a free-running frequency, and the output reference signal 4 _SC1 is input to the encoder 2 via the selection circuit 16.

On the other hand, the PLL circuit 5 similarly oscillates at a free-running frequency, and the output horizontal synchronization signal HD1 is input to the encoder 2.

Therefore, the video signal VBS1 is synthesized based on the subcarrier signal SC1 and the synchronization signal HD1, which are determined by the free-running frequencies of the PLL circuits 3 and 5, and is output.

According to the above configuration, by using the encoder 2 that synthesizes the video signal VBS1 using the reference signal 4 _SC2 , synchronization can be reliably achieved with the subcarrier signal _SC as an external synchronization signal, and internal synchronization and external An external synchronization circuit whose synchronization can be switched can be obtained.

FIG. 2, in which parts corresponding to those in FIG. 1 are designated by the same reference numerals, shows a case where the present invention is applied to an NTSC color television camera.

The external synchronization circuit 6 synchronizes the horizontal synchronization frequency HD2 and the subcarrier signal SC3 with respect to the subcarrier signal EXT-SC of the external synchronization signal input in burst form. Consists of VOC 44, 1/2 frequency divider circuit 21, frequency divider circuit 42 of NTSC synchronization signal synthesis circuit 41, phase comparator circuit 12, and low-pass filter 13
Synchronize burst signal SB2 of video signal VBS2 with PLL circuit 7 and subcarrier signal SC3
The PLL circuit 8 includes a VCO 40, a selection circuit 16, an encoder 2, a gate circuit 17, a phase comparison circuit 18, and a low-pass filter 19.

In the PLL circuit 7, the comparison output S4 of the phase comparison circuit 12 is passed through the low-pass filter 13.
Output to VCO44.

VCO44 is NTSC based on comparison output S4.
The first subcarrier signal SC3 has a frequency eight times that of the subcarrier signal SC3 of the system.
Oscillates the reference signal 2 _CL2 (=8 _SC3 ) and converts it to 1/
It is output to the divide-by-2 circuit 21.

The output signal _CL2 (=4 _SC3 ) of the 1/2 frequency divider circuit is
The signal is input to an NTSC synchronization signal synthesis circuit 41.

The frequency dividing circuit 42 of the synchronization signal synthesis circuit 41 divides the signal
The subcarrier signal SC3 and the horizontal synchronization signal HD2 are synthesized by frequency-dividing _CL2 by 1/4 and 1/910, respectively.

The subcarrier signal SC3 is output to the phase comparison circuit 12, and the horizontal synchronization signal HD2 is output to the encoder 2.

Therefore, when no external synchronization is applied, the PLL circuit 7 adjusts the horizontal synchronization frequency HD2 based on the free-running frequency.
and subcarrier SC3, and when external synchronization is applied, subcarrier signal SC3 and horizontal synchronization signal HD2 are output at timing synchronized with external subcarrier signal EXT-SC input in burst form.

On the other hand, in the PLL circuit 8, the phase comparison circuit 18
The comparison output S5 of is passed through the low-pass filter 19.
Output to VCO40.

The VCO 40 oscillates a second reference signal _CL3 (=4 _SC3 ) having a frequency four times that of the NTSC subcarrier signal SC3 based on the comparison output S5, and outputs it to the contact 16a of the selection circuit 16.

The output signal _CL2 of the 1/2 frequency divider circuit 21 is input to the contact 16b of the selection circuit 16.

Thus, when external synchronization is applied, the PLL circuit 8 uses the VCO 40, selection circuit 16, encoder 2,
A PLL loop consisting of a gate circuit 17, a phase comparator circuit 18, and a low-pass filter 19 is configured,
Output signal SC of the synchronization signal synthesis circuit 41 whose phase and frequency are synchronized with the external subcarrier signal EXT-SC
Burst signal SB whose phase and frequency are synchronized to 3
output a video signal VBS2 having a value of 2.

On the other hand, when external synchronization is not applied, the PLL loop is not configured and the encoder 2 outputs the video signal VBS2 having the burst signal SB2 obtained by dividing the free-running frequency reference signal _CL2 (=4 _SC3 ) of the PLL circuit 7. do.

In the above configuration, when applying external synchronization, the selection circuit 16 is switched to the contact 16a, and the external synchronization subcarrier signal EXT-SC is input to the phase comparison circuit 12.

The subcarrier signal SC3 output from the synchronization signal synthesis circuit 41 of the PLL circuit 7 is an external subcarrier signal.
Output in synchronization with the phase and frequency of EXT-SC.

In addition, the horizontal synchronization signal HD2 is the subcarrier signal EXT
-SC is outputted in synchronization with the input timing of subcarrier signal EXT-SC and delayed by a predetermined time from the input timing of subcarrier signal EXT-SC.

On the other hand, in the PLL circuit 8, the video signal VBS
The second burst signal SB2 is synchronized with the phase and frequency of the subcarrier signal SC3.

Thus, the video signal VBS2 output from the encoder 2 has the phase of the burst signal SB2,
The frequency, output timing, and horizontal synchronization signal timing are output based on the external subcarrier signal EXT-SC.

According to the above configuration, the same effects as in the first embodiment can be obtained even in an NTSC color television camera.

In the above embodiment, the present invention was applied to a color television camera, but the present invention can also be widely applied to external synchronization circuits of other video equipment.

H. Effects of the invention As described above, according to the invention, synchronization can be reliably achieved with an external subcarrier by using the encoder 2 that synthesizes a video signal using a reference signal with a frequency four times that of the subcarrier. It is possible to obtain an external synchronization circuit that can be used.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of the PAL system of the external synchronization circuit of the present invention, and Figure 2 is a block diagram of the NTSC system.
A block diagram showing an example of the method, FIG. 3 is a block diagram of a circuit that creates a subcarrier signal and a signal with a 90° phase difference, FIG. 4 is a signal waveform diagram for explaining its operation, and FIG. FIG. 3 is a signal waveform diagram for explaining synchronization of a subcarrier signal and a reference signal having a frequency four times that of the subcarrier signal. 1, 6...External synchronization circuit, 2...Encoder,
3, 4, 5, 7, 8...PLL circuit, 10, 15,
20, 40, 44...VCO, 12, 18, 23
... Phase comparison circuit, 11, 21, 22 ... Frequency division circuit, 16 ... Selection circuit, 41 ... Synchronization signal synthesis circuit.

Claims (1)

[Claims for Utility Model Registration] A video signal synthesis circuit that synthesizes color subcarrier signals based on a video signal synthesis reference signal having a frequency four times that of the subcarrier signal and outputs a video signal, which is supplied from an external source. a first oscillation circuit that generates a reference signal having a frequency four times that of the subcarrier signal based on the first phase comparison result; a frequency dividing circuit that divides the frequency of the reference signal and outputs a frequency-divided signal; and a frequency dividing circuit that divides the frequency of the reference signal and outputs the frequency-divided signal;
a first phase comparison circuit that outputs a phase comparison result of the reference signal, and a first phase comparison circuit that controls the phase of the reference signal so that the phase of the frequency-divided signal is locked to the subcarrier signal supplied from the outside. a phase-locked loop circuit; a second oscillation circuit that generates the video signal synthesis reference signal based on the second phase comparison result and outputs it to the video signal synthesis circuit; a second phase comparison circuit that compares the phase with the frequency signal and outputs the second phase comparison result; and a second phase-locked loop circuit that controls the phase of the reference signal, and outputs the video signal synchronized with the externally supplied subcarrier signal.