JPS5868387A - Jitter correcting circuit - Google Patents

Abstract

PURPOSE:To solve jitters without increasing the number of bits while maintaining high transfer efficiency, by setting the center frequency of a transfer clock in a jitter correcting circuit which uses a variable delay element according to the amount of generated jitters. CONSTITUTION:A horizontal synchronizing signal and a burst signal are separated from a jitter-corrected output obtained by controlling a variable delay element by a transfer clock, and then compared with reference signals to obtain a jitter detection output, which is supplied as a control input to a variable oscillating circuit. In this jitter correcting circuit, a jitter detection output outputted from an adding circuit 11 is detected by a detecting circuit 12. The obtained detected level is applied to a variable oscillating circuit 3 as a DC bias for prescribing the center frequency of the transfer clock, so the best jitter correction of any reproduced video signal is performed regardless of the level of the jitters without increasing the number of bits of a variable delay line.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a jitter correction circuit using variable delay elements.

Analog delay elements are capable of delaying the transmission signal depending on the frequency change of the transmission station, and have recently become available at low cost. Therefore, jitter correction circuits for video tape recorders and video disk players using these variable delay elements are becoming commonly used.

Generally, the transfer lock frequency of a variable delay element needs to be selected to be at least three times the highest transmission frequency in consideration of its transfer efficiency; the higher the transfer lock frequency, the higher the transfer efficiency can be obtained. However, when changing the delay amount of the variable delay element in order to eliminate the time axis fluctuation (jitter) component that occurs, if the transfer lock frequency is high, the amount of frequency folding required to eliminate the jitter must also be increased. The number of bits of the delay element must also be increased.

Therefore, the present invention makes it possible to eliminate jitter while maintaining high transfer efficiency without increasing the number of bits of the variable delay element by setting the center frequency of the transfer lock according to the amount of jitter that occurs. The purpose of this paper is to propose a new and effective jitter correction circuit.

Hereinafter, the present invention will be explained according to an embodiment to illustrate the invention. In this embodiment, the present invention is applied to a video disc player, and the figure shows that after an FM demodulation circuit (1) demodulates an FM-modulated playback signal together with a color signal, the jitter component of the demodulated output is eliminated. A circuit block diagram of a jitter correction circuit is shown. The variable delay element (2) composed of COD is
The input demodulated output is transferred by the transfer lock generated by the variable oscillation circuit (3), and the number of bits is 685.
b 1 t. A part of the jitter-corrected output of the variable delay element (2), which has undergone jitter correction, is input to a horizontal synchronization separation circuit (4) and a burst gate (5), which convert the horizontal synchronization signal and burst signal into the first and second burst signals, respectively. The second phase comparator circuit (6) (inputs to the comparison input terminal of 7i). Also, the reference signal generation circuit (8) divides the crystal oscillation output into the horizontal synchronization period and the color subcarrier period, respectively. Said first and second phase comparison circuits (6) (7)
input to the reference input terminal. Therefore, the first phase comparison circuit (6) detects a large phase variation, and the second phase comparison circuit detects a small variation.

Both comparison outputs are passed through the 1st and 20th pass filters (9
1Q (respectively input to I, high frequency phase fluctuations are eliminated, and input to adder circuit αυ. This adder circuit a1)
The derived jitter detection output is output from the variable oscillation circuit (3).
) is input as a control signal, and the transfer lock whose oscillation frequency is changed according to the jitter is input to the variable delay element (2). Although this circuit configuration makes it possible to correct jitter to a certain extent, the feature of this embodiment is that it further detects the level of jitter and adds a DC bias to the variable oscillation circuit (3). In the embodiment, the detection circuit a'! has a cutoff frequency of 30 Hz or less. The jitter detection output is input to J, and when the jitter level becomes large, a DC bias is applied to the usable oscillation circuit (2) to lower the center frequency of the transfer lock below 14MHz. The center frequency of the transfer lock is lowered to about 9 MHz depending on the DC bias level. Therefore, it must be 1 near the upper limit (15 MH) of the transfer lock frequency of the CCD composed of MO8, but if a jitter of ±5 seconds occurs in the square of this example, @DC bias is applied. When setting the transfer lock center frequency to 9M), set the transfer lock frequency domain to 8.45M.
The frequency may be Hz to 9.65 MHz. In this embodiment, in order to make the transfer lock center frequency follow fluctuations in the jitter level, the phase in the first phase comparator circuit changes by approximately 25 tones 1·C as the transfer lock frequency center frequency changes.
Although the degree changes, this change is so gradual that it cannot be detected as jitter, and at least it is not derived from the addition circuit and does not interfere with sick correction.

As described above, according to the present invention, the jitter level is detected by detecting the jitter detection output, and this detected level is applied as a DC bias, so that the reproduced video signal with small jitter can be transferred with high transfer efficiency. For reproduced video signals with large jitter, it is possible to completely correct the jitter, although it sacrifices some transfer efficiency, and it is possible to completely correct the jitter without increasing the number of bits of the variable delay line. This makes it possible to perform the best jitter correction even for reproduced video signals, and the effect is great.

[Brief explanation of the drawing]

The figure is a circuit block diagram for implementing the present invention. Explanation of main figure numbers α...Detection circuit, (2)...Variable delay element, (3
)...Variable oscillation circuit

Claims (1)

[Claims] (11) The variable oscillation circuit derives a transfer lock to control the variable delay element which inputs the reproduced video signal, and separates the horizontal synchronization signal and burst signal from the derived jitter correction output. A jitter correction circuit compares the jitter detection output with a reference signal and uses the obtained jitter detection output as a control input of the variable oscillation circuit, the jitter correction circuit detects the jitter detection output and applies the transfer lock to the variable oscillation circuit. A jitter correction circuit comprising a detection circuit that applies a DC bias that defines a center frequency of the jitter correction circuit.