JPS599484Y2 - Signal jitter correction circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to a signal jitter correction circuit, which uses semiconductor element delay circuits (analog shift registers) such as BBDs (bucket top-loaded devices) and CCDs (charge-coupled devices) to create a closed-loop circuit. It is an object of the present invention to provide a signal jitter correction circuit that does not include any part having the following characteristics.

Generally, in a recording/reproducing apparatus for audio signals or video signals, the time axis of the signal display function fluctuates due to changes in the tape running speed, causing the signal to become FM or PM, resulting in jitter.

In order to correct this, conventionally, the FM or PM signal is passed through an FM or PM modulator to be modulated by the same amount.

A specific device for this purpose is a variable delay line.
The amount of delay is changed in a direction that cancels out the jitter.

However, such a device has drawbacks in that it is difficult to set a large amount of delay, it is difficult to widen the passband in terms of both amplitude and phase, and the circuit is complicated.

Therefore, instead of the variable delay line mentioned above, a recently developed BB
The present applicant previously proposed a signal jitter correction circuit that can eliminate the above-mentioned drawbacks by using a semiconductor element delay circuit such as a D (bucket triplicate device) or a CCD (charge coupled device), dated March 18, 1971. First patent application
We proposed a circuit as shown in the figure.

In the figure, 1 is a video signal input element, and the video signal inputted from this element is sent to a horizontal synchronization separation circuit 2 and a semiconductor element delay circuit 3.
are supplied respectively.

The horizontal synchronization signal taken out from the horizontal synchronization separation circuit 2 is applied to a phase comparator 4, where it is compared with the phase of an output oscillation signal of substantially the same frequency as the horizontal synchronization signal of a voltage controlled oscillator (VCO) 6, which will be described later. be done.

As a result, the error voltage obtained by comparing the phases of the two signals in the phase comparator 4 is applied to the voltage controlled oscillator 7 as a control voltage, and is also applied to the voltage controlled oscillator 6 as a control voltage via the reduction filter 5.

Here, the loop consisting of the phase comparator 4, reduction filter 5, and voltage controlled oscillator 6 constitutes a so-called phase-locked loop (PLL).

A signal taken out from the voltage controlled oscillator 7 is applied to the semiconductor element delay circuit 3 as, for example, two-phase clock pulses φ1 and φ2 having mutually opposite phases.

Now, the number of shift stages of the semiconductor element delay circuit 3 is N stages,
The clock period of the clock pulses φ1 and φ2 is Tc.
In general, the output signal of the delay circuit 3 is a signal obtained by delaying the input signal by NTc seconds.

Therefore, by changing the frequency of the output clock pulses φ1 and φ2 of the voltage controlled oscillator 7, the delay time of the input video signal is varied in the semiconductor element delay circuit 3 so as to correct jitter, and the input video signal is treated as a jitter-free or improved signal. It is guided to the output terminal 8.

As mentioned above, the signal jitter correction circuit shown in FIG.
The amount of delay of the semiconductor element delay circuit is variably controlled by the phase error voltage obtained from the PLL.

Therefore, it will not operate unless the PLL is locked.

For this reason, the PLL is designed to have a relatively wide lock-in bandwidth (capture range).

Therefore, in order to detect the phase error in the low frequency range, the PL
If the cutoff frequency of L is lowered, the lock-in band width will also be narrowed.

Therefore, it is necessary to find a balance between the lock-in bandwidth of the PLL and the cut-off frequency of the PLL, and there is also the problem that the circuitry, adjustment, etc. become somewhat complicated.

The present invention solves the above problems, and is shown in Figures 2 to 4.
One embodiment will be explained with reference to the drawings.

FIG. 2 shows a block diagram of one embodiment of the signal jitter correction circuit according to the present invention.

In the figure, the same signals are attached to the same parts as in FIG. 1, and the explanation thereof will be omitted.

In the same figure, the horizontal synchronization signal, which is a periodic signal extracted from the horizontal synchronization separation circuit 2, is passed through a frequency discriminator (freque
frequency discriminator) 9 and is phase-compared with a horizontal synchronizing signal delayed by one period. Here, the frequency change is converted into a voltage change (f-V conversion), and the speed change output voltage of the frequency discriminator 9 is converted into a voltage change. It is applied as a phase error control voltage to a voltage controlled oscillator (VCO) 7 through an integrating circuit 10 that performs integration.

As a result, the jitter included in the input signal of the semiconductor element delay circuit 3 is corrected here and then guided to the output terminal 8.

Note that the frequency discriminator (frequency discriminator)
riminator) 9 detects a frequency change, that is, a differential, by comparing the phase with a horizontal synchronizing signal delayed by one period.The circuit structure of the phase comparator that performs the phase comparison or , which is similar to an ordinary phase comparator.

- That is, the frequency discriminator 9 may have a commonly used structure, for example, the output of a sampling pulse discriminator to which a horizontal synchronizing signal delayed by one period is input, and the output of a sampling pulse discriminator to which the next horizontal synchronizing signal is input. A configuration may be used in which the output of the slope waveform shaper is input to a phase comparator, and the output of the phase comparator is the frequency error voltage.

The above-mentioned delay circuit for delaying by one period is constructed by using two stages of monostable multivibrators, for example, and performs compensation for stabilizing the pulse width to suppress delay time variations as much as possible.

Therefore, this frequency discriminator 9 is a differential system with respect to phase, and therefore it is difficult to detect phase error discrimination at low frequencies.

However, the frequency discriminator 9 has the advantage of having a simple circuit and adjustment, and stable operation.

FIG. 3 shows an example of a block diagram in which each element in FIG. 2 is expressed as a transfer function.

In the figure, Kd is the gain of the frequency discriminator 9, KV is the gain of the voltage controlled oscillator 7, N is the number of shift stages of the semiconductor element delay circuit 3, TH is the period of the horizontal synchronizing signal, and the integrating circuit 10
The time constants of are shown respectively.

From FIG. 3, the transfer function Y(S) regarding the phase of the system is expressed by the following equation, where the input signal and the output signal are θ1(S) and θ2(S), respectively.

becomes.

However, it is.

Therefore, if we set s=jω in the above equation (2), then y=
The frequency characteristics of 20 10g1o 1y (jω) are as shown in FIG.

In the figure, the fact that the vertical axis is OdB means that there is only one input and one output, and in this case, jitter is not corrected at all.

On the other hand, the negative sign of the vertical axis indicates that the larger the absolute value, the better the jitter is corrected.

Therefore, from the figure, when the jitter angular frequency is smaller than ωO, the jitter is not corrected at all, and when the jitter angular frequency is from ωO to ω1, the jitter of the output signal of the semiconductor element delay circuit is -
It decreases with a slope of 6 dB/Oct.

At the angular frequency ωl or higher, it rises at a slope of 6 dB/Oct and finally reaches O dB.

As described above, the signal jitter correction circuit according to the present invention includes a periodic signal separation circuit that extracts a periodic signal from an input signal, and a frequency discrimination circuit that converts the periodic signal extracted from the periodic signal separation circuit from frequency to voltage. d
an integrator circuit that integrates the speed error output voltage of the frequency discrimination circuit; a voltage controlled oscillator (VCO) that is supplied with the output of the integrator circuit as a phase error control voltage; , a circuit structure including a semiconductor element delay circuit which is supplied with the output clock pulse signal of the voltage controlled oscillator as a control signal and outputs a signal corrected for a certain amount of jitter contained in the input signal, and does not include a part having a closed loop. Therefore, when correcting signal jitter using a semiconductor element delay circuit, the semiconductor element delay circuit is essentially a phase modulator,
If the signal that controls this does not have a phase error in the input signal, the dimensions of the control input and the controlled object will not match.Therefore, if the output of the conversion circuit that converts the periodic signal of the input signal into frequency voltage is used as the control signal, the frequency error will occur. Therefore, the periodic signal of this input signal is integrated and used as a phase error voltage of the input signal to control the frequency of the clock pulse that varies the delay amount of the semiconductor element delay circuit. Since it does not have a closed loop, there is no need to consider loop lock-in, and it has features such as being able to effectively and accurately remove jitter contained in the input signal with an extremely inexpensive structure. It is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a signal jitter correction circuit previously proposed by the applicant, FIG. 2 is a block diagram of an embodiment of the signal jitter correction circuit of the present invention, and FIG. 2
FIG. 4 is a signal system diagram of an example of the input signal phase shown in the figure, and FIG. 4 is a frequency characteristic curve diagram of the transfer function of the system in FIG. 1...Input terminal, 2...Horizontal synchronization separation circuit, 3...Semiconductor element delay circuit, 4...
...Phase comparator, 5...Low pass filter, 6,7
...Voltage controlled oscillator, 8...Output terminal, 9...Frequency discriminator, 10...Integrator circuit.

Claims (1)

[Scope of utility model registration request] a periodic signal separation circuit that extracts a periodic signal from an input signal;
a frequency discrimination circuit that converts the periodic signal extracted from the periodic signal separation circuit from frequency to voltage; an integration circuit that integrates the speed error output voltage of the frequency discrimination circuit; and an output of the integration circuit as a phase error control voltage. A voltage controlled oscillator is supplied, and a semiconductor element is supplied with the input signal and is supplied with an output clock pulse signal of the voltage controlled oscillator as a control signal, and outputs a signal corrected for jitter included in the input signal. A signal jitter correction circuit comprising a delay circuit and having a circuit structure that does not include a portion having a closed loop.