JP3087422B2 - Time axis correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correction apparatus for removing a time axis fluctuation component from a signal having a time axis fluctuation component such as a reproduced signal in a video tape recorder or the like, and in particular, to a charge coupled device. The present invention relates to a time axis correction device using a so-called clock-driven analog variable delay line in which a delay time is controlled in accordance with the frequency of a clock such as a charge coupled device (CCD).

[0002]

2. Description of the Related Art Conventionally, as a means for removing a time axis fluctuation component included in a reproduction signal from a recording medium in a video signal reproduction apparatus, a synchronization signal included in the reproduction signal is face-locked loop (hereinafter referred to as PLL). And enter
The phase comparison error voltage is used as a control signal to control the oscillation output of the voltage controlled oscillator, and the oscillation output is used as a clock to drive an analog variable delay line whose delay amount is controlled, and to reduce the delay amount in a direction to cancel the time axis fluctuation. There is a time axis correction method for changing. The outline is shown in FIG.

In FIG. 3, a video signal input from a video signal input terminal 1 is a horizontal synchronizing signal separating circuit 4 and a clock-driven analog variable delay line. In this example, the video signal is applied to a charge-coupled device (hereinafter referred to as a CCD) 3. Supplied. The horizontal synchronizing signal separated by the horizontal synchronizing signal separating circuit 4 is applied to a phase comparator 5, and the phase of the horizontal synchronizing signal is compared with the oscillation output signal of a first voltage controlled oscillator 6 having an oscillation frequency substantially the same as the horizontal synchronization signal. You.

The error voltage phase-compared by the phase comparator 5 is applied as a control voltage to a second voltage-controlled oscillator 8 and controlled by the first voltage-controlled oscillator 6 via a phase correction circuit 7. Applied as a voltage. Here, the loop including the phase comparator 5, the phase correction circuit 7, and the first voltage controlled oscillator 6 constitutes a PLL. The oscillation signal of the second voltage controlled oscillator 8 is supplied as a clock of the CCD 3.

Therefore, in the CCD 3, the delay time of the video signal is changed so as to correct the time-axis fluctuation by the frequency change of the oscillation signal of the second voltage-controlled oscillator 8, and the image signal does not include the time-axis fluctuation. It is led to the output terminal 2 as an improved signal. As described above, the time axis correction circuit shown in FIG.
3 is variably controlled.

[0006]

As is well known, such a conventional device does not operate unless the PLL is locked. Further, when a video signal is input from a no-signal state, it takes time until the PLL is locked. Therefore, during the period from the no-signal state to the time when the video signal is input and the PLL is locked, not only the time axis correction does not operate, but also a time axis fluctuation unrelated to the time axis fluctuation of the video signal is given to adversely affect the reproduction screen. There is a drawback that it does.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a time axis correcting apparatus of the present invention detects a lockout of a PLL and changes the clock frequency of the CCD during the lockout period. Means for inhibiting the phase error voltage of the supplied PLL is provided to inhibit the time axis correction during the period when the PLL is not locked.

[0008]

According to the present invention, a phase error voltage obtained by the PLL after the PLL is locked in is supplied to the voltage controlled oscillator for controlling the clock frequency of the CCD by the above-mentioned configuration, so that the video signal is inputted from the no signal state. PL
It is possible to suppress the disorder of the playback screen that occurs until L is locked in.

[0009]

FIG. 1 is a block diagram showing an embodiment of a time axis correcting apparatus according to the present invention, and the same reference numerals are given to the same parts as those in the conventional configuration shown in FIG. The difference is that a lockout detecting means 10 for detecting lockout of a PLL loop comprising a phase comparator 5, a phase compensation circuit 7 and a first voltage controlled oscillator 6 is added, and the phase error voltage of the phase When the PLL is locked, the output of the lockout detection means 10 is supplied to the second voltage controlled oscillator 8 via the switch circuit 9 which is used as a control signal. The phase error voltage is supplied to the second voltage controlled oscillator 8, and the oscillation frequency of the second voltage controlled oscillator 8 is controlled.

That is, the delay amount of the CCD 3 is variably controlled by the phase error voltage of the PLL. Also,
When the PLL is not locked, the phase error voltage of the phase comparator 5 is not supplied to the second voltage controlled oscillator 8. In this case, the oscillation frequency of the second voltage controlled oscillator 8 is set so that the delay amount of the CCD 3 becomes a predetermined value.

The lock-out detection means 10 of the PLL outputs the horizontal synchronizing signal a and the gate signal b obtained by shaping a predetermined period of the oscillation signal period of the first voltage controlled oscillator 6 by the waveform shaping circuit 11 to the OR circuit 12. The output e is obtained by comparing a signal d obtained by inputting the output signal c and integrating the output signal c by the integrator 13 with the comparator 14 based on the output voltage of the voltage power supply 15.

The operation will be described with reference to FIG. 2. The phase relationship between the horizontal synchronizing signal a and the oscillation signal of the first voltage controlled oscillator 6 is synchronized when the PLL is locked.
When L is not locked, it is asynchronous. Accordingly, the output signal c of the OR circuit 12 is such that the horizontal synchronization signal a passes during the period A in which the PLL is not locked,
Is fixed to the high level during the period B in which the is locked.
In the period A, the level of the signal d obtained by integrating the output signal c by the integrator 13 is lower than in the period B due to the horizontal synchronization signal a passing therethrough. The output signal e can be obtained by comparing the level difference with the comparator 14. Here, the lockout of the PLL can be detected by controlling the switch circuit 9 to open at the low level of the output signal e and close at the high level.

[0013]

As described above, according to the structure of the present invention, P
Abnormal operation of the time axis correction circuit caused by the LL not being locked can be suppressed, and even when a video signal is input from a no-signal state, a stable reproduction signal can be obtained without adverse effects. It is extremely effective in practical use.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a time axis correction device according to an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of a main part of the time axis correction device according to one embodiment of the present invention.

FIG. 3 is a block diagram showing a main part of a conventional time axis correction device.

[Explanation of symbols]

 Reference Signs List 1 video signal input terminal 2 video signal output terminal 3 CCD 4 horizontal synchronization signal separation circuit 5 phase comparator 6 voltage controlled oscillator 7 phase correction circuit 8 voltage controlled oscillator 9 switch circuit 10 lockout detection means 11 waveform shaping circuit 12 OR circuit 13 Integrator 14 Comparator 15 Voltage power supply

Claims (1)

(57) [Claims] An analog variable delay line whose delay time is controlled in accordance with a frequency of a clock signal; a horizontal synchronization signal separation circuit for separating a horizontal synchronization signal in a video signal supplied to the analog delay line; A phase comparator for comparing the phase of the oscillation output signal of the first voltage controlled oscillator with the horizontal synchronizing signal separated by the horizontal synchronizing signal separating circuit; A phase correction circuit for supplying a voltage to the voltage controlled oscillator as a control voltage; a lockout detecting means for detecting a lockout of a PLL loop including the phase comparison circuit, the phase correction circuit and the first voltage controlled oscillator; A second voltage regulator in which an oscillation frequency is controlled by a phase comparison error voltage of the phase comparator via a switch circuit using an output of the detection means as a control signal; An output of the second voltage controlled oscillator is supplied as a clock of the analog variable delay line, and the output of the lockout detecting means when the lockout of the PLL loop is detected is supplied to the switch circuit. A time axis correction device, wherein a phase comparison error voltage of the phase comparator which is driven and supplied to the second voltage controlled oscillator is prohibited.