JPS6322775Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a drive circuit for a charge transfer device (CTD), which is a general term for solid-state electronic functional devices including a bucket brigade device (BBD) and a charge-coupled device (CCD).

Charge transfer devices move charges in a controlled manner through a semiconductor substrate by applying clock pulses in an appropriate sequence, and this basic mechanism can be used for imaging, data storage, signal processing, and other applications. It is generally known that a very wide range of electrical functions can be achieved, including logical operations.

However, this charge transfer element has a phenomenon in which the DC operating point inside the charge transfer element deviates from the initial setting due to changes in clock frequency, changes in ambient temperature, and the like. For this reason, when the clock frequency is changed repeatedly at, for example, 30 Hz, the DC component of the output signal fluctuates, and when viewed on, for example, a television monitor, this appears as a so-called flicker phenomenon in which the screen flickers.

Furthermore, although the charge transfer element has a voltage range (dynamic range) within which it can transmit, the voltage may deviate from the original voltage range due to the above-mentioned shift in the DC operating point. This causes fluctuations in transmission gain, frequency characteristics, differential gain (DG), etc., making it impossible to transmit faithful signals.

FIG. 1 shows an example in which a conventional charge transfer element drive circuit is applied to a video disc player that uses the above-mentioned charge transfer element as a variable delay line for time base correction. In FIG. 1, a reproduced signal picked up from a video disk 1 is amplified by a reproducing amplifier 2, demodulated by an FM demodulator 3, and taken out as a video signal with time axis fluctuations (jitter). This extracted video signal is given an appropriate delay time by the charge transfer device 4, and then the clock and unnecessary spectrum are removed by the low frequency filter 5, and a jitter-free video signal is output from the output terminal 6 to a monitor TV (not shown). ).

Note that the delay time of the charge transfer element 4 is set in a loop as shown by arrow a. That is, first, only the 3.58MHz color component is extracted from the output signal of the low frequency filter 5 by the bandpass filter 7, and then the burst extraction circuit 8 extracts only the 3.58MHz color component.
supply to. On the other hand, the synchronization separation circuit 9 separates a horizontal synchronization signal from the output signal of the low frequency converter 5, and based on this horizontal synchronization signal, the burst flag generator 10 generates a burst flag pulse, which is supplied to the burst extraction circuit 8. do. By applying this burst flag pulse, only the burst signal is extracted to the output side of the burst extraction circuit 8. Furthermore, this burst signal is supplied to the phase comparator circuit 11,
The phase is compared with the 3.58MHz reference signal from the reference signal input terminal 12. The phase error signal from the phase comparison circuit 11 is then supplied to a voltage controlled oscillator (hereinafter referred to as VCO) 13, and the VCO 13 controls the oscillation frequency, that is, the clock frequency, according to the phase error signal and drives the oscillation signal. The signal is supplied to the charge transfer device 4 via the charge transfer device 14, and the delay time of the charge transfer device 4 is set.

By setting the delay time of the charge transfer element 4 in this way, a jitter-free video signal synchronized with the reference signal from the input terminal 12 is taken out at the output side of the low frequency converter 5.

However, if the reproduced signal obtained at the output side of the FM demodulator 3 has jitter, the oscillation frequency of the VCO 13, that is, the clock signal, changes by the phase error corresponding to the jitter, and the output signal of the charge transfer element 4 changes. It is subject to direct current fluctuations at the same frequency component as jitter, and when viewed on a TV monitor, the screen will flicker.

Furthermore, the output signal of the charge transfer element 4 fluctuates in a direct current manner due to a temperature change, and faithful signal transmission may not be possible as described above.

Therefore, in the case of a conventional charge transfer device drive circuit,
It is not possible to eliminate the disadvantages peculiar to charge transfer devices, in which the DC operating point inside the charge transfer device deviates from the initial setting due to changes in clock frequency, changes in ambient temperature, etc., and the DC component of the output signal of the charge transfer device fluctuates. Furthermore, as mentioned above, when used in a video disc player or the like, there was a drawback that direct current fluctuations due to jitter could not be removed.

The present invention was devised in view of these points, and is a versatile charge transfer device that can stabilize the operation of the charge transfer device by reducing the DC component of the output signal of the charge transfer device due to changes in clock frequency and temperature. A drive circuit for a transfer element is provided.

Embodiments of the present invention will be described in detail below with reference to FIGS. 2 to 4, taking as an example the case where the invention is applied to a video disc player that uses a charge transfer element as a variable delay line for time axis correction as described above. do.

FIG. 2 shows a first embodiment of the present invention. In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted. In this embodiment, color subcarriers (3.58MHz, 4.43MHz) are applied to the output side of the charge transfer element 4 from the output signal of the charge transfer element 4.
etc.) A low-frequency wave generator 21 is provided to cut off the above frequencies, and the output signal of the low-frequency wave generator 6, for example, the DC voltage at the synchronization tip part, is sampled and held using the horizontal synchronization signal separated by the synchronization separation circuit 9. A sample hold circuit 22 is provided. Further, after the sample and hold circuit 22, there is a low frequency filter 23 which has a cutoff frequency sufficiently lower than the sampling frequency and acts as a loop filter, and a reference signal having approximately the same potential as the initially set DC operating point of the charge transfer element 4. A reference signal generator such as a variable resistor 24 that generates the FM demodulator 3 and a comparison/amplification circuit such as a differential amplifier 25 that compares and amplifies the output signal of the low frequency amplifier 23 and the reference signal are provided. The differential amplifier 2 is arranged between the charge transfer elements 4 and
An adder 26 is provided for superimposing the output signal of FM demodulator 5 on the reproduced video signal obtained at the output side of the FM demodulator 3.
The other configurations are the same as in FIG. 1.

When an output signal containing a DC fluctuation component appears on the output side of the charge transfer element 4, this output signal is supplied to a sample and hold circuit 22 after removing frequency components higher than the color subcarrier such as residual clocks in a low frequency filter 21. Here, the DC voltage at the synchronization tip is held by the horizontal synchronization signal. This DC voltage is then supplied to the differential amplifier 25 through the low frequency amplifier 23, where it is compared with a reference voltage.
The error obtained by the differential amplifier 25 is amplified and supplied to the adder 6, superimposed on the reproduced video signal from the FM demodulator 3, and supplied to the charge transfer element 4.

Since the charge transfer element 4 normally transmits the input DC component with a gain of approximately 1, the output voltage (error component) of the differential amplifier 25 passes through the charge transfer element 4 and appears on its output side. Therefore, in terms of direct current, the charge transfer element 4
Negative feedback is applied in a loop from the output side of the circuit to the input side of the charge transfer element 4 via the low frequency converter 21, sample hold circuit 22, low frequency converter 23, differential amplifier 25 and adder 26, and the above-mentioned DC voltage Either of these is forcibly corrected, and an output signal containing a DC voltage always at a constant level, with DC fluctuations corrected, is obtained on the output side of the charge transfer element 4.

Furthermore, if the pass band of the low-pass filter 23 is selected so that the frequency of jitter in the reproduced video signal is sufficiently passed through, it is possible to compress the DC fluctuation of the output signal of the charge transfer element 4 due to the jitter, and the flicker caused by this can be compressed. The phenomenon will also be reduced.

FIG. 3 shows a second embodiment of the present invention. In FIG. 3, parts corresponding to those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

In this embodiment, a differential amplifier 31 whose cut-off frequency is lower than that of the color subcarrier is used in place of the low frequency amplifier 21 used in the first embodiment, and the differential amplifier 25 used in the first embodiment is deleted. , the burst flag pulse generated from the burst flag generator 10 is used as the sampling pulse supplied to the sample and hold circuit 22 instead of using the horizontal synchronizing signal as in the first embodiment, and the voltage is applied to the pedestal of the burst section. hold. That is, a differential amplifier 31 is provided on the output side of the charge transfer element 4, and an output signal of the charge transfer element 4 is supplied to an inverting input terminal of the differential amplifier 31, and a reference signal generator, such as a variable resistor 32, generates a signal. A reference signal is supplied to the non-inverting input terminal of the differential amplifier 31, and the differential amplifier 3
1 output signal is supplied to the sample hold circuit 22. Further, a buffer circuit 33 is provided between the low frequency converter 23 and the adder 26. and charge transfer element 4
The potential of the output signal is set by the variable resistor 32. The other configurations are the same as in FIG. 2.

With this configuration, in this embodiment, the input voltage of the sample and hold circuit 22 can be increased, so that the operation of the sample and hold becomes more stable. Furthermore, since the sample is sampled at the flat part of the back porch portion of the synchronization signal, stable operation can be achieved even if the position and width of the sampling pulse are not very accurate.

In this second embodiment, a horizontal synchronizing signal may be used as the sampling pulse as in the first embodiment, and the DC voltage at the leading edge of synchronization may be held.

FIG. 4 specifically shows an example of the circuit configuration of the main part of the second embodiment, and parts corresponding to those in FIG. 3 are denoted by the same reference numerals, and detailed explanation thereof will be omitted.

As described above, according to the present invention, the output signal of the charge transfer element is sampled and held using a synchronization signal separated from this output signal or a sampling pulse based on this synchronization signal, and the hold voltage is compared with a reference voltage to determine the comparison error. Since the input signal of the charge transfer element is superimposed on the input signal of the charge transfer element, DC fluctuations in the output signal of the charge transfer element due to changes in clock frequency and temperature can be reduced, and the operation of the charge transfer element becomes stable.

Furthermore, as mentioned above, it is possible to reduce DC fluctuations in the output signal of the charge transfer device, so the operating point does not deviate from the voltage range that can be transmitted. It is possible to reduce sharpening of various characteristics such as sharpness, and faithful transmission of signals becomes possible.

Furthermore, since there is no need to provide a dedicated clamp circuit or the like to suppress DC fluctuations, the configuration is simplified.

Therefore, by using this device, the charge transfer device can be used in various fields and the versatility of the charge transfer device can be expanded. In this case, DC fluctuations in the output signal of the charge transfer element, that is, DC fluctuations due to changes in clock frequency and temperature, as well as DC fluctuations in the output signal of the charge transfer element due to jitter, are removed, so screen flickering is prevented. , it is possible to obtain images with excellent image quality, and it is extremely useful for use in equipment etc. that require the electrical function of such a charge transfer element.

Although the above-mentioned embodiment describes the case where the present invention is applied to a video disc player, the present invention is not limited to this, but can be similarly applied to other devices that require the electrical function of such a charge transfer element. can.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a video disc player to which a conventional device is applied, and Fig. 2 is a block diagram showing an example of a video disc player to which the present invention is applied.
FIG. 3 is a block diagram showing a second embodiment in which the present invention is applied to a video disc player, and FIG. 4 is a circuit diagram showing a specific example of the main part of FIG. 3. . 3 is an FM demodulator, 4 is a charge transfer element, 9 is a synchronous separation circuit, 10 is a burst flag generator, 2
Reference numerals 1 and 23 are low-frequency amplifiers, 22 is a sample and hold circuit, 24 and 32 are variable resistors, 25 and 31 are differential amplifiers, and 26 is an adder.

Claims (1)

[Scope of utility model registration request] wave means for removing signal components of a predetermined frequency or higher from the output signal of the charge transfer element and detecting at least the DC component of the output signal; and a synchronization signal separated from the output signal or a sampling pulse based on the synchronization signal. a sample and hold circuit that samples and holds the output signal of the wave means;
Comparing and adding means for comparing the output signal of the sample and hold circuit with a reference signal and superimposing a comparison error on the input signal of the charge transfer element, so as to prevent DC fluctuations in the output signal of the charge transfer element. A drive circuit for a charge transfer element, characterized in that: