JPH05327027A - Voltage variation display element - Google Patents
Voltage variation display elementInfo
- Publication number
- JPH05327027A JPH05327027A JP4133596A JP13359692A JPH05327027A JP H05327027 A JPH05327027 A JP H05327027A JP 4133596 A JP4133596 A JP 4133596A JP 13359692 A JP13359692 A JP 13359692A JP H05327027 A JPH05327027 A JP H05327027A
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- chip
- voltage
- package
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電源電圧の変動、特に
その低下を検出してランプ表示する電圧変動表示素子に
関し、例えば、携帯用音響製品、ＶＴＲカメラ、電話
機、テレビジヨン受像機等の各種携帯用民生機器や産業
機器等に使用される電圧変動表示素子に係る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage fluctuation display element for detecting fluctuations in power supply voltage, particularly a decrease in the power supply voltage, and displaying it in a lamp. The present invention relates to a voltage fluctuation display element used in various portable consumer equipment, industrial equipment and the like.
【０００２】[0002]
【従来の技術】従来の電圧変動表示素子としては、図５
の如く、制御チップ（ＩＣ）および発光チップ（赤色Ｌ
ＥＤ）を内蔵した足（リードフレーム）付きのドーム型
のものがあつた。これは、従来のキヤンタイプの発光装
置についてリードフレームの一部を改造したもので、図
中、１はリードフレーム、２はレンズ形状の樹脂部であ
る。2. Description of the Related Art A conventional voltage fluctuation display device is shown in FIG.
, Control chip (IC) and light emitting chip (red L
There was a dome type with a foot (lead frame) with a built-in ED). This is a modification of a part of a lead frame of a conventional CAN type light emitting device. In the figure, 1 is a lead frame and 2 is a lens-shaped resin portion.
【０００３】そして、図６の如く、電源電圧ＶＤＤが決
められた検出電圧以下に下がつたときに、樹脂部２の内
部に収納されたＬＥＤが点灯する。なお、図６は電圧変
動表示素子を含むレベルシフト回路であり、電圧変動表
示素子の出力端子ＯＵＴは、電源ＶＤＤとＧＮＤの間に
接続されたＰＮＰ型トランジスタＴｒにベース入力され
る。ここで、ＲＢ，ＲＣは抵抗である。Then, as shown in FIG. 6, when the power supply voltage V DD falls below a predetermined detection voltage, the LED housed inside the resin portion 2 is turned on. Note that FIG. 6 shows a level shift circuit including a voltage fluctuation display element, and an output terminal OUT of the voltage fluctuation display element is base-inputted to a PNP transistor Tr connected between a power supply V DD and GND. Here, R B and R C are resistors.
【０００４】この電圧変動表示素子への入力電源電圧Ｖ
ＤＤと出力端子ＯＵＴの電圧ＶＯＵＴとの関係は、図７
のようになる。Input power supply voltage V to this voltage fluctuation display element
The relationship between DD and the voltage V OUT of the output terminal OUT is shown in FIG.
become that way.
【０００５】[0005]
（１）電圧変動表示素子は、用途としてバッテリー駆動
の携帯機器に使用される事が多い。しかも近年、携帯機
器は小型、薄型化が急速に進んでおり、それらに使用さ
れる部品はチップ部品が大半である。(1) The voltage fluctuation display element is often used as a battery-powered portable device. Moreover, in recent years, mobile devices have rapidly become smaller and thinner, and most of the parts used for them are chip parts.
【０００６】これに対し、従来のランプ型の電圧変動表
示素子では、外部実装基板へのリード挿入タイプであっ
て、表面実装が不可能であり、しかも高さ寸法が大であ
るためスペースを取り、超小型化が要求される最近の携
帯機器には使用しにくかつた。On the other hand, the conventional lamp type voltage fluctuation display element is of a lead insertion type on an external mounting substrate, cannot be surface mounted, and has a large height dimension, thus taking up space. , It is difficult to use for the recent portable devices that require ultra-miniaturization.
【０００７】（２）従来のＬＥＤランプタイプの電圧変
動表示素子では、リードフレーム、樹脂部など構成部が
大きいため、材料、生産効率が悪く、コスト的に不利で
あつた。(2) In the conventional LED lamp type voltage fluctuation display element, since the lead frame, the resin portion and the like are large in size, the material and the production efficiency are poor and the cost is disadvantageous.
【０００８】本発明は、小型化、薄型化により表面実装
が可能で、かつリードフレームを使用せずに低コスト化
できる電圧変動表示素子の提供を目的とする。It is an object of the present invention to provide a voltage fluctuation display element which can be surface-mounted by miniaturization and thinning and can be manufactured at low cost without using a lead frame.
【０００９】[0009]
【課題を解決するための手段】本発明請求項１による課
題解決手段は、図１の如く、入力電源電圧ＶＤＤの電圧
変化を表示する発光チップ１２と、前記入力電源電圧Ｖ
ＤＤを基準電圧ＶＲＥＦと比較し入力電源電圧ＶＤＤが
基準電圧ＶＲＥＦより低くなったときに発光チップ１２
を駆動制御するための制御チップ１３とを備えた電圧変
動表示素子において、パツケージ１１に、発光側凹部１
５と制御側凹部１６が形成され、前記発光側凹部１５に
薄膜状の発光側配線部１７が立体的に形成され、該発光
側配線部１７に前記発光チップ１２が搭載され、前記制
御側凹部１６に薄膜状の制御側配線部１８が立体的に形
成され、該制御側配線部１８に前記制御チップ１３が搭
載され、前記発光側凹部１５は、パツケージ１１の上面
に配され、前記制御側凹部１６は、パツケージ１１の下
面に配されたものである。According to a first aspect of the present invention, a light emitting chip 12 for displaying a voltage change of an input power supply voltage V DD and the input power supply voltage V are shown in FIG.
The light emitting chip 12 is compared when DD is compared with the reference voltage V REF and the input power supply voltage V DD becomes lower than the reference voltage V REF.
In a voltage fluctuation display device including a control chip 13 for driving and controlling the light emitting side concave portion 1 in the package 11.
5 and a control side recess 16 are formed, a thin film light emitting side wiring portion 17 is three-dimensionally formed in the light emitting side concave portion 15, the light emitting chip 12 is mounted on the light emitting side wiring portion 17, and the control side concave portion is formed. A thin film-shaped control-side wiring portion 18 is three-dimensionally formed on 16, the control chip 13 is mounted on the control-side wiring portion 18, and the light-emitting side recessed portion 15 is arranged on the upper surface of the package 11, The concave portion 16 is arranged on the lower surface of the package 11.
【００１０】[0010]
【作用】上記課題解決手段において、パツケージ１１に
薄膜状の配線部１７，１８を形成して、これに各チップ
１２，１３を搭載することで、電圧変動表示素子の各部
品を可能な限り一体化する。そうすると、構造の簡略
化、小型薄型化、低コスト化が可能となる。In the above means for solving the problems, thin-film wiring portions 17 and 18 are formed in the package 11 and the chips 12 and 13 are mounted on the wiring portions 17 and 18 to integrate the components of the voltage fluctuation display element as much as possible. Turn into. Then, the structure can be simplified, the size and thickness can be reduced, and the cost can be reduced.
【００１１】また、発光チップ１２が発光しても、これ
と上下に離反する制御チップ１３に光が進入することは
ない。そうすると、光による制御チップ１３の誤動作が
なくなる。Even when the light emitting chip 12 emits light, the light does not enter the control chip 13 which is vertically separated from the light emitting chip 12. Then, malfunction of the control chip 13 due to light is eliminated.
【００１２】[0012]
【実施例】図１は本発明の一実施例を示す電圧変動表示
素子であつて、（Ａ）は平面図、（Ｂ）は（Ａ）のＡ−
Ａ断面図、（Ｃ）は（Ａ）のＢ−Ｂ断面図、（Ｄ）は下
面図、（Ｅ）は（Ａ）のＣ−Ｃ断面図、（Ｆ）は側面図
である。図２は電圧変動表示素子の内部回路構成図、図
３は入力電源電圧と発光チップの点灯との関係を示す
図、図４は点灯時の消費電流を示す図である。なお、図
１（Ａ）（Ｄ）中、各凹部内の透光性封止樹脂は、便宜
上省略している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a voltage fluctuation display device according to an embodiment of the present invention, in which (A) is a plan view and (B) is A- of (A).
A sectional view, (C) is a BB sectional view of (A), (D) is a bottom view, (E) is a CC sectional view of (A), and (F) is a side view. 2 is a diagram showing the internal circuit configuration of the voltage fluctuation display element, FIG. 3 is a diagram showing the relationship between the input power supply voltage and lighting of the light emitting chip, and FIG. 4 is a diagram showing current consumption during lighting. In addition, in FIGS. 1A and 1D, the translucent sealing resin in each recess is omitted for convenience.
【００１３】図示の如く、本実施例の電圧変動表示素子
は、電源電圧の変動を検出してランプ表示するもので、
例えば、携帯用音響製品、ＶＴＲカメラ、電話機、テレ
ビジヨン受像機等の各種携帯用民生機器や産業機器等に
使用される。As shown in the figure, the voltage fluctuation display element of this embodiment detects fluctuations in the power supply voltage and displays a lamp.
For example, it is used for various portable consumer products such as portable audio products, VTR cameras, telephones, television receivers, and industrial equipment.
【００１４】該電圧変動表示素子は、パツケージ１１
と、該パツケージ１１上で外部からの入力電源電圧の電
圧変化を表示する発光チップ１２と、前記入力電源電圧
が予め設定された基準電圧より低くなったときに発光チ
ップ１２を駆動制御するための制御チップ１３とを備え
ている。The voltage fluctuation display element comprises a package 11
A light emitting chip 12 for displaying a voltage change of an external input power supply voltage on the package 11, and a driving light emitting chip 12 for controlling the driving of the light emitting chip 12 when the input power supply voltage becomes lower than a preset reference voltage. And a control chip 13.
【００１５】前記パツケージ１１としては、リードフレ
ームを用いずに、小型、薄型の一体化した部品を得るた
めのＭｏｌｄｅｄ Ｉｎｔｅｒｃｏｎｎｅｃｔｉｏｎ
Ｄｅｖｉｃｅ法（以下、ＭＩＤ法と称す）を用いたもの
である。ここで、ＭＩＤ法とは、射出成形または押出し
成形によつて得られた成形品に化学めつき等の方法で電
気回路を形成したものである。The package 11 is a Molded Interconnection for obtaining a small and thin integrated component without using a lead frame.
The device method (hereinafter referred to as the MID method) is used. Here, the MID method is a method in which an electric circuit is formed on a molded product obtained by injection molding or extrusion molding by a method such as chemical plating.
【００１６】そして、図６の如く、トランジスタＴｒや
抵抗ＲＢ，ＲＣ等を有するレベルシフト回路の一構成部
分として組み込まれる。Then, as shown in FIG. 6, it is incorporated as one component of a level shift circuit having a transistor Tr, resistors R B , R C and the like.
【００１７】すなわち、該パツケージ１１は、耐熱性の
ある液晶ポリマー、ポリフエニレンサルフアイド（ＰＰ
Ｓ）、あるいはポリエーテルスルフオン（ＰＥＳ）等の
電気的絶縁性を有する遮光性樹脂が使用され、一枚の有
機樹脂基板に数百個のデバイスが規則正しく配列される
よう金型成形され、後に図１（Ａ）〜（Ｆ）のような個
別のデバイスにダイシング分割される。該パツケージ１
１の上面には、前記発光チップ１２を収納するための発
光側凹部１５が形成され、パツケージ１１の下面には、
前記制御チップ１３を収納するための制御側凹部１６が
形成されている。ここで、両凹部１５，１６を上下に離
反させているのは、発光チップ１２からの光が制御チッ
プ１３に進入して制御チップ１３が誤動作するのを防止
するためである。That is, the package 11 is made of a heat-resistant liquid crystal polymer, polyphenylene sulfide (PP).
S) or a light-shielding resin having electrical insulation such as polyether sulfone (PES) is used, and a mold is formed so that hundreds of devices are regularly arranged on one organic resin substrate. The chips are diced and divided into individual devices as shown in FIGS. The package 1
A light emitting side concave portion 15 for housing the light emitting chip 12 is formed on the upper surface of 1, and the lower surface of the package 11 is
A control-side recess 16 for accommodating the control chip 13 is formed. Here, the two recesses 15 and 16 are vertically separated from each other in order to prevent light from the light emitting chip 12 from entering the control chip 13 and causing the control chip 13 to malfunction.
【００１８】該各凹部１５，１６は逆台錐形とされ、各
凹部１５，１６の傾斜壁面は、制御チップ１３へのクロ
ストークを防止するための遮光壁とされる。The recesses 15 and 16 have an inverted trapezoidal shape, and the inclined wall surfaces of the recesses 15 and 16 are light-shielding walls for preventing crosstalk to the control chip 13.
【００１９】前記発光側凹部１５には、めつきにて発光
側配線部１７が立体的に形成されている。該発光側配線
部１７には、前記発光チップ１２が上向きに搭載され
る。A light emitting side wiring portion 17 is three-dimensionally formed in the light emitting side concave portion 15 by fitting. The light emitting chip 12 is mounted upward on the light emitting side wiring portion 17.
【００２０】前記制御側凹部１６には、めつきにて制御
側配線部１８が立体的に形成されている。該制御側配線
部１８には、前記制御チップ１３が上向きに搭載され
る。A control side wiring portion 18 is three-dimensionally formed in the control side concave portion 16 by fitting. The control chip 13 is mounted on the control side wiring portion 18 so as to face upward.
【００２１】ここで、前記各配線部１７，１８は、各凹
部１５，１６からパツケージ１１の外周面を介して、図
１（Ｆ）の如く、スルーホール１９の外部接続電極１７
ａ，１８ａにまで引きまわしされている。Here, as shown in FIG. 1F, the wiring portions 17 and 18 are connected to the external connection electrodes 17 of the through holes 19 from the recesses 15 and 16 through the outer peripheral surface of the package 11.
a, 18a.
【００２２】なお、前記発光側配線部１７は、発光チッ
プ１２を搭載するためのみならず、発光チップ１２から
の照射光を凹部１５の傾斜壁面で反射させることにより
光指向特性を高める機能を有する。The light emitting side wiring portion 17 has a function not only for mounting the light emitting chip 12, but also for improving the light directivity by reflecting the irradiation light from the light emitting chip 12 on the inclined wall surface of the recess 15. ..
【００２３】前記発光チップ１２は、可視光発光ダイオ
ード（ＬＥＤ）チツプが用いられ、図２の如く、アノー
ド端子が入力電源ＶＤＤに、カソード端子が出力端子Ｏ
ＵＴに夫々接続される。The light emitting chip 12 uses a visible light emitting diode (LED) chip. As shown in FIG. 2, the anode terminal is the input power source V DD and the cathode terminal is the output terminal O.
Connected to UT respectively.
【００２４】前記制御チップ１３は、複数の電子部品が
集積されたＩＣであつて、図２の如く、基準電圧Ｖ
ＲＥＦを出力する基準電圧電源２１と、該基準電圧電源
２１の基準電圧ＶＲＥＦと入力電源からの入力電源電圧
ＶＤＤとを比較する比較器（オペアンプ）２２と、該比
較器２２での比較結果に基づいて出力電圧を決定するイ
ンバータ２３と、該インバータ２３の出力電圧によつて
発光チップ１２に出力信号を出力する出力部２４とを備
えている。The control chip 13 is an IC in which a plurality of electronic components are integrated, and has a reference voltage V as shown in FIG.
Reference voltage power supply 21 that outputs REF , a comparator (operational amplifier) 22 that compares the reference voltage V REF of the reference voltage power supply 21 with the input power supply voltage V DD from the input power supply, and the comparison result by the comparator 22 And an output unit 24 that outputs an output signal to the light emitting chip 12 based on the output voltage of the inverter 23.
【００２５】前記比較器２２の正入力端子は、抵抗Ｒ１
を介して入力電源ＶＤＤに接続され、かつ抵抗Ｒ２，Ｒ
３を介して接地側端子ＶＳＳに接続される。また、該比
較器２２の負入力端子は、前記基準電圧電源２１に接続
される。The positive input terminal of the comparator 22 has a resistor R1.
Connected to the input power supply V DD via the resistors R2 and R
3 is connected to the ground side terminal V SS . The negative input terminal of the comparator 22 is connected to the reference voltage power supply 21.
【００２６】なお、前記抵抗Ｒ３には、入力電源電圧Ｖ
ＤＤが低下した際に、抵抗Ｒ３にかかる電圧を接地側端
子ＶＳＳに短絡させるためのＦＥＴチップ２５が並列接
続される。The input power source voltage V is applied to the resistor R3.
When DD is decreased, FET chip 25 for the voltage across the resistor R3 is short-circuited to the ground terminal V SS are connected in parallel.
【００２７】前記インバータ２３の入力端子は、前記比
較器２２の出力端子に接続され、インバータ２３の出力
端子は、前記出力部２４の入力端子および前記ＦＥＴチ
ップ２５のゲート端子に接続される。The input terminal of the inverter 23 is connected to the output terminal of the comparator 22, and the output terminal of the inverter 23 is connected to the input terminal of the output section 24 and the gate terminal of the FET chip 25.
【００２８】なお、図２中、２６は定電流回路である。
また、図１中、２７はボンデイングワイヤ（金属細
線）、２８はシリコン樹脂やエポキシ樹脂等の透光性封
止樹脂、２９は遮光性封止樹脂である。In FIG. 2, reference numeral 26 is a constant current circuit.
Further, in FIG. 1, 27 is a bonding wire (fine metal wire), 28 is a translucent sealing resin such as silicon resin or epoxy resin, and 29 is a light shielding sealing resin.
【００２９】上記電圧変動表示素子は、以下のように製
造される。まず、多数のめつきグレードのパツケージ１
１を、複数デバイス分並置して一体的に射出成形する。
この際、各デバイス領域の上面に発光側凹部１５を下面
に受光側１６を形成する。そして、図１（Ａ）〜（Ｆ）
の如く、各凹部１５，１６に金または銀めつき処理を行
い配線部１７，１８を形成する。この配線部１７，１８
は、パツケージ１１のスルーホール１９の外部接続電極
１７ａ，１８ａまで引きまわししておく。The voltage fluctuation display element is manufactured as follows. First of all, a large number of plating grade packaging 1
1 is juxtaposed for a plurality of devices and integrally injection-molded.
At this time, the light emitting side concave portion 15 is formed on the upper surface and the light receiving side 16 is formed on the lower surface of each device region. And FIG. 1 (A)-(F)
As described above, the recesses 15 and 16 are plated with gold or silver to form the wiring portions 17 and 18. These wiring parts 17, 18
Is drawn around to the external connection electrodes 17a and 18a of the through hole 19 of the package 11.
【００３０】次に、導電性ペーストを用いて、発光チッ
プ１２を発光側配線部１７に搭載し、制御チップ１３を
制御側配線部１８に搭載し、ボンデイングワイヤ２７を
用いて夫々ボンデイング結線する。その後、発光側凹部
１５を透光性封止樹脂２８で封止し、制御側凹部１６を
遮光性封止樹脂２９で封止する。Next, the light emitting chip 12 is mounted on the light emitting side wiring portion 17 and the control chip 13 is mounted on the control side wiring portion 18 using the conductive paste, and the bonding wires 27 are used for the bonding connection. After that, the light emitting side concave portion 15 is sealed with a translucent sealing resin 28, and the control side concave portion 16 is sealed with a light shielding sealing resin 29.
【００３１】しかる後、ダイシングソーで切断してチツ
プ化し、図１〜５に示す電圧変動表示素子を完成させ
る。After that, it is cut with a dicing saw and made into chips to complete the voltage fluctuation display element shown in FIGS.
【００３２】表面実装時には、図１（Ｆ）の如く、スル
ーホール１９に形成された各配線部１７，１８の接続電
極部１７ａ，１８ａに半田付けを施して外部接続する。At the time of surface mounting, as shown in FIG. 1F, the connection electrode portions 17a and 18a of the wiring portions 17 and 18 formed in the through holes 19 are soldered to be externally connected.
【００３３】そうすると、メタルリードフレームを用い
ないで、絶縁物としてのパツケージ１１に薄膜状の配線
部１７，１８を形成しているため、ＭＩＤ法の利点、す
なわち、各部品を可能な限り一体化して構造を簡単にで
き、形状を小さくすることが可能であり、コスト低減が
容易であり、また表面実装用部品として使用できる。具
体的には、図５の従来例の高さ寸法が約１ｃｍであつた
のに対し、本実施例では、高さ寸法が２〜３ｍｍに縮小
できた。Then, since the thin film wiring portions 17 and 18 are formed in the package 11 as an insulator without using the metal lead frame, the advantage of the MID method is that the respective parts are integrated as much as possible. The structure can be simplified, the shape can be made small, the cost can be easily reduced, and it can be used as a surface mount component. Specifically, the height dimension of the conventional example of FIG. 5 was about 1 cm, whereas the height dimension of the present example could be reduced to 2-3 mm.
【００３４】また、リードフレームとパツケージのモー
ルド樹脂との間の熱膨張係数の差による剥離等の問題も
なく、半田リフロー時の耐熱性の向上、および熱衝撃に
対しても品質の向上が図り得る。Further, there is no problem such as peeling due to the difference in thermal expansion coefficient between the lead frame and the molding resin of the package, and the heat resistance during solder reflow and the quality against heat shock are improved. obtain.
【００３５】さらに、従来のようにリードピンを外部に
突出させなくてもよいので、リードピンの外力による変
形を防止し得る。Further, unlike the conventional case, the lead pin does not have to be projected to the outside, so that the deformation of the lead pin due to an external force can be prevented.
【００３６】次に、使用時において、入力電源電圧Ｖ
ＤＤが充分なとき、図２の如く、入力電源からの電流
は、抵抗Ｒ１，Ｒ２，Ｒ３を介してＶＳＳに流れ出てい
く。この場合、制御チップ１３の出力端子ＯＵＴには電
流が流れず、発光チップ１２は点灯しない。Next, in use, the input power supply voltage V
When DD is sufficient, as shown in FIG. 2, the current from the input power source, will flow out to V SS via the resistors R1, R2, R3. In this case, no current flows through the output terminal OUT of the control chip 13, and the light emitting chip 12 does not light up.
【００３７】ここで、入力電源電圧ＶＤＤが低下し、図
３に示したＶＤＥＴ（−）以下になると、図２の如く、
常に一定の基準電圧ＶＲＥＦとなる比較器２２の負入力
端子に対し、正入力端子の電圧が低下する。そうする
と、比較器２２でＬＯＷ（０［Ｖ］）出力され、インバ
ータ２３で約５［Ｖ］に反転され、さらに出力部２４か
ら出力されて、発光チップ１２が点灯する。Here, when the input power supply voltage V DD drops and falls below V DET (-) shown in FIG. 3, as shown in FIG.
With respect to the negative input terminal of the comparator 22, which always has a constant reference voltage V REF , the voltage at the positive input terminal decreases. Then, the comparator 22 outputs LOW (0 [V]), the inverter 23 inverts the output to about 5 [V], and the output unit 24 further outputs the light-emitting chip 12 to light.
【００３８】なお、図３中、ＶＤＥＴ（−）は図２中の
抵抗Ｒ２，Ｒ３にて確保される電位が基準電圧ＶＲＥＦ
と一致するために要する入力電源電圧ＶＤＤの値、Ｖ
ＤＥＴ（＋）は図２中の抵抗Ｒ２のみにて確保される電
位が基準電圧ＶＲＥＦと一致するために要する入力電源
電圧ＶＤＤの値である。この際の消費電流は、図４のよ
うになる。In FIG. 3, V DET (-) is the reference voltage V REF which is the potential secured by the resistors R2 and R3 in FIG.
The value of the input power supply voltage V DD required to match
DET (+) is the value of the input power supply voltage V DD required for the potential secured only by the resistor R2 in FIG. 2 to match the reference voltage V REF . The current consumption at this time is as shown in FIG.
【００３９】また、インバータ２３からの出力はＦＥＴ
チップ２５にも出力されるので、抵抗Ｒ３の両端子が短
絡する。The output from the inverter 23 is an FET.
Since it is also output to the chip 25, both terminals of the resistor R3 are short-circuited.
【００４０】そうすると、比較器２２の正入力端子の電
位は、ＦＥＴチップ２５の短絡前に比べると低くなる。Then, the potential of the positive input terminal of the comparator 22 becomes lower than that before the FET chip 25 is short-circuited.
【００４１】このため、比較器２２の正入力端子が初期
の基準電圧ＶＲＥＦ以上に復帰するためには、ＶＤＤが
ＶＤＥＴ（−）より高いＶＤＥＴ（＋）以上となること
が必要となる。Therefore, in order for the positive input terminal of the comparator 22 to return to the initial reference voltage V REF or higher, V DD must be V DET (+) or higher, which is higher than V DET (−). Become.
【００４２】この場合、制御チップ１３を発光チップ１
２に離反させているので、発光チップ１２からの光によ
る制御チップ１３の誤作動がない。しかも、発光チップ
１２の発光時に制御チップ１３が視認されるのを防止で
き、デザイン上のマイナス効果を防止できる。In this case, the control chip 13 is replaced by the light emitting chip 1.
Because the light is emitted from the light emitting chip 12, the control chip 13 does not malfunction. Moreover, the control chip 13 can be prevented from being visually recognized when the light emitting chip 12 emits light, and a negative effect on the design can be prevented.
【００４３】なお、本発明は、上記実施例に限定される
ものではなく、本発明の範囲内で上記実施例に多くの修
正および変更を加え得ることは勿論である。The present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made to the above embodiments within the scope of the present invention.
【００４４】例えば、上記実施例では、各配線部１７，
１８をめつき法にて形成していたが、金属蒸着等の他の
方法で形成してもよい。For example, in the above embodiment, each wiring portion 17,
Although 18 is formed by the plating method, it may be formed by another method such as metal vapor deposition.
【００４５】また、上記実施例では、発光チップ１２を
単体チツプとして実装したが、ＩＣ、ＬＳＩの中に発光
チップ１２を含ませて制御チップ１３に離反させてマウ
ントしてもよい。そうすると、二個分のＩＣが一個分の
スペースで実装できる。Although the light emitting chip 12 is mounted as a single chip in the above embodiment, the light emitting chip 12 may be included in an IC or LSI and mounted separately from the control chip 13. Then, two ICs can be mounted in one space.
【００４６】[0046]
【発明の効果】以上の説明から明らかな通り、本発明に
よると、ＭＩＤ法を用いてパツケージを形成しているの
で、発光チップおよび制御チップを簡単な構造で一部品
に組み込むことが可能で、小型のチップ部品として小型
化できる。したがつて、超高密度実装基板への実装が可
能となり、近年の各種携帯用機器の小型化の要請に対応
できる。As is apparent from the above description, according to the present invention, since the package is formed by using the MID method, the light emitting chip and the control chip can be incorporated into one component with a simple structure. It can be miniaturized as a small chip component. Therefore, it becomes possible to mount on an ultra-high-density mounting board and meet the recent demand for miniaturization of various portable devices.
【００４７】また、発光チップと制御チップをパツケー
ジの上下に離反させているので、発光チップからの光に
よつて制御チップが誤動作するのを防止できるといつた
優れた効果がある。Since the light emitting chip and the control chip are separated from each other above and below the package, it is possible to prevent the control chip from malfunctioning due to light from the light emitting chip.
【図１】本発明の一実施例を示す電圧変動表示素子であ
つて、（Ａ）は平面図、（Ｂ）は（Ａ）のＡ−Ａ断面
図、（Ｃ）は（Ａ）のＢ−Ｂ断面図、（Ｄ）は下面図、
（Ｅ）は（Ａ）のＣ−Ｃ断面図、（Ｆ）は側面図FIG. 1 is a voltage fluctuation display device showing an embodiment of the present invention, in which (A) is a plan view, (B) is a sectional view taken along line AA of (A), and (C) is B of (A). -B sectional view, (D) is a bottom view,
(E) is a sectional view taken along line CC of (A), and (F) is a side view.
【図２】電圧変動表示素子の内部回路構成図FIG. 2 is an internal circuit configuration diagram of a voltage fluctuation display element.
【図３】入力電源電圧と発光チップの点灯との関係を示
す図FIG. 3 is a diagram showing a relationship between an input power supply voltage and lighting of a light emitting chip.
【図４】点灯時の消費電流を示す図FIG. 4 is a diagram showing current consumption during lighting.
【図５】従来の電圧変動表示素子の側面図FIG. 5 is a side view of a conventional voltage fluctuation display element.
【図６】一般的な電圧変動表示素子のレベルシフト回路FIG. 6 is a level shift circuit of a general voltage fluctuation display device.
【図７】一般的な電圧変動表示素子の入力電源電圧と出
力電圧との関係を示す図FIG. 7 is a diagram showing a relationship between an input power supply voltage and an output voltage of a general voltage fluctuation display element.
１１ パツケージ １２ 発光チップ １３ 制御チップ １５ 発光側凹部 １６ 制御側凹部 １７ 発光側配線部 １８ 制御側配線部 11 Package 12 Light-Emitting Chip 13 Control Chip 15 Light-Emitting Side Recess 16 Control-side Recess 17 Light-Emitting Wiring 18 Control-side Wiring
Claims (1)
チップと、前記入力電源電圧を基準電圧と比較し入力電
源電圧が基準電圧より低くなったときに発光チップを駆
動制御するための制御チップとを備えた電圧変動表示素
子において、パツケージに、発光側凹部と制御側凹部が
形成され、前記発光側凹部に薄膜状の発光側配線部が立
体的に形成され、該発光側配線部に前記発光チップが搭
載され、前記制御側凹部に薄膜状の制御側配線部が立体
的に形成され、該制御側配線部に前記制御チップが搭載
され、前記発光側凹部は、パツケージの上面に配され、
前記制御側凹部は、パツケージの下面に配されたことを
特徴とする電圧変動表示素子。1. A light emitting chip for displaying a voltage change of an input power supply voltage, and a control chip for comparing the input power supply voltage with a reference voltage and drivingly controlling the light emitting chip when the input power supply voltage becomes lower than the reference voltage. In the voltage fluctuation display device including the above, the package has a light emitting side recess and a control side recess, and the light emitting side recess is three-dimensionally formed with a thin film light emitting side wiring portion, and the light emitting side wiring portion is provided with A light emitting chip is mounted, a thin film-shaped control side wiring portion is three-dimensionally formed in the control side concave portion, the control chip is mounted on the control side wiring portion, and the light emitting side concave portion is arranged on the upper surface of the package. ,
The voltage fluctuation display element, wherein the control-side concave portion is arranged on the lower surface of the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4133596A JPH05327027A (en) | 1992-05-26 | 1992-05-26 | Voltage variation display element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4133596A JPH05327027A (en) | 1992-05-26 | 1992-05-26 | Voltage variation display element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05327027A true JPH05327027A (en) | 1993-12-10 |
Family
ID=15108510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4133596A Pending JPH05327027A (en) | 1992-05-26 | 1992-05-26 | Voltage variation display element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05327027A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000057491A1 (en) * | 1999-03-19 | 2000-09-28 | Rohm Co., Ltd. | Chip light-emitting device |
| JP2003209295A (en) * | 2002-01-16 | 2003-07-25 | Sony Corp | Electronic component, manufacturing method therefor and image display device using the same |
| JP2008211132A (en) * | 2007-02-28 | 2008-09-11 | Koa Corp | Light-emitting component |
| JP2009076949A (en) * | 2009-01-15 | 2009-04-09 | Nichia Corp | Led display device, and usage therefor |
| WO2010139518A1 (en) * | 2009-06-04 | 2010-12-09 | Osram Opto Semiconductors Gmbh | Optoelectronic semi-conductor component |
| JP2012227514A (en) * | 2011-04-08 | 2012-11-15 | Sony Corp | Pixel chip, display panel, illumination panel, display device, and illumination device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4940117A (en) * | 1972-08-17 | 1974-04-15 | ||
| JPS6278890A (en) * | 1985-10-01 | 1987-04-11 | Ricoh Co Ltd | Dot array device |
| JPH01270282A (en) * | 1988-04-21 | 1989-10-27 | Matsushita Electric Ind Co Ltd | Light emitting diode |
-
1992
- 1992-05-26 JP JP4133596A patent/JPH05327027A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4940117A (en) * | 1972-08-17 | 1974-04-15 | ||
| JPS6278890A (en) * | 1985-10-01 | 1987-04-11 | Ricoh Co Ltd | Dot array device |
| JPH01270282A (en) * | 1988-04-21 | 1989-10-27 | Matsushita Electric Ind Co Ltd | Light emitting diode |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000057491A1 (en) * | 1999-03-19 | 2000-09-28 | Rohm Co., Ltd. | Chip light-emitting device |
| JP2003209295A (en) * | 2002-01-16 | 2003-07-25 | Sony Corp | Electronic component, manufacturing method therefor and image display device using the same |
| JP2008211132A (en) * | 2007-02-28 | 2008-09-11 | Koa Corp | Light-emitting component |
| JP2009076949A (en) * | 2009-01-15 | 2009-04-09 | Nichia Corp | Led display device, and usage therefor |
| WO2010139518A1 (en) * | 2009-06-04 | 2010-12-09 | Osram Opto Semiconductors Gmbh | Optoelectronic semi-conductor component |
| US8482025B2 (en) | 2009-06-04 | 2013-07-09 | Osram Opto Semiconductors Gmbh | Optoelectronic semiconductor component |
| JP2012227514A (en) * | 2011-04-08 | 2012-11-15 | Sony Corp | Pixel chip, display panel, illumination panel, display device, and illumination device |
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