JPH05326871A - Memory module - Google Patents

Abstract

PURPOSE:To adapt a parity bit memory and a data bit memory to each other in operation speed so as to enhance a memory module in profitability by a method wherein a data bit memory IC and a parity bit memory IC higher than the data bit memory IC in operation speed are mounted on the same substrate. CONSTITUTION:A memory module is composed of n data bit memory ICs of low speed and a parity bit memory IC of high speed. The control signal lines of the memory ICs are connected in parallel to terminals. Read/write data signal lines used for write/read of memories are separately connected to the terminals of the data memory ICs and the parity memory IC. By this setup, data memories and a parity memory are read or written from outside of a memory module at the same timing. Data are separately set. As data memories and a parity memory are not separated from each other in a conventional memory module, memories of the same operation speed with a parity memory are used, and data memories of low speed can be used in a memory module of this design.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory module in which a plurality of memory ICs having different operating speeds are mounted on a substrate, and more particularly to a memory I which makes the memory module economical.
Regarding the utilization technology of C.

[0002]

2. Description of the Related Art All memory ICs on a memory module have the same operating speed. Therefore, the memory bit data IC and the parity bit memory IC have the same operating speed. When adding data parity, 1-bit parity is added to n-bit data. Since this parity is created from n-bit data, it takes time until the parity bit is created after the data is determined. In this way, since the parity bit is slower in determining the data than the data bit, when writing data to the memory of the data bit and the parity bit at the same time, the memory IC for the parity bit is better than the memory IC for the data bit. It must be able to operate at high speed. Therefore, in the case of the conventional memory module in which all the ICs in the memory module are configured with the same speed, the operation speed must be matched with the parity memory that requires high speed, and the low speed data bit As a result of using a high-speed memory, even a memory module has to be expensive and uneconomical.

[0003]

As described above, in the past, no consideration was given to adapting the operating speeds of the parity bit memory and the data bit memory in order to make the memory module economical. The memory module was configured to be consistent with the required high speed, which was uneconomical. An object of the present invention is to provide an economical memory module in which the operating speeds of the parity bit memory and the data bit memory are adapted to each other.

[0004]

To achieve the above object, in the memory module of the present invention, for example, as shown in FIG. 1, a data bit memory IC and a data bit memory IC are provided on the same substrate. A high-speed parity bit memory IC is mounted.

[0005]

According to the present invention, the high-speed memory IC suitable for the parity bit and the memory IC suitable for the data bit requiring a lower speed than the above are mounted on the same substrate. The low-speed memory IC is cheaper than the high-speed memory IC, and since the low-speed data bit memory is used in a larger number than the parity bit memory, all memory modules are integrated into an expensive high-speed memory compared to the conventional memory module. Can be made economical.

[0006]

FIG. 1 shows an embodiment of the memory module of the present invention. It consists of n low-speed data bit memories and high-speed parity bit memories. The control signal lines of each memory IC are all connected in parallel and connected to terminals.
The read / write data signal lines for reading and writing the memory are connected to the terminals separately for the data and the parity memory.
As a result, the data and the parity memory are read and written from the outside of the memory module at the same timing. The data is set individually.

FIG. 2 shows the write timing of the memory. In the memory write cycle, the address line is first determined, and the address in the memory for writing data is designated. Next, the write data is determined and written in the memory at the rising edge of the write pulse.
Here, the speed of the memory is the minimum required time as the memory cycle time in terms of the write cycle. This time is represented by the time (C) from the time when the address is fixed and the address is specified until the data can be written, and the time (B) from the time when the write data for writing is fixed to the time when the data can be written. Be done. Since the parity bit is created by calculating the parity of the write data, the parity bit is settled later than the write data. Therefore, the time from data determination to data writing is "B" for write data and "A" for parity data. As a result, if it is attempted to write data and parity to the memory at the rising edge of the write pulse, the parity memory must be faster than the data memory.

Since conventional memory modules do not distinguish between memory for data and memory for parity, memory modules of the same speed as those for parity have been used. In this case, as shown in FIG. 2, since the data memory may be slower than the parity memory, conventionally, the data memory is faster than the required speed. In other words, only the high speed memory for parity should be used, and the low speed memory for data should be used.

As an example of the configuration of the data bit and the parity bit, as shown in FIG. 1, in the case where one parity bit is added to n data bits or when one parity bit is added for every n data bits, and so on. In this case, since all the data bits need only be memories of the same speed, a plurality of bits (for example, 4 bits, 8 bits) parallel one IC may be used. In addition, as for the parity bit, when several bits are collected, an IC for a plurality of bits can be used.

FIG. 3 shows an example of 8-bit data and 1-bit parity, and FIG. 4 shows 8-bit data with 8-bit parallel I.
An example in which C is used and the parity is 1 bit, FIG. 5 is an example having two configurations of data 8 bits and an example having one parity bit for each data configuration, and FIG. 6 is a configuration having four data 8-bit parallel ICs. , An example of a 4-bit parity 1 configuration.

When reading the memory, the parity bit is read faster than the data bit because the data and the parity are read at the same time. However, the parity check is performed after waiting for both the data and the parity to be determined. There is no problem if it is faster.

[0012]

In the past, the speed of the memory for data and the speed for parity were all used for parity, but the speed of the memory for data may be slower than that for parity, so it is inexpensive. Memory can be used.
Since the data memory uses several times as many as the parity memory, the economic effect of the present invention is great.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a write timing chart of the memory module.

FIG. 3 is a bit configuration example of a data bit memory and a parity bit memory.

FIG. 4 is a bit configuration example of a data bit memory and a parity bit memory.

FIG. 5 is a bit configuration example of a data bit memory and a parity bit memory.

FIG. 6 is a bit configuration example of a data bit memory and a parity bit memory.

Claims (1)

[Claims] 1. A data bit memory IC in a memory module having a plurality of memory ICs mounted on the same substrate.
And a parity bit memory IC faster than the data bit memory IC.