JPH04276383A - Random access memory - Google Patents

Abstract

PURPOSE:To prevent the reduction of transmission speed and to increase the packaging density in a wiring board by integrating a serial-parallel function and a parallel-serial converting function in a semiconductor chip. CONSTITUTION:The memory cell array 2 of a RAM chip 1 inputs/outputs data in parallel, and parallel data outputted to a parallel data bus 5 are converted to serial data by a parallel-serial converting part 4. The serial data inputted from a serial data input/output port 8 are inputted through a serial data bus 6 to a serial-parallel converting part 3 and converted to the parallel data. Thus, since by inputting/outputting directly the serial data to/from the RAM chip 1, the transmission speed is not reduced even when the processing through the RAM is performed for the high-speed serial transmission data, and the RAM chip 1 may be only packaged to a wiring substrate, the packaging density can be improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to random access memories.

[0002] In data transmission, random access memory (RAM) is used to perform processing such as data format conversion.
ry), it is necessary to adjust the high-speed serial data transmission speed and RAM access time.

0003

2. Description of the Related Art Conventionally, adjustment between high-speed serial data transmission speed and RAM access time has been performed as follows.

(1) Writing to RAM is performed by serial-parallel conversion of transmission data.

(2) Reading from the RAM is performed by performing parallel-to-serial conversion on the parallel data output from the RAM.

FIG. 4 is a diagram showing a conventional example.

In the figure, 31 is RAM LSI, 32
3 is a serial-to-parallel conversion IC, 33 is a parallel-to-serial conversion IC, and 34 is a data bus.

The RAM LSI 31 has 8-bit input/output ports (I/O1 to I/O8). Storage capacity is arbitrary.

The serial-parallel conversion IC 32 converts the input serial data into 8-bit parallel data and outputs it to the data bus 34.

The parallel-to-serial conversion IC 33 converts input 8-bit parallel data into serial data and outputs the serial data.

The data bus 34 has a data width of 8 bits.

The conventional method of accessing serial data to the RAM will be described below with reference to FIG.

(1) Writing serial data to RAM is input to the Si port of the serial-parallel conversion IC 32. The serial-parallel conversion IC 32 converts input serial data into 8-bit parallel data. Then, the OE signal which is synchronized with the WE (write enable) signal that puts the RAM LSI 31 into the write state
(output enable) signal enables eight output ports (QA, QB, QC, QD, QE, QF, QG,
QH) to the data bus 34. data bus 34
The 8-bit parallel data output to RAMLS
The 8 input/output ports (I/O1, I
/O2, I/O3, I/O4, I/O5, I/O6, I
/O7, I/O8) is input to RAMLSI31 in the write state by the WE signal, and the address signal (A0
~AX) is stored at the address specified.

(2) Read from RAM Specify the address of RAM LSI 31 where data to be read is stored using address signals (A0 to AX). RAMLSI31
transfers the data stored at the address to eight input/output ports (I/O1, I/O2, I/O3, I/O4, I/O
O5, I/O6, I/O7, I/O8) are output to the data bus 34 as 8-bit parallel data. The 8-bit parallel data output to the data bus 34 is
The data is input to the parallel-serial conversion IC 33 from eight input ports (A, B, C, D, E, F, G, H) that the parallel-serial conversion IC 33 has. The parallel-serial conversion IC 33 converts the input 8-bit parallel data into serial data and outputs it from the output port QH.

[0015]

[Problems to be Solved by the Invention] In the conventional example shown in FIG. 4, when high-speed serial transmission data accesses the RAM LSI 31 having an 8-bit I/O port, serial-to-parallel conversion of the transmission data and conversion from RAM to Since the output data is converted from parallel to serial, the RAM
Access to the LSI 31 must be performed at 1/8 of the transmission speed. That is, the conventional example had a problem in that the data transmission speed decreased.

Furthermore, since a serial-parallel conversion IC 32 and a parallel-serial conversion IC 33 are required in addition to the RAM LSI 31, there is also the problem that the number of components mounted on the wiring board increases and the packaging density decreases. Ta.

[0017] The present invention solves these problems and
By making it possible to input and output serial data directly to the AM chip, it is possible to prevent the transmission speed from decreasing even when high-speed serial transmission data is processed through RAM, and to reduce the number of components mounted on the wiring board. The purpose of this invention is to provide a random access memory that can improve packaging density.

[0018]

[Means for Solving the Problems] In order to achieve the above object, the random access memory according to the present invention is capable of writing data to any address in one semiconductor chip, and also allows data to be written to any address in one semiconductor chip. A memory cell array that can read data and input and output data in parallel, a serial-parallel converter that converts input serial data to parallel data and outputs it, and a serial-parallel converter that converts input parallel data to serial data. Parallel to output
A parallel data bus connects the serial converter, the output part of the serial-parallel converter, the input part of the parallel-serial converter, and the input/output part of the memory cell array, and the input part of the serial-parallel converter and the parallel-serial converter. A serial data bus for inputting and outputting serial data to and from the outside of the semiconductor chip is integrated.

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, 1 is a RAM chip, 2 is a memory cell array, 3 is a serial-parallel converter, 4 is a parallel-serial converter, 5 is a parallel data bus,
6 is a serial data bus, 7 is a parallel data input/output port, and 8 is a serial data input/output port.

The memory cell array 2 is capable of writing data to any address specified by an address signal and reading data from any address, and inputs and outputs data in parallel.

The serial-parallel converter 3 converts the input serial data into parallel data and outputs the parallel data.

The parallel-serial converter 4 converts the input parallel data into serial data and outputs the serial data.

The parallel data bus 5 connects the output section of the serial-parallel converter 3 and the input section of the parallel-serial converter 4 to the input/output section of the memory cell array 2.
Transfers parallel data between each section.

The serial data bus 6 connects the input part of the serial-parallel converter 3 and the output part of the parallel-serial converter 4, and transmits serial data to the outside of the RAM chip 1 via the serial data input/output port 8. Perform input/output.

The RAM chip 1 includes a memory cell array 2,
A serial-parallel converter 3, a parallel-serial converter 4, a parallel data bus 5, and a serial data bus 6 are integrated into one semiconductor chip.

[0027]

[Operation] The principle of the present invention will be explained using FIG.

Since the RAM chip 1 of the present invention incorporates a serial-parallel converter 3 and a parallel-serial converter 4, serial data can be directly input and output. As a result, even if processing such as format conversion via the RAM is performed on high-speed serial transmission data, the transmission speed does not decrease. In addition, it is only necessary to mount the RAM chip 1 on the wiring board, and unlike the conventional example, it is necessary to mount the RAM chip 1 on the wiring board.
Since this method does not require the use of 3D components, the number of components to be mounted can be reduced and the packaging density can be improved.

Next, a method of accessing the RAM chip 1 of the present invention will be explained.

(1) Writing serial data Serial data input from the serial data input/output port 8 is input to the serial-parallel converter 3 through the serial data bus 6. The serial-parallel converter 3 is
Converts input serial data to parallel data,
It is output to the parallel data bus 5 by a WE (write enable) signal. The parallel data output to the parallel data bus 5 is input to the memory cell array 2 which is in the write state by the WE signal, and is written to the address specified by the address signal.

(2) Reading of serial data The memory cell array 2 outputs the data stored at the address designated by the address signal to the parallel data bus 5 by an OE (output enable) signal. The parallel data output to the parallel data bus 5 is input to the parallel-serial converter 4. The parallel-serial converter 4 converts the input parallel data into serial data and outputs it to the serial data bus 6 in response to a read strobe signal. The serial data output to the serial data bus 6 is taken out from the RAM chip 1 through the serial data input/output port 8.

[0032]

[Embodiment] FIG. 2 is a diagram showing an embodiment of the present invention.
The RAM chip 1 shown in FIG. 1 is manufactured using normal semiconductor manufacturing technology and is shown packaged.

Each terminal of the RAM according to the present invention shown in FIG. 2 will be explained below.

[0034] A0, A1, A2, A3, A4, A5, A
6, A7, A8, A9, and A10 are address input terminals. I/O1, I/O2, I/O3, I/O4
, I/O5, I/O6, I/O7, and I/O8 are
This is an 8-bit parallel data input/output terminal. Sio is a serial data input/output terminal. CS is a chip select signal terminal, WE is a write enable signal terminal, OE is an output enable signal terminal, DCNT
is a data control signal terminal, and RSTB is a read strobe signal terminal. In addition to these, power supply terminals and the like are required, but terminals that are not directly related to the explanation of the operation of the RAM according to the present invention are omitted.

Next, the operation of the RAM according to the present invention will be explained using the example of the timing chart shown in FIG.

(1) The length of write cycle addresses A0 to A10 changes with the rise of the WE (write enable) signal. DCNT (data control) from t0 at the first rise of the WE signal
Serial data input/output terminal Si for 8 signal pulses
From o, serial data “01, 02, 03, 04, 0
5, 06, 07, 08" are input. The input serial data is written to address "0" at the next rising edge of the WE signal t1. At the same time, the next serial data "11, 12, 13, 14, 15, 16, 17, 1
8" is input. This serial data is written to the address "1" at the next rising edge of the WE signal t2. Thereafter, the same operation is repeated.

(2) The length of read cycle addresses A0 to A10 changes with the rise of the RSTB (read strobe) signal. From the first rising edge of the RSTB signal t0, the parallel data input/output terminals I/O1, I/O2, I/O3, I/O4, I/O5
, to I/O6, I/O7, and I/O8, address "
0” parallel data “01”, “02”, “03”,
“04”, “05”, “06”, “07”, and “08” are output. From the next rising time t1 of the RSTB signal, the serial data “01, 02, 03” is transferred to the serial data input/output terminal Sio for 8 pulses of the DCNT signal.
, 04, 05, 06, 07, 08" are output. At the same time, parallel data input/output terminals I/O1 to I/O8 are output.
to, parallel data “11” to “18” at address “1”
" is output. From the next rising time t2 of the RSTB signal, the serial data "11, 12" is output to the serial data input/output terminal Sio by 8 pulses of the DCNT signal.
, 13, 14, 15, 16, 17, 18'' are output.The same operation is repeated thereafter.

[0038]

According to the present invention, since the RAM chip has a built-in serial-parallel function and parallel-serial conversion function, serial data can be directly input and output as RAM data. As a result, for high-speed serial transmission data, R
Even when processing is performed via AM, the transmission speed does not decrease. In addition, it is only necessary to mount a RAM chip on the wiring board.
Since there is no need for a serial-to-parallel conversion IC or a parallel-to-serial conversion IC as in the past, the number of mounted parts can be reduced and the packaging density can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a timing chart.

FIG. 4 is a diagram showing a conventional example.

[Explanation of symbols]

1 RAM chip 2 Memory cell array 3 Serial-parallel converter 4 Parallel-serial conversion section 5 Parallel data bus 6 Serial data bus 7 Parallel data I/O 8 Serial data I/O

Claims (1)

[Claims] [Claim 1] One semiconductor chip includes a memory cell array (2) that can write data to any address and read data from any address, and input and output data in parallel. a serial-to-parallel converter (3) that converts input serial data into parallel data and outputs it; and a parallel-to-serial converter (3) that converts input parallel data to serial data and outputs it.
4), a parallel data bus (5) connecting the output section of the serial-to-parallel converter (3), the input section of the parallel-to-serial converter (4), and the input/output section of the memory cell array (2); A serial data bus (6) that connects the input part of the parallel converter (3) and the output part of the parallel-serial converter (4) and inputs and outputs serial data to the outside of the semiconductor chip is integrated. A semiconductor integrated circuit device characterized by: