JPH05324496A - Dma controller - Google Patents

Abstract

PURPOSE:To perform time monitor and DMA interruption control at high speed with a hardware by setting the monitor time of DMA control individually for input/output devices concerning the DMA controller to perform the DMA control for the plural input/output devices. CONSTITUTION:This controller is provided with a DMA control part 12 to directly control and monitor the transfer of data, and the DMA control part 12 is provided with a monitor time setting part 14 to set the monitor time for each input/output device for interrupting the direct data transfer control to the input/output devices when there is no response from the input/output devices 21-23, request monitor and control part 15 to detect the presence/absence of the response from the input/output devices 21-23 and to output a DMA interruption request signal for interrupting the direct data transfer control to the input/output devices when there is no response from the input/output devices 21-23 within the monitor time, and DMA interruption control part 13 to interrupt the direct data transfer control by inputting the DMA interruption request signal from the request monitor and control part 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller for direct data transfer control between a plurality of input / output devices and a main memory.

Direct data transfer between a plurality of input / output devices and a main memory by one DMA controller (hereinafter referred to as DM
(Referred to as A), the response of the target I / O device is monitored, and if there is no response from the I / O device within the predetermined monitoring time, the DMA of the I / O device is monitored.
The control is interrupted and the DMA control is transferred to another I / O device.

In such a DMA control, since the CPU timer cannot be used for other processing while the CPU timer is dedicated to the time monitoring of the DMA control, it is necessary to minimize the time dedicated to the monitoring. ..

[0004]

2. Description of the Related Art Conventionally, time monitoring has been performed by firmware when performing DMA control of a plurality of input / output devices by one DMA control device. In this case, since the time interval differs depending on the input / output device, the set monitoring time may be set for each input / output device, but the conventional DMA control device set the monitoring time uniformly. For example, in the case of a magnetic disk device, 16 ms is set to allow for a time to make a round of a track, whereas in the case of a semiconductor disk, 1 ms is sufficient to allow for an average transfer rate. However, since the operation of the firmware is slow in practice, if a short monitoring time such as 1 ms is set, the time dedicated to CPU time monitoring becomes too long, and a short monitoring time should be set. I couldn't.
Therefore, in the past, multiple I / O devices of different types were
The monitoring time for A control is set to a uniformly large monitoring time (for example, 16 ms). FIG. 6 shows the configuration of a conventional DMA controller.

In the figure, 100 is a CPU, which is a CPU on the main body side. Reference numeral 101 denotes a DMA control device, which includes a plurality of input / output devices (I / O) (120, 121, 1).
22) and the main memory 103 to directly transfer data (D
MA). 102 is a system bus, 10
Reference numeral 3 is a main memory, and 104 is a time monitoring means composed of firmware, which uses a CPU timer to monitor the time of the input / output device in the DMA transfer.

Reference numeral 110 is an M in the DMA control device 101.
PU and 111 are adapter control registers for inputting and releasing control commands. Reference numeral 112 denotes a DMA control unit, which performs DMA control.
Reference numeral 113 denotes a DMA interruption control unit, which is a time monitoring means 10
Based on the time-up signal from 4, the DMA control of the target input / output device is interrupted. 114 is DM
RAM / ROM in the A control device. 115 is I
The I / O control unit 1 controls input / output with the input / output device 1 (120). Reference numeral 116 denotes an I / O control unit 2, which controls input / output with the input / output device 2 (121). An I / O controller n 117 controls the input / output with the input / output device n (122). 1
Reference numeral 18 is an internal bus in the DMA control unit. Reference numeral 120 is an input / output device 1, 121 is an input / output device 2, and 122 is an input / output device n.

The time monitoring of the DMA in the configuration shown in the figure will be described. When the DMA is activated, the time monitoring means 104
Detects whether there is a response from the I / O device and counts the time from the data transfer request until the next data transfer request by the timer. And beyond the monitoring time I
If there is no data transfer request from the I / O, the time monitoring means 104
Instructs the DMA controller 101 to suspend the DMA transfer to the input / output device. The DMA interruption control unit 113 performs the interruption processing of the DMA control of the target input / output device.

The MPU 110 is the D for the next input / output device.
The MA is activated, and the DMA control unit 112 starts the DMA control. FIG. 7 shows a time monitoring method in the conventional DMA transfer.

When the DMA is activated in the input / output device 1, the time monitoring means monitors the time with an external timer. Then, in response to a data transfer request from the input / output device 1, data in a data transfer unit (1 byte or 1 word) is transferred.
The figure shows that after the data transfer of the data transfer unit is performed twice,
Indicates that no data transfer request was made. Since there is no data transfer request even after the monitoring time has elapsed, the time monitoring means 104 issues a DMA interruption instruction to the DMA control device 101. As a result, the DMA interruption control unit 113 executes the DMA interruption process, and the MPU 110 starts the DMA of the input / output device 2.

[0010]

In the conventional time monitoring in the DMA control, a large monitoring time is set commonly to each input / output device according to the input / output device having a slow data transfer rate.
It was done by firmware. Therefore, the time occupied by the timer of the CPU for time monitoring becomes large, which hinders other processing of the CPU.

An object of the present invention is to provide a DMA control device capable of efficiently performing time monitoring and DMA control.

[0012]

[Means for Solving the Problems] Time monitoring of DMA and DMA interruption control are performed at high speed by hardware, and a monitoring time is individually set for an input / output device to efficiently perform DM.
A control can be performed.

FIG. 1 shows the basic configuration of the present invention. In the figure, 1 is a CPU on the main body side. Reference numeral 2 denotes a DMA controller, which is a plurality of input / output devices (I / O) (21, 22, 2).
3) and the main memory 3 are DMA-transferred. Reference numeral 3 is a main memory, and 4 is a system bus.

In the DMA controller 2, 10 is an MP
U and 11 are adapter control registers for inputting and releasing control commands. 12 is DMA
The control unit is for performing DMA control and monitoring DMA time. A monitoring time setting unit 14 sets a monitoring time for each input / output device (21, 22, 23). Reference numeral 15 is a request monitoring control unit,
The presence / absence of a data transfer request from the input / output device (21, 22, 23) is determined. Reference numeral 16 is a RAM / ROM in the DMA control device. An I / O control unit 17 controls input / output with the input / output device 1 (21). Reference numeral 18 denotes an I / O control unit 2, which controls input / output with the input / output device 2 (22). 19 is I
The / O control unit n controls input / output with the input / output device n (23). 20 is an internal bus in the DMA controller.

Reference numeral 21 is an input / output device 1, 22 is an input / output device 2, and 23 is an input / output device n.

[0016]

The operation of time monitoring in the operation of the basic configuration of FIG. 1 will be described with reference to FIG. Flow number shown in parentheses
(Refer to FIG. 1 as needed).

(1) The CPU 1 executes the following initial setting by DMA
Instruct the control device 2. The type of connection I / O (21, 22, 23) (type of magnetic disk, semiconductor disk, etc.) is designated.

The average data transfer rate of the connection I / O (21, 22, 23) is designated. (2) The DMA controller sets the maximum waiting time (monitoring time). The maximum waiting time is, for example, a value obtained by calculating the data transfer request time interval of the I / O from the average data transfer speed of the connection I / O, and multiplying the calculated data transfer request time interval by a coefficient with a margin. As a coefficient to allow for margin,
For example, the value 16 is empirically determined in consideration of the data transfer time of the internal buffer of the DMA control unit 12. The average data transfer rate for magnetic disks is 4
If it is MB / S, the data transfer request interval is 2
50 ns (1/4 M) is calculated and 250 ns × 16 = 4
Set 000ns. Similarly, for a semiconductor disk, if the average data transfer rate is 10 MB / S, a data transfer request interval of 100 ns is calculated, and 100 × 16 = 16
Set 00 ns.

Alternatively, the maximum waiting time may be set to 16 ms for a magnetic disk and 1 ms for a semiconductor disk as in the conventional case. However, the above method of determining the maximum waiting time is an example, and the present invention is not limited to this.

(3) The CPU 1 uses the I / O (21, 22, 2
The DMA controller 2 is instructed to read or write 3). (4) When the DMA controller 2 receives a read or write instruction from the CPU 1, it sets the maximum waiting time in the monitoring time setting unit (monitoring time setting register) 14.

Next, the MPU 10 includes the DMA control unit 1
2. Start DMA by 2. (5) The DMA control unit 12 performs the following operation. The request monitoring controller 15 uses I / O (21, 22, 23)
Counting the data transfer request time interval from the I / O (21, 21) when there is no data transfer request within the maximum waiting time (monitoring time) set in the monitoring time setting unit 14.
(22, 23) to suppress the data request and issue a DMA interrupt request to the DMA interrupt controller 13.

The DMA suspension control unit 13 executes the following operation in response to the DMA suspension request from the request monitoring control unit 15. (a) Dummy data is added to the data held in the DMA buffer (not shown), the data transfer request signal is forcibly generated, and the data is forcibly transferred in accordance with the bowing of the main memory 3.

(B) The DMA control unit 12 notifies the MPU 10 of a forced DMA end interrupt after forcibly ending the DMA. (6) Upon accepting the interrupt, the MPU 10 transfers the DMA control to the I / O (21, 22, 23) that needs the next data transfer.

FIG. 3 shows a comparison of operating time between the present invention and conventional time monitoring. (a) is the conventional time monitoring (the description is omitted because it is the same as FIG. 7). (b) shows the time monitoring of the present invention. The time scales of (a) and (b) are the same.

The description of (b) will be given (see FIG. 1 as necessary). The DMA monitoring of the input / output device 1 starts the time monitoring of the request monitoring controller 15. After the data transfer request, even if the time set in the monitoring time setting unit (monitoring time setting register) 14 elapses, there is no data transfer request from the input / output device 1, so the request monitoring control unit 1
Reference numeral 5 requests the DMA interruption control unit 13 for interruption processing. DM
The A interruption control unit 13 performs the DMA interruption processing. And
DMA activation is started for the input / output device 2.

As can be seen from comparison with FIG. 7A, the time monitoring of the present invention is short in the time occupied by the timer without a data request, and the DMA is interrupted until the DMA of the next I / O device is activated. The time is greatly reduced.

FIG. 4 shows an embodiment of the time monitoring unit and the request monitoring unit of the present invention. In the figure, reference numeral 30 is a monitoring time setting unit, which comprises a monitoring time setting register. 31
Is a request monitoring unit. Reference numeral 32 is a time monitoring counter, 33 is a gate A which is composed of an OR circuit, and 34 is a gate C which is composed of an AND circuit. 35 is a data request timeout flip-flop, which is DM
A interrupt request signal (IO REQ T
IMEOUT) is output. 36 is a DMA start flip-flop (DMA START FF). 37 is a gate B, which is composed of an AND circuit.

Signals in the figure have the following meanings. + DMATIMER SET: A signal for setting the monitoring time setting unit (register) 30 through the internal bus from the MPU.

+ DMA START IN: DMA
Start signal for activating. -DMA START: Time monitoring counter 3
2 is a signal for starting the operation.

+ DMA START: resets the time monitoring counter 32 (a signal that resets the count value to 0.) -LOAD INIT: loads the value set in the monitoring time setting unit 30 into the time monitoring counter 32 at the time of starting the DMA. + IO REQ: Data transfer request signal from I / O -TIME UP: IO from I / O
It is a time-up signal output when REQ does not reach the set value for the monitoring time. -CCLR: DMA from MPU
Control signal for resetting the control. + IO REQ TIMEOUT: This signal is output by the time monitoring time-up signal (-TIMEUP) and is sent to the DMA interruption control unit. + IO ACK (see FIG. 5): This is a signal corresponding to IO REQ.

The operations of the time monitoring unit and the request monitoring control unit shown in FIG. 4 will be described with reference to FIG. Monitoring time setting unit 30 from MPU
A monitoring time set signal (DMATIMERSET) is input to and the monitoring time (maximum waiting time) is set.
DMA start signal from MPU (+ DMA START I
N) is a DMA start flip-flop (DMA STAR
T FF) 36. As a result, the output of the DMA start flip-flop (DMA START FF) 36 is turned on (the output Q is + DMASTART having a value of 1).
Is output, the value 0 from the Q bar is -DMA START.
Is output).

-DMA START is input to the time monitoring counter 32, the time monitoring counter 32 starts its operation, and the monitoring time of the monitoring time setting register 30 is fetched and set.

+ DMA START IN and -DMA STA output from the DMA start flip-flop 36
RT is input to the gate B (37), and -L from the gate B
OAD INITIAL is output. -LOAD I
The NIT is input to the time monitoring counter 32 via the gate A33 and resets the time monitoring counter 32 (counts the value of the counter returned to 0).

When there is a data request (IO REQ), IO REQ and + DMA START output from the DMA start flip-flop 36 are input to the gate C34 and the time monitoring counter via the gate A33. 32 is reset.

When there is no data transfer request signal (IO REQ) and the time monitoring counter 32 times up, the time monitoring counter 32 outputs the time up signal (TIM).
E UP) is output. TIME UP is input as a clock of the data request time-out flip-flop 35, and the data request time-out flip-flop 35 outputs a signal (+ IO REQTIME OUT) for requesting DMA interrupt control to the interrupt controller (not shown).

+ IO REQ TIME OUT is DM
The data is input to the A interruption control unit, and the interruption control unit adds dummy data to the data remaining in the buffer of the DMA control unit and forcibly transfers it to the main memory.

[0037]

According to the present invention, the DMA interruption control is speeded up, and the time can be monitored by setting the individual monitoring time in the input / output device, so that the DMA control can be efficiently performed. Moreover, since the CPU timer is not exclusively used for time monitoring, the processing of the entire system is made efficient.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing a time monitoring operation of the basic configuration of the present invention.

FIG. 3 is a diagram showing a comparison of operating times of the present invention and conventional time monitoring.

FIG. 4 is a diagram showing an embodiment of a time monitoring unit and a request monitoring unit of the present invention.

FIG. 5 is an operation explanatory diagram of a time monitoring unit and a request monitoring unit of the present invention.

FIG. 6 is a diagram showing a configuration of a conventional DMA control device.

FIG. 7 is a diagram showing a time monitoring method in a conventional DMA transfer.

[Explanation of symbols]

 1: CPU 2: DMA control device 3: Main memory 4: System bus 10: MPU 11: Adapter control register 12: DMA control unit 13: DMA interruption control unit 14: Monitoring time setting unit 15: Request monitoring control unit 16: RAM / ROM 17: I / O control unit 1 18: I / O control unit 2 19: I / O control unit n 21: I / O device 1 22: I / O device 2 23: I / O device n

Claims (2)

[Claims] 1. A main memory (3) and an input / output device (21, 22,
23) DMA controller for direct data transfer with (2)
DMA control unit for direct data transfer control and monitoring in (12)
The DAM control unit (12) has a monitoring time setting for each input / output control device that sets a monitoring time for interrupting direct data transfer control for the input / output device when there is no response from the input / output device. Direct data for the I / O device is detected if there is no response from the I / O device and the I / O device, and if there is no response from the I / O device within the monitoring time set in the monitoring time setting unit (14). A request monitoring control unit (15) that outputs a DMA interrupt request signal for interrupting transfer control, and a request monitoring control unit (1
5) The DMA interruption request signal from 5) is input, and the DMA interruption control unit (13) for interrupting the direct data transfer control is provided, and the direct data transfer is monitored according to the monitoring time set for each I / O device. DMA characterized by having a function
Control device. 2. The method according to claim 1, wherein when the direct data transfer control is suspended, the DMA suspension controller (13) converts dummy data left in the DMA controller (2) into dummy data having a predetermined data length. A DMA controller characterized by being added and forcibly transferred to the main memory (3).