JP2012198605A - Data transfer device and field equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly detect that a transfer failure has been generated while maintaining the performance of a system (without depriving a CPU of its processing capability) in a data transfer device for performing the DMA transfer of predetermined data which periodically arrive.SOLUTION: The data transfer device (to which a microcomputer 110 is equivalent) includes as representative configurations: a DMA controller 116 for, on the basis of the transfer request of predetermined data (physical quantity data) which periodically arrive, transferring the data; a timer in a data transfer monitoring circuit 120 for measuring the lapse of a time on the basis of the transfer request; and a time-out detection circuit for detecting the time-out of the timer. The data transfer device is configured to monitor a time until the data transfer is completed, and to, when the transfer of the whole data is not completed within the time, and time-out occurs, issue an error by determining that a transfer failure has been generated.

Description

  The present invention relates to a data transfer apparatus that DMA-transfers predetermined data that arrives periodically, and a field device that incorporates the data transfer apparatus.

  In field devices such as industrial instruments, data on physical quantities (for example, flow rate, pressure, temperature) detected by sensors is periodically transferred to the sensor I / F circuit (interface circuit), and the DMA controller periodically detects the sensor. There is a configuration in which the data accumulated in the I / F circuit is written into the memory (DMA transfer). In such a field device, when a failure (disruption or delay) occurs in the data transfer for some reason, it is necessary to take measures such as detecting it and generating an error.

  As a method for detecting the transfer failure, two methods are generally used. The first method is a method in which the CPU monitors the time until the data transfer is completed by software, and if the transfer of the entire data is not completed within that time, an error is generated as a transfer failure has occurred. . The second method is a method in which an interrupt is generated in the CPU every time the DMA controller transfers data, and the CPU confirms whether the data transfer is completed.

  Note that Patent Documents 1 and 2 are known as conventional techniques related to DMA transfer.

Japanese Patent Laid-Open No. 7-219887 JP 2003-6139 A

  In the first method, even if a transfer failure occurs midway, the transfer failure is left until the time when the entire data is scheduled to be transferred. For this reason, it is impossible to deal with the transfer failure for a long time, and there is a problem that a large rework occurs.

  On the other hand, in the second method, when a transfer failure occurs midway, this can be detected quickly. However, it is a major concern that the CPU cannot perform more important processing (the CPU processing capacity is lost) due to frequent interruptions to the CPU.

  Therefore, there is a strong demand for a new technique that can quickly detect a transfer failure without causing frequent interruptions to the CPU and without a time-out associated with non-transfer of the entire data requiring a long time. The present invention has been made in view of the above problems, and an object of the present invention is to provide a new technique capable of quickly detecting a transfer failure when a transfer failure occurs without degrading the performance of the system.

  In order to solve the above-described problems, a typical configuration of a data transfer apparatus according to the present invention includes a DMA controller that transfers data based on a transfer request for predetermined data that arrives periodically, and a time based on the transfer request. And a time-out detection circuit for detecting a time-out of the timer.

  According to this configuration, the transfer failure is not left for a long time unlike the first method, and the transfer failure can be detected and dealt with promptly. Further, unlike the second method, interrupts to the CPU do not occur frequently. This is because the occurrence of a transfer failure is determined based on whether or not a transfer request (DMA transfer request) arrives periodically without operating the CPU. Therefore, the system performance can be maintained without depriving the CPU of processing capacity.

  Preferably, the data transfer device further includes a transfer request transmission path that is independent of the internal bus and transmits a transfer request to the DMA controller, and a branch path that branches from the transfer request transmission path and transmits the transfer request to the timer. Thereby, a transfer failure can be detected suitably.

  In the data transfer device, it is preferable that a timer is connected to the internal bus, and a timeout threshold of the timer is set through the internal bus. Thereby, a transfer failure can be detected suitably.

  The data transfer device may be built in the field device. Thereby, it is possible to obtain a particularly remarkable effect.

  According to the present invention, a data transfer device capable of quickly detecting when a transfer failure occurs while maintaining the performance of the system (without depriving the processing capacity of the CPU), and the data transfer device are incorporated. Field equipment can be provided.

It is a block diagram which shows schematic structure of the field apparatus concerning embodiment of this invention. FIG. 2 is a block diagram illustrating a schematic configuration of a data transfer monitoring circuit illustrated in FIG. 1. It is a figure which illustrates the operation example of the transfer failure detection of the data transfer of the microcomputer shown in FIG.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The dimensions, materials, and other specific numerical values shown in the embodiments are merely examples for facilitating understanding of the invention, and do not limit the present invention unless otherwise specified. In the present specification and drawings, elements having substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted, and elements not directly related to the present invention are not illustrated. To do.

  FIG. 1 is a block diagram showing a schematic configuration of a field device 100 according to an embodiment of the present invention. As shown in FIG. 1, the field device 100 includes a microcomputer 110 corresponding to a data transfer device, a sensor 102, and a communication circuit 136.

  A microcomputer 110 as a data transfer device according to the present embodiment includes a CPU 124, a memory 126, a sensor I / F circuit 112, a DMA controller 116, a data transfer monitoring circuit 120, an interrupt controller 122, and a communication I / F circuit 128. Composed. These are connected by an internal bus 130.

  The sensor 102 converts data (predetermined data) of the detected physical quantity (for example, flow rate, pressure, temperature) from an analog signal to a digital signal, and periodically transmits it to the sensor I / F circuit 112 (interface circuit) of the microcomputer 110. Forward to.

  The data transferred to the sensor I / F circuit 112 is temporarily stored in the buffer 114. When the buffer 114 becomes full, the sensor I / F circuit 112 issues a transfer request to the DMA controller 116 through a transfer request transmission path 132 independent of the internal bus 130 (separate from the internal bus 130). This transfer request is issued periodically.

  Upon receiving the transfer request, the DMA controller 116 accesses the buffer 114 of the sensor I / F circuit 112 through the internal bus 130 and temporarily reads the data in the buffer 114 into its own buffer 118. Thereafter, the DMA controller 116 writes the data temporarily read into the buffer 118 to the memory 126.

  The field device 100 is connected to a host control device and other field devices via the communication bus 138. As a result, the data stored in the memory 126 can be transmitted to these devices via the communication I / F circuit 128 and the communication circuit 136.

  Hereinafter, a method for detecting a transfer failure, which is a feature of the present embodiment, will be described. As a feature of the present embodiment, a data transfer monitoring circuit 120 is provided in the microcomputer 110 corresponding to the data transfer device.

  FIG. 2 is a block diagram showing a schematic configuration of the data transfer monitoring circuit 120. As shown in FIG. 2, the data transfer monitoring circuit 120 includes a timer 120a that measures the passage of time and a timeout detection circuit 120b that detects a timeout of the timer 120a.

  The data transfer monitoring circuit 120 is connected to the internal bus 130 of the microcomputer 110 and a branch path 132a branched from the transfer request transmission path (see FIG. 1). Upon receiving a transfer request (DMA transfer request) from the sensor I / F circuit 112 entering from the branch path 132a to the DMA controller 116, the timer 120a starts measuring time. Then, upon receiving the next transfer request, the time until the present is reset, and the time measurement is newly started. The timer 120a measures time with reference to an internal clock of the microcomputer 110 or the like.

  The timeout threshold of the timer 120a is set by a command from the CPU 124 via the internal bus 130 (the threshold is rewritten). The threshold value is incorporated in a program that runs on the CPU 124 or is input by the administrator via the program. This threshold is set based on the interval between transfer requests (DMA transfer requests) issued periodically.

  As described above, when a transfer request is periodically received from the sensor I / F circuit 112, the timer 120a does not time out, and the timer 120a times out only when a transfer failure occurs and the transfer request is interrupted or delayed.

  The timeout detection circuit 120b detects a timeout of the timer 120a and outputs a signal to cause the interrupt controller 122 to generate an interrupt to the CPU 124. When receiving an interrupt signal from the interrupt controller 122, the CPU 124 performs processing such as giving an error to the administrator.

  According to the configuration described above, it is possible to quickly detect a transfer failure without waiting for transfer of the entire data (without requiring a long time). Further, since the detection of the transfer failure is completed by the data transfer monitoring circuit 120 without causing the CPU 124 to work, the processing capability of the CPU 124 is not deprived. That is, interrupts to the CPU 124 are only performed when the data transfer monitoring circuit 120 detects a transfer failure, so that frequent interrupts to the CPU 124 can be eliminated.

  This configuration is possible because a data transfer monitoring circuit 120 is newly provided, a transfer request transmission path 132 for transmitting a transfer request to the DMA controller 116 is branched (a branch path 132a is provided), and this data transfer is performed. This is because the monitoring circuit 120 is connected. Since the transfer (DMA transfer) by the DMA controller 116 is a technique for increasing the transfer speed by performing transfer without using the CPU 124, the CPU 124 knows the transfer request (signal on the transfer request transmission path 132) conventionally. could not. Therefore, conventionally, as described in the background art of this specification, an interrupt is generated in the CPU 124 in units of data transfer, and the CPU 124 is checked whether the data transfer is completed, or the entire data is not transferred. They had to wait until the accompanying timeout occurred.

  Hereinafter, specific operation examples will be illustrated. FIG. 3 is a diagram illustrating an example of the operation of detecting a transfer failure in data transfer of the microcomputer 110. As illustrated in FIG. 3, the microcomputer 110 first receives the first transfer data in the buffer 114 of the sensor I / F circuit 112, and issues a transfer request (DMA transfer request) when the buffer 114 is full. Then, the DMA controller 116 reads the data into its own buffer 118 and writes it into the memory 126 after the reading is completed. The timer 120a starts measuring time from the start of the transfer request.

  In general, transfer data periodically arrives from the sensor 102 to the sensor I / F circuit 112. However, here, the second transfer data arrives regularly, but the third transfer data arrives with a delay due to the occurrence of a transfer failure. Therefore, the second transfer data is written into the memory 126 in the same manner as the first transfer data, and the time measurement of the timer 120a is reset (initialized) in accordance with the transfer request for the second transfer data. Since the transfer request for the third transfer data is issued with a delay, the timer 120a times out.

  It is possible to take measures such as giving an error due to this timeout, or to retransfer or discard the transfer data in which the delay has occurred. That is, if the transfer data is not periodically transferred, an interruption to the CPU 124 occurs. Therefore, it can be determined that no transfer failure has occurred because no interruption to the CPU 124 has occurred. .

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to this example. For example, in the above-described embodiment, the physical quantity data of the sensor 102 is illustrated as equivalent to “predetermined data” recited in the claims, but is not limited to this example. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  The present invention can be used as a data transfer device that DMA-transfers predetermined data that arrives periodically, and a field device that incorporates the data transfer device.

DESCRIPTION OF SYMBOLS 100 ... Field apparatus, 102 ... Sensor, 110 ... Microcomputer (data transfer apparatus), 112 ... Sensor I / F circuit, 114 ... Buffer, 116 ... DMA controller, 118 ... Buffer, 120 ... Data transfer monitoring circuit, 120a ... Timer, 120b ... timeout detection circuit, 122 ... interrupt controller, 124 ... CPU, 126 ... memory, 128 ... communication I / F circuit, 130 ... internal bus, 132 ... transfer request transmission path, 132a ... branch path, 134 ... access path, 136: Communication circuit, 138: Communication bus

Claims (4)

A DMA controller that transfers the data based on a transfer request of predetermined data that periodically arrives;
A timer for measuring the passage of time based on the transfer request;
A timeout detection circuit for detecting a timeout of the timer;
A data transfer device comprising: A transfer request transmission path for transmitting the transfer request to the DMA controller independently of an internal bus;
2. The data transfer apparatus according to claim 1, further comprising a branch path that branches from the transfer request transfer path and transmits the transfer request to the timer. The timer is connected to an internal bus;
3. The data transfer apparatus according to claim 2, wherein a timeout threshold of the timer is set through the internal bus.   A field device including the data transfer device according to claim 1.

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