JPH05324395A - Program debugging device - Google Patents

Abstract

PURPOSE:To provide the program debugging device capable of breaking operation and data tracing at the optional position of a program even for the ROMed program. CONSTITUTION:The optional debugging position is registered by a register group 14 and the read position of an instruction is held by a register 15. Coincidence between the register group 14 and the register 15 is discriminated by a comparator 16. An interruption instruction transmission part 17 transmits a specific software interruption instruction at the time of the coincidence and masks the actually stored instruction. A specific software interruption processing part 22 analyzes the position of an interruption source when the interruption is generated by the execution of the specific software interruption instruction and performs the breaking operation or the data racing based on preregistered information. A command processing part 24 sets, changes or displays registered positions information to be referred to by the specific software interruption processing part 22. A RAM 13 is used as a working area. A CPU 11 corrects the debugging information of the optional debugging position by the software interruption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debugging device for debugging a program.

[0002]

2. Description of the Related Art Conventionally, in a program debugging device, a program and fixed data are stored in a RAM (random access memory) as a storage element whose storage content can be changed for debugging. ..

In such a device, a specific software interrupt instruction is sent to the command processor by the application processor.
Write it in the program. Then, the application unit executes the specific software interrupt instruction.

In the interrupt processing unit activated by the execution of this specific software interrupt instruction, the location of the interrupt source is obtained from the interrupt recovery information. Next, the registration table of the processing information is indexed at the location of the interrupt source to obtain the previously registered processing type, and the data trace or break operation is performed.

After that, the original instruction before writing a specific software interrupt instruction is restored, the single step operation is set, and the original instruction is executed so that the original instruction is executed. After setting 1 to return one instruction, restore the interrupt.

Immediately after executing the original instruction, the interrupt processing started by the set single-step interrupt cancels the single-step operation, and again writes a specific software interrupt instruction, and then interrupts. It was supposed to be restored.

[0007]

In such a conventional program debugging device, the program is stored in the RAM and replaced with a specific software interrupt instruction by a command. Therefore, it is impossible to rewrite the stored contents of the program and fixed data.
Such a method could not be adopted in a device which stores data in M (read only memory).

Therefore, an object of the present invention is to provide a program debugging device capable of performing a data trace and a break operation at a desired location registered in advance even in a ROMized program.

[0009]

A program debugging apparatus according to the present invention has a register group in which an arbitrary debug location is registered in advance, and if an instruction is read at a location registered in this register group, the memory content will not be affected. First, a memory bus having an interrupt instruction sending unit for sending a specific software interrupt instruction to the bus and a location of an interrupt source when an interrupt occurs due to the execution of the specific software interrupt instruction. Set, change, or display an interrupt processing unit that analyzes and performs a data trace or break operation based on previously registered information, and the registration information referred to by the arbitrary debug location and the interrupt processing unit. A first storage unit that stores a program and fixed data that configure each of the command processing units, and a second storage unit that is a work area during program execution. Comprising a 憶 means, a central processing unit for collecting debug information for any debug points by the occurrence of the interrupt.

The memory bus is provided with a register group for registering an arbitrary debug point, a comparator for determining a match between the register point and the instruction read point, and a specific software. The interrupt processing unit may be configured to include an interrupt command transmitting unit that transmits an interrupt command and a control unit that enables or disables the operation of the interrupt command transmitting unit. It is also possible to obtain the location of the data source and to index the registration information in which the content of the data to be collected next is registered to perform the data trace or break operation.

[0011]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a program debugging apparatus according to the present invention. The debugging device of this embodiment is a central processing unit (CPU) 11
And a ROM 12 storing a program and fixed data
A RAM 13 as a work area, a register group 14 for registering a debug location, a register 15 for holding an instruction read location, a register group 14 and a register 1.
5, a comparator 16 for judging the coincidence with 5, and an interrupt command sending unit 17 comprising a sending unit for sending a specific software interrupt command on the memory bus and a control unit for controlling the validity or invalidity of its operation. , A memory data bus 18, a memory address bus 19, and a memory control bus 20 for controlling instructions, addresses and data.

The application section 2 is stored in the ROM 12.
1, a specific software interrupt processing unit 22 of a specific software interrupt instruction, a single-step interrupt single-step interrupt processing unit 23 and a command processing unit 24
The programs for realizing each are stored.

FIG. 2 is a simplified flow chart showing an example of the flow of the program in the application section of FIG. In the application unit 21, a certain process A is performed (step S101), and then the instruction at the debug location is executed (step S102). If the register group 14 is registered in advance as a debug point, the interrupt instruction sending unit 17 becomes effective when reading this instruction,
Instead of the instruction actually stored, it is read and executed in place of a specific software interrupt instruction.

FIG. 3 is a flowchart showing how the specific software interrupt processing section 22 of FIG. 1 performs processing. The specific software interrupt processing unit 22 first performs a process of analyzing a location that is an interrupt source (step S201). Next, a process of indexing the analyzed interrupt location and indexing information registered in advance is performed (step S202).

After the indexing is performed, the corresponding processing is performed based on the obtained information. That is, when the type of processing is data trace (step S203; Y
es), collect the data to be processed in the registration information (step S204), and proceed to the next processing (step S206).

When the type of processing is break operation (step S203; No), control is passed to the monitor (step S205). And when the monitor returns control,
The process proceeds to the next process (step S206).

In the next processing, in order to execute the instruction actually stored in the debug location (step S102), (a) single step operation is set.

(B) The operation setting of the interrupt command sending section 17 is invalidated and the sending of the interrupt command is stopped.

(C) The instruction execution pointer in the interrupt recovery information is returned by one instruction.

After executing the series of processes, the interrupt is restored (end).

Returning again to the application section 21 of FIG. Since the operation setting of the interrupt command sending unit 17 is invalid,
The instruction actually stored in the debug location is executed (step S102). Further, since the single-step operation is set, a single-step interrupt is generated again before the next process B is performed (step S103).

FIG. 4 is a flow chart showing the control of the single-step interrupt processing unit of FIG. The single-step interrupt processing unit 23 again releases the (a) single-step operation in order to validate the setting of the debug location again.

(B) The operation setting of the interrupt command sending section 17 is made valid, and the sending of the interrupt command is made valid.

After executing the series of processes of (1), the interrupt is restored (end).

FIG. 5 is a flow chart showing the control of the command processing section 24 of FIG. In the command processing unit 24,
Register an arbitrary debug location in the register group 14, and
The registration information referred to by the specific software interrupt processing unit 22 activated by an arbitrary specific software interrupt command is set, changed, or displayed (step S401).

As described above, in the program debugging apparatus of this embodiment, two types of processing are registered in advance in the register group at any debug location of the application section 21 and are actually stored at that location. A specific software command instead of the current command to the CPU 11 to generate a software interrupt,
Collect the debug information of the relevant part. Therefore, even if the program of the application unit 21 is stored in the ROM, the debug information collecting function can be realized.

Further, it is possible to register an arbitrary debug location and switch the processing type of the debug information collecting processing to be performed there, that is, the data trace and the break operation by a command.

[0029]

As described above, according to the present invention, even in a device in which a program is stored in a storage means that cannot be rewritten when the program is executed, the data trace or the break operation can be debugged at any place. There is an effect that the information collecting function can be executed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a program debug device according to the present invention.

FIG. 2 is a flow chart showing an example of the flow of a program in the application unit of FIG.

FIG. 3 is a flowchart showing how the specific software interrupt processing unit of FIG. 1 performs processing.

FIG. 4 is a flowchart showing how the single-step interrupt processing unit in FIG. 1 is controlled.

5 is a flowchart showing how the command processing unit of FIG. 1 performs processing.

[Explanation of symbols]

 11 CPU 12 ROM 13 RAM 14 Register Group 15 Register 16 Comparator 17 Interrupt Command Sending Section 18 Memory Data Bus 19 Memory Address Bus 20 Memory Control Bus 21 Application Section 22 Specific Software Interrupt Processing Section 23 Single・ Step interrupt processing unit 24 Command processing unit

Claims (3)

[Claims] 1. A register group in which an arbitrary debug location is registered in advance, and a specific software interrupt instruction is transferred to a bus when instruction reading is performed at a location registered in this register group, regardless of the stored contents. A memory bus having an interrupt command sending unit for sending and an interrupt source part is analyzed when an interrupt occurs due to execution of the specific software interrupt command, and based on information registered in advance. A program and fixed data that configure the interrupt processing unit that performs data trace or break operation, and the command processing unit that sets, changes, or displays the registration information referred to by the arbitrary debug location and the interrupt processing unit, respectively. The stored first storage means, the second storage means as a work area during program execution, and arbitrary debug by the occurrence of the interrupt A debugging device for a program, comprising: a central processing unit for collecting debugging information of a location. 2. The memory bus includes a register group for registering an arbitrary debug location, a comparator for determining a match between a location registered in the register group and an instruction read location, and a specific software. 2. The program debugging apparatus according to claim 1, wherein the bus is composed of an interrupt command sending unit for sending an interrupt command and a control unit for enabling or disabling the operation of the interrupt command sending unit. 3. The interrupt processing unit obtains the location of the interrupt source from the interrupt recovery information and indexes the registered information that registers the content of the data to be collected next to perform a data trace or break operation. 3. The program debugging apparatus according to claim 1, wherein the program debugging apparatus is a program debugging apparatus.