JPS61204703A - Developing device for engine control computer system - Google Patents

Abstract

PURPOSE:To execute a debug so that an execution of a regular program is not obstructed, by executing an access preferentially to a computer system to be debugged, when the access has competed. CONSTITUTION:When control signals of an access from control buses 41, 43 have competed, a control device 40 executes preferentially the using right of a bus 33 connected to a CPU 73. Accordingly, the CPU 73 can execute smoothly a regular program without waiting. A CPU 20 executes an access to a bidirectional memory, when the CPU 73 does not execute an access to a bidirectional memory 30. In this way, when necessity has been generated, the CPU 73 debugs a data inputted from the bidirectional memory 30.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is an engine control system useful for the development of microcomputer systems, particularly for the development of systems for controlling automobile engines that require high-speed signal processing and control. This invention relates to a computer system development device.

[Prior Art] In the development of a control computer system that handles temporally varying events, debugging the control constants of the computer system requires the following steps in order to maintain simultaneity with regular program execution: It is desirable to execute a monitor program for debugging without stopping or affecting the operation of the computer. In particular, in a car engine that rotates at high speed, the above-mentioned simultaneity is required for debugging control constants of a control computer system.

However, the conventional debugging system is configured as shown in the block diagram shown in FIG. 7, and debugging of control constants is executed according to the flowchart shown in FIG. That is, in this method, the contents of the ROM 205 in which control constants are stored are transferred to the RAM 207 for debugging. Therefore, in a debugging method during system operation, the contents of the RAM 207 are read/written by a monitor program that runs sequentially in time after the system control program is executed. Therefore, if debugging is interrupted midway,
System operating time will be longer than real time. For this reason,
It was not possible to debug simultaneously with the actual system production.

[Problems to be Solved by the Invention] Therefore, the present invention provides a bidirectional memory that can be used in common by the program that arrives directly and the monitor program, and reads/writes control constants to the bidirectional memory. By disposing a control device that controls write access and giving priority to the execution of the regular program, the access of the monitor program can be performed without affecting the execution of the regular program, and the concurrency can be maintained. The purpose is to be able to perform debugging work on control constants while satisfying the following.

[Means for Solving the Problems] The present invention provides: a memory having a program to be processed by a computer; a microcomputer that inputs and executes the program from the memory; and the microcomputer and a computer system to be debugged. a bidirectional memory connected by a first bus and a second bus and accessed from both directions by the respective buses; a first control bus and a second control bus connected to the microcomputer and the computer system to be debugged, respectively; Control that allows the computer system to be debugged to access the bidirectional memory by giving priority to the access from the second control bus when the two control buses are connected via a control bus and accesses from the respective control buses are input at the same time. This is a development device for an engine control computer system, comprising: a device; and a display device that displays the contents of the bidirectional memory based on a control signal from the microcomputer.

FIG. 1 is a block diagram illustrating the invention in detail.

The memory 10 is a storage device having a monitor program for debugging the computer system 70 to be debugged, and as a storage medium, for example, a ROM1 magnetic disk, a bubble cassette, etc. can be used.

The microcomputer 20 (hereinafter the microcomputer will be abbreviated as CPU) inputs and executes the monitor program, and also provides information to the bidirectional memory 30, which will be described later.
This is a device that executes data read/write access according to instructions from the control device @40.

The bidirectional memory 30 has a first bus 31 and a second bus 33 each consisting of an address bus and a data bus, and each bus is connected to the CPU 20 and the system 7.
The control bus 35 is connected to the control device 40. As the bidirectional memory 30, for example, a dual port RAM can be used.

The control device 40 includes the CPU 20 and the CPU 73.
and are connected by control buses 41 and 43, respectively, and when accesses from the control buses 41 and 43 conflict, priority is given to the right to use the control bus 43.

Examples of the display device@50 include a CRT display,
Printers etc. are available.

[Operation] The computer system 70 that the device 60 of the present invention attempts to debug controls the engine 75 according to the regular program input from the memory 71 by the CPLJ 73 .

When the start switch of the device 60 of the present invention is turned on, the CPL
The I20 inputs a debug monitor program from the memory 10 and executes the program.

The CPU 73 and the CPU 20 access the bidirectional memory 30 according to their respective programs. The control device 40 receives an access control signal from the CPU 20.73 via the control bus 41.43. The control device 40
When access control signals from the respective control buses 41 and 43 conflict, priority is given to the right to use the bus 33 connected to the CPLJ 73. Therefore, the CPtJ7
3, the regular program can be executed smoothly without waiting. The CPU 20 accesses the bidirectional memory 30 when the CPU 73 does not access the bidirectional memory 30, and when the need arises, the CPU 73 accesses the bidirectional memory 30.
debugs the data input from the bidirectional memory 30. A display device [50] displays the debugging status of the bidirectional memory 30 in response to a control signal from the CPU 20.

[Examples] The present invention will be described in detail below based on specific examples. FIG. 2 is a block diagram showing the configuration of an engine control computer system development apparatus according to a specific embodiment of the present invention.

The microcomputer that executes the monitor program is C
It is composed of a PU 20, and its memory is composed of a ROM 10 in which a monitor program for debugging is written. A keyboard 5 for controlling the monitor program is provided, and a display device is composed of a CRT 50. Bidirectional memory is R
It consists of AM317.

The control unit [40 is composed of a cycle steal 1IIIn'11 circuit 400.

The computer system to be debugged by the device of the present invention, that is, the target microcomputer system 70 (hereinafter abbreviated as microcomputer system 70) that is the target of control constant debugging, is as follows:
Control device CPU73 and RO with regular program
It consists of an M71 and an engine 75 as an object to be controlled by the CPLI 73.

Next, the block diagram of FIG. 2 shows how the bidirectional memory 30, which is a characteristic part of the device of the present invention, is accessed by the CPU 20173, and the timing when the CPU 20 reads from the bidirectional memory 30 shown in FIG. This will be explained using a chart.

That is, all accesses to the RAM 317 are performed in synchronization with the timing of the CPU 73 of the microcomputer system 70.

The RAM 317 that the CPU 20 attempts to read
BSY4 is written to the address registers 319 and 320 in the order of upper and lower addresses, and inputs the processing request signal RQ425 to the cycle steal control circuit 400.
26 becomes H, notifying the CPU 20 that the RAM 317 is in use. From the CPU 73 to the RAM
When the access to the RAM 317 is completed and the signal CACC 427 indicating the access from the CPU 73 to the RAM 317 becomes L, access from the CPIJ 20 side is permitted and becomes ACC-1. At this time, the RE429 signal is generated in synchronization with the E signal E428 of the CPLJ73, and the RE429 signal is generated.
Upon completion of step 429, the BSY 426 is cleared and the CPU 20 is notified that the processing request has ended. When a read request is generated from the CPIJ20 in this way, the CPU
The request is processed at the timing of one read/write cycle of 73. The same timing applies to write requests.

Incidentally, FIG. 6 shows an embodiment of the main parts of the cycle steal control circuit 400 for realizing the read timing shown in FIG. 3.

Next, the operation of the device of this embodiment will be explained as follows: CP tJ 73, CP
This will be explained using the flowcharts of FIGS. 4 and 5, in which the U20 processes the respective processes.

The microcomputer system 70 includes a microcomputer in step 100.
Executes only the system control program. C.P.
U20 executes a monitor program in ROM10. The bidirectional memory 30 has a control constant RAM 317 to which the contents of the control constant ROM 315 containing the control constants of the microcomputer system 70 are transferred, and which can be rewritten to perform matching.

Step 202 is a step with input from the keyboard 5, and when a command is input from the keyboard 5, the process moves to the next step 204, and the target to be accessed by the CP (J73) of the microcomputer system 70 is changed to the control constant RAM.
After setting it to 317, start debugging.

As a feature of the device of this embodiment, a 2-boat memory 317 is provided as the control constant memory, and by performing cycle steal control on the 2-boat memory 317, the microcomputer system 70 is exactly the same as when the CPU 20 is not connected. The control constant memory can be accessed by the processing procedure and processing FRrflJ. The CPU 20 inputs the address of the control constant RAM 317 and the content to be rewritten from the keyboard 5, and rewrites the content of the address to the data value of the content.

This operation is performed by cycle steal control in the two-vote memory 317 while the microcomputer system 70 is not accessing the control constant RAM 317.

Step 206 is a step of displaying the contents of the control constant RAM 317 on the CRT display 50. When the display is completed, the process jumps to step 202 and executes the series of operations described above.

According to this embodiment, cycle steal control is performed on accesses to the 2-boat memory from two asynchronous and different systems, the system of the CPU 20 and the microcomputer system 70 of the CPU 73, so that the access of the microcomputer system 70 has priority. The microcomputer system 7o is not burdened in operation by connecting the cPU 20 system, and can debug control constants while operating normally.

As a modification of the above embodiment, the following method can also be used. That is, two RAMs forming the bidirectional memory 30 are provided, one being accessed by the CPU 73 and the other being accessed by the CPU 73.
20 to distinguish it from a RAM whose constants are rewritten. After rewriting all the control constants that need to be changed, the RAM accessed by the CPU 73 is switched using a specific trigger. By doing this, the CPU 73
In this case, the same effect as when the control constants are changed all at once instead of one data at a time can be obtained.

Further, as the trigger factor, for example, a command trigger by manual keystroke, an address trigger which is triggered when the CPU 73 of the microcomputer system accesses a specific address, a trigger by external input, etc. can be used.

[Effects of the Invention] According to the present invention, a bidirectional memory accessed by both the microcomputer of the engine control computer system development device and the microcomputer of the computer system to be debugged is provided, and A control device is installed to control access from the microcomputers, and when there is conflict between accesses, W
Since Aυ111111 gives preferential access to the computer system to be debugged, debugging can be performed without interfering with the execution of a program that is normal for debugging.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the invention in detail. FIG. 2 is a block diagram illustrating an engine control computer system development apparatus according to a specific embodiment of the present invention. Figure 3 shows the CP of the same example.
FIGS. 4 and 5 are timing charts when the U20 accesses the bidirectional memory 30, and FIGS.
CPLJ73 and CPLJ20 used in the same example
3 is a flowchart showing a program for processing. FIG. 6 is a block diagram illustrating the main parts of the Nicle Steel control circuit used in the same example, and FIG.
FIG. 8 is a block diagram showing the configuration of a development system and a flowchart of computer processing, respectively, to explain conventional snow preparation. 1o...Memory 2o...Microcomputer 30...Bidirectional memory 40...Control device 5o.
...Display device patent applicant Nippondenso Co., Ltd. agent Patent attorney Hirotoshi Okawa Patent attorney Shudo Fujitani Patent attorney Akio Maruyama Figure 3, □ Figure 5 procedural amendment (voluntary) April 12, 1985 Showa 1960 Patent Application No. 044466 2 Name of the invention Development device for engine control computer system 3 Relationship with the person making the amendment Case Patent applicant Representative Nippondenso Co., Ltd., 1-1 Showa-cho (42B), Kariya City, Aichi Prefecture Person 1) Kengo 4, Agent 8-3-4 Meieki, Nakamura-ku, Nagoya, Aichi Prefecture 460 Figure 2 of the detailed explanation of the invention in the specification □ 6. Contents of amendment (1) On page 8, lines 5 and 6 of Meifusho, it says “RAM
317. '' should be corrected as in the following sentence. It is composed of rRAM 317 and ROM 31δ. This R.O.
M315 stores basic control constants for regular programs stored in memory 71 in computer system 70, and the contents are stored in RAM 317 during debugging.
will be forwarded to. Therefore, the computer system 70 operates according to the regular program and the control constants, and the control constants are rewritten and changed in the RAM 317 so that the operation becomes appropriate. (2) Add the following sentence after "..." on page 10, line 15 of the specification. j The control constant ROM 315 is originally the microcomputer system 7.
0, but when debugging control constants, it is built in the bag 60 of the present invention and used as a 2-board memory like the RAM 317. Access from CI' U 73 is from ROM315 or R
The ROM/R of the CPU 20 is manually executed from the keyboard 5 to be executed for either one of the AM317.
Switching can be performed by switching C8 according to an instruction from an AM signal. CI) at startup of the device 60 of the present invention)
Access from U 73 is fixed to r1M315, the keyboard instructs the transfer of control constants from ROM 315 to RAM 317, CPU 20 executes this, switches the access destination from CPU 73 to RAM 317, and debugs the control constants. I do. C)' Reading from U 20 to ROM 315 is performed in the same way as reading to RAM 317, and which one to read depends only on the switching. (3) Page 12, line 7 of the specification "...I can."
Add a written statement after . ``Then, the debugged results, that is, the contents of RAM 317 that have been properly rewritten, are stored in an external P-R (not shown).
It is stored in OM or EP-ROM. Thereafter, depending on the result, the mask of the ROM 71 is changed using, for example, a general semiconductor process to add control constants to the regular program. (4) Add the ROM 315 to Figure 2 of the drawings as shown in the attached sheet. 7. List of attached documents

Claims (1)

[Scope of Claims] A memory having a program to be processed by a computer, a microcomputer that inputs the program from the memory and executes the program, and connects the microcomputer and the computer system to be debugged to a first bus and a second bus, respectively. a bidirectional memory connected by a bus and accessed from both directions by the respective buses; a bidirectional memory connected to the microcomputer and the computer system to be debugged by a first control bus and a second control bus, respectively; a control device that gives priority to access from the second control bus when accesses from the respective control buses are input at the same time and causes the computer system to be debugged to access the bidirectional memory; A display device for displaying the contents of the bidirectional memory according to a control signal of the engine control computer system.