JPH05323909A - Display method for liquid crystal display device - Google Patents

Abstract

PURPOSE:To drive a liquid crystal with low electric power when the electromo tive force of a power supply battery is reduced in relation to a method for displaying a liquid crystal display device with low electric power. CONSTITUTION:In a method for displaying display data on a liquid crystal display device, a display control part 1 is provided with a display control part 2 generating a synchronizing signal of a standard period and a display control part 2' generating a synchronizing signal of a longer period than the standard period in a low electric power mode to drive the liquid crystal display device with the low electric power. In the low electric power mode, writing control to a frame memory 12 is executed by the synchronizing signal of the longer period than the standard period and reading control is executed by the synchronizing signal of the standard period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a liquid crystal display device with low power. A personal computer (personal computer) has a configuration connectable to both a liquid crystal display device and a CRT. In such a personal computer, a frame memory for liquid crystal display control is provided in order to absorb the difference in driving conditions between the liquid crystal display device and the CRT, and data for one screen of the liquid crystal display is stored in the frame memory and displayed from the frame memory. Data is read out and displayed on the liquid crystal.

Such a battery-driven liquid crystal display device for a portable personal computer or the like needs to be driven with as low power as possible and the battery life needs to be extended as long as possible. Therefore, it is necessary to make it possible to display the display screen without flickering even when the battery voltage drops, but conventional liquid crystal display devices have not taken measures against the power supply voltage drop.

[0003]

2. Description of the Related Art FIG. 7 shows the structure of a conventional display device. In the figure, reference numeral 70 denotes a display control unit (CRTC) which generates a horizontal synchronizing signal, a vertical synchronizing signal of the CRT and the liquid crystal display device, a control clock signal (CCLK) for display control, etc. in accordance with a display clock. Is. Reference numeral 71 denotes a frame memory control unit which controls writing and reading of the frame memory and display control of the liquid crystal display device. A frame memory 72 stores display data for one screen. 73 is a liquid crystal display device, and 74 is a CRT.

A system bus interface 75 serves as an interface between the system bus of the computer main body and the system bus 76 of the display device. 7
Reference numeral 6 is a system bus, and reference numeral 77 is a graphic memory control unit for designating an address of the graphic memory and writing and reading graphic data.
Reference numeral 78 denotes a character memory control unit which addresses the character memory 80 and the font memory 81 and writes and reads character data. A graphic memory 79 stores graphic data. A character memory 80 stores a character code. A font memory 81 stores a pattern of characters corresponding to a character code. Reference numeral 82 denotes a signal synthesizing unit for synthesizing graphic data and character data to synthesize display data for one screen. The outline of the operation of the configuration shown in the figure will be described.

A display control unit (CRTC) 70 has a horizontal synchronizing signal, a vertical synchronizing signal and a display control clock (C) for the CRT 74 and the liquid crystal display device 73 according to a display clock.
CLK) and supplies it to the CRT 74, the liquid crystal display device 73 and the frame memory control unit 71 (hereinafter, when simply referred to as a synchronization signal, a horizontal synchronization signal, a vertical synchronization signal, a display control clock (CCLK), a DISP signal (described later). , See FIG. 9))). At the same time, the CRTC 70 also sends a synchronization signal to the graphic memory controller 77 and the character memory controller 78. Then, the graphic memory control unit 77 specifies an address in the graphic memory according to the synchronization signal from the CRTC 70 to write or read data. Similarly, the character memory control unit 78 designates addresses to the graphic memory 79 and the font memory 81 in accordance with a synchronization signal from the CRTC 70 to write or read data.
The signal synthesizing unit 82 synthesizes the graphic display data fetched from the graphic memory 79 and the display data in character units fetched from the font memory 81 corresponding to the character code of the character memory 80 to obtain display data for one screen.

The CRT 74 displays the display data on the screen according to the display data sent from the CRTC 70 and the synchronizing signal. On the other hand, the frame memory controller 71 uses the CRTC 70
In accordance with the sync signal sent from the frame memory 7
Address 2 is specified and display data is written and read. Then, the frame memory control unit 71 displays the data read from the frame memory 72 on the liquid crystal according to the synchronization signal and the display data.

The operation of the configuration of FIG. 6 will be described later. A liquid crystal display device in which the liquid crystal screen is vertically divided into two and driven will be described with reference to FIG.

FIG. 8 shows a two-divided liquid crystal screen. Figure 8 is horizontal 8
0 block (1 block is 8 dots horizontally × 1 dot vertically),
Shows the case of vertical 400 lines (1 line is 1 dot),
A shows the upper half and B shows the lower half. In order to represent the address of one block, the upper half A is represented by numbers from 1 to 80 in the horizontal direction, and the lower half B represents the address of one line in the horizontal direction by 2
It is represented by numbers from 01 to 280.

FIG. 9 is a time chart of a conventional liquid crystal display. A display method of a conventional liquid crystal display device will be described with reference to FIG. In the figure, DCLK (1) is a control clock for dots of display data. When one block is displayed with horizontal 8 dots, DCLK (1) has eight cycles in one cycle of CCLK (1). CCLK (1) is a display control clock for controlling the horizontal synchronizing signal (1), the vertical synchronizing signal (1), the DISP signal (1) and the like.

The horizontal synchronizing signal (1) is the horizontal synchronizing signal (1) of the liquid crystal display device. The DISP signal (1) controls the horizontal display period of the display data of one line, and the horizontal front porch portion from the fall of the horizontal sync signal (1) to the rise of the DISP signal (1) and the DISP signal ( 1)
It consists of the horizontal back porch portion from the falling edge of to the rising edge of the horizontal synchronizing signal. The display data represents a cycle of writing (W) and reading (R) of the frame memory once. The figure shows a case where display control of 80 blocks is performed by one line. In one horizontal display period, the write cycle controls the readout of display data of 80 blocks per line and the read cycle is 40 blocks above and 40 blocks below the liquid crystal screen. Controls reading of block display data. The frame memory cycle represents a write cycle (W) and a read cycle (R) of the frame memory. One cycle of write and read is performed in one cycle of display data. The frame memory write address represents a write address designation cycle of the frame memory, and 80 addresses are designated in one horizontal display period corresponding to each block of one line. The read address of the frame memory represents a cycle for designating the read address of the frame memory, and the upper half and the lower half of the liquid crystal screen are alternately addressed. 1,
3, ..., 40 are addresses of 1-line blocks in the upper half, and 201, 202, ..., 240 are addresses of 1-line blocks in the lower half.

The above describes the control of one line of each signal. The display line, vertical sync signal (1), and DISP signal (1) represent control for one screen. The display lines in the figure represent a display cycle in the case of 400 lines per screen. The vertical sync signal (1) and the bottommost DISP signal (1) represent each cycle of one screen.

The display operation for one line will be described in accordance with the signals shown in the figure. Horizontal sync signal synchronized with CCLK (1)
(1) occurs. After the horizontal sync signal (1) rises,
The DISP signal (1) rises in synchronization with CCLK (1). Then, the control of the display data is started in synchronization with the rising edge of the DISP signal (1). That is, DISP
Display data of 80 blocks is controlled in one horizontal period of (1). Then, in one cycle of the display data, one writing (W) and one reading (R) of the frame memory are performed. At this time, as shown in the frame memory write address, the writing to the frame memory is sequentially designated and written for the horizontal 80 blocks of one line. When the display data in the frame memory is read and displayed, the upper half and the lower half of the liquid crystal display screen are alternately addressed one block at a time and the corresponding display data is displayed.

When display is performed up to 400 display lines, a vertical synchronizing signal (1) is generated, and the above processing is repeated from the first block of the first line of the liquid crystal display device.

[0014]

The conventional battery-driven liquid crystal display device is designed only when the supply voltage of the power supply battery is above a certain level, and is low power when the power supply battery is low. It wasn't meant to be displayed in mode.

The present invention makes it possible to drive the liquid crystal at low power when the electromotive force of the power supply battery is reduced, and also when driving at low power, there is no flicker of the display screen, An object of the present invention is to provide a display method of a liquid crystal display device which can display almost the same.

[0016]

According to the present invention, when it is necessary to drive the liquid crystal display device in a low power mode due to a decrease in the voltage of a battery for driving the liquid crystal display device or the like, a frame is displayed in a unit time (one frame time). The number of screens to be transferred to the memory has been reduced so that it can be driven with low power. On the other hand, the frame memory read cycle was not changed, and the screen flicker was minimized due to power saving.

FIG. 1 shows the basic configuration of the present invention. In the figure, 1 is a display control unit, 2 is a display control unit (1) (CRTC
(1)), and when the power supply voltage is normal, the standard period synchronization signal (1) (horizontal synchronization signal (1), vertical synchronization signal (1), C
CLK (1) and DISP (1) are generated). Reference numeral 2'denotes a display control unit (2), which is provided with a frequency dividing circuit for dividing the display clock, and when the output voltage of the power supply battery drops, a synchronizing signal (2) (horizontal synchronizing Signal (2), vertical sync signal (2), CCLK (2), DIS
(Including the P signal (2)).

Reference numeral 3 is a selection unit (1) for generating a synchronization signal (2) having a period slower than the standard period of the display control unit (2) based on the low power mode setting signal.
3'is a frequency dividing circuit. A low power mode setting signal generator 4 generates a signal for setting the low power operation mode of the liquid crystal display device on the basis of a decrease in power supply voltage or the like.

A graphic / character memory 5 is composed of a graphic data memory and a character data memory. A memory control unit 6 controls the graphic memory / character memory 5. Reference numeral 7 is a selection unit (2) for selecting the synchronization signal (1) when driving in the standard mode and selecting the synchronization signal (2) in the low power mode such as when the power supply voltage drops. Is.

Reference numeral 8 denotes a frame memory control unit, which controls the display data to be written in or read out from the frame memory 12 according to the synchronization signal (1) or (2) and displayed on the liquid crystal display device. is there. 9
Is a write address generator, which sequentially generates the write address of the frame memory in a standard cycle in the standard mode, and generates the write address in a cycle slower than the standard cycle in the low power mode. Reference numeral 10 denotes a read address generation unit that sequentially generates the read address of the frame memory at a standard cycle in both the standard mode and the low power mode. A frame memory access control unit 11 writes display data in the frame memory 12 or reads display data from the frame memory 12 and controls display on the liquid crystal display device.

Reference numeral 12 is a frame memory, and 13 is a liquid crystal display device.

[0022]

The operation of the basic configuration of FIG. 1 will be described with reference to FIGS. FIG. 2 is an explanatory diagram of the display data transfer method of the present invention.

In the figure, (a) shows a conventional display method, showing that display data (data for one screen) of 400 lines per frame time is transferred to the frame memory. (b) shows an example of a display data transfer method in a low power mode such as when the power supply voltage drops. For example, the display data of one screen is transferred to the frame memory in two frame times. The time required for display data of one screen is not limited to 2 frame times, 4 frame times,
It can be adopted variously as necessary such as 8 frame time. In the standard mode such as when the power supply voltage is normal, the same display data transfer method as in the past is followed.

FIG. 3 is a diagram for explaining the operation of the basic configuration of the present invention when the power supply voltage drops. The figure shows an example in which the display data of one screen is controlled to be written in the frame memory at a time twice as long as that in the standard mode (two frame times) (see FIG. 2B).

In the figure, (a) is CCLK (2),
The dotted line shows the case of the standard mode. (b) shows the cycle of display data, and the dotted line shows the case of standard mode. (c) is a frame memory cycle and represents a write (W) and read (R) cycle. The frame memory cycle operates in the same cycle in the low power mode and the standard mode. (d) shows a cycle of the frame memory write address, which is a cycle slower than the standard mode (for example, twice as long) (the dotted line shows the standard mode).
(e) shows the cycle of the frame memory read address, which has the same cycle in the standard mode and the low power mode.

The operation of the basic configuration of FIG. 1 in the case of the low power mode will be described (see FIG. 1). The low power mode setting signal generator 4 generates a low power mode setting signal (for example, detecting a drop in the power supply voltage). Selector (1)
3 detects the low power mode setting signal and divides the display clock. The display control unit (2) (CRTC2) 2'outputs the synchronizing signal (2) slower than the standard.

At the same time, the selection section (2) 7 selects the synchronization signal (2) by inputting the low power mode setting signal and transfers it to the memory control section 6. The memory control unit 6 performs write control and read control of the graphic / character memory 5 according to the synchronization signal (2).

The frame memory access control unit 11 performs write control and read control to the frame memory in the low power mode based on the low power mode setting signal. At this time, the write address generator 9 generates a write address in a cycle slower than the standard mode according to the sync signal (2). The read address generator 10 generates a read address in the same cycle as in the standard mode even in the low power mode.

The operation of the frame memory control unit will be described with reference to FIG. In the low power mode, the frame memory control unit 8 controls the writing and reading of the display data according to CCLK (2). Frame memory 12
Write control and read control are performed according to the frame memory cycle (c), and write (W) and read (R) are performed at the same cycle as in the standard mode. The frame memory write address cycle by the write address generator 9 is performed at a cycle twice as long as that in the standard mode. Therefore, one line of data is written in two frame times. On the other hand, the read address generator 10 reads the display data of the frame memory at the same cycle as in the standard mode. For example, the frame memory addresses 1 and 201 are generated between the display data 1, the frame memory addresses 1 and 201 are read out in 2 frame time, and the liquid crystal display device 1
Display in 3. Therefore, the display control on the liquid crystal display screen is performed in the same cycle as the standard mode.

In the low power mode of the present invention, the write control time and the display data period of the frame memory access control are longer than those in the standard mode, and at the same time, one horizontal scanning time is extended, so that the liquid crystal display can be saved in power. However, since the read cycle is the same as in the standard mode, the display on the liquid crystal display device can be performed in the same manner as in the standard mode. Therefore, since the read cycle is shorter than the write cycle to the frame memory, there is a read period for empty display data, but flicker on the screen can be suppressed to a minimum.

[0031]

FIG. 4 shows the configuration of an embodiment of the present invention. In the figure, 20 is a low power mode setting signal generator, and 21 is a selection circuit (1).
(2) The synchronization signal (2) is output from (CRCT (2)). 22 is a display control unit (1) (CRTC
(1)). 23 is a display control unit (2) (CRTC (2))
Is. A selection circuit (2) 24 selects the synchronizing signal (1) in the standard mode and selects the synchronizing signal (2) according to the low power signal mode setting signal.

A system bus interface 25 serves as an interface with the system bus of the control unit on the main body side. 26 is a system bus, 27 is a graphic memory, 27 'is a graphic memory control unit, 2
8 is a character memory, 28 'is a font memory, 29
Is a character memory control unit.

Reference numeral 30 is a signal synthesis unit, 31 is a frame memory control unit, 32 is a frame memory, and 33 is a liquid crystal display device. In the configuration shown in the figure, the CRT is omitted. The operation of the configuration shown in the figure will be described later.

FIG. 5 shows the configuration of the frame memory controller of the present invention. In the figure, 40 is a frame memory control unit,
A write address counter 41 generates a write address. The write address counter generates a write address in the low power mode at a time period twice as long as in the standard mode. 42 is a read address counter, which generates a read address. The read address counter generates a read address at the same time cycle in both the standard mode and the low power mode. 43
Is a frame memory access control unit, 44 is a frame memory, and 45 is a liquid crystal display device.

The operation of the embodiment of FIG. 6 in the low power mode will be described. The selection circuit (1) 21 divides the display clock based on the low power mode setting signal so that the CRTC (2) 23 outputs CCLK (2). Selection circuit (2)
24 selects CCLK (2) based on the low power mode setting signal. The graphic memory control unit 27 'is a synchronization signal.
By (2), writing to and reading from the graphic memory is performed. The character memory control unit 29 controls writing and reading of the character memory 28 and the font memory 28 '. The signal synthesizer 30 synthesizes graphic data and character data to create display data for one screen. The frame memory control unit 31 generates an address and writes the display data in the frame memory, generates an address and reads the display data from the frame memory, and displays it on the liquid crystal display device.

FIG. 6 is a time chart in the low power mode according to the embodiment of the present invention. In the configuration shown in the figure, the standard mode when the power supply voltage is normal operates according to the time chart of FIG.

In the figure, DCLK (2) is a clock for dot control of display data. The cycle is the same as the dot control clock (DCLK (1)) in the standard mode (see FIG. 9). CCLK (2) is a display control clock and has a time period twice that of CCLK (1) in the standard mode. The dotted line in CCLK (2) shows the standard mode CCLK (1). Horizontal sync signal (2), DISP
Signal (2) is horizontal sync signal (1) in standard mode, DI
It functions in the same way as the SP signal (1), but the time period of each is doubled. Similarly, the display data and the frame memory write cycle have twice the time period as compared with the standard mode. The frame memory cycle and the frame memory read address cycle are the same as in the standard mode.

The time period of the display line and the vertical synchronizing signal (2) is also twice that of the standard mode. According to FIG. 6, the CRT of the present invention
The operation of C (2) and the frame control unit will be described (Fig. 4,
See FIG. 5).

The CRTC (2) 23 generates CCLK (2) and also outputs a horizontal synchronizing signal (2), a vertical synchronizing signal (2), D
Generate the ISP signal (2) (the sync signal (2) includes those signals).

Write address counter 41 (see FIG. 5)
Input the low power mode setting signal, and
Write addresses are generated in a double time cycle. And C
A write address is generated based on CLK (2) and DISP signal (2). The frame memory control unit 40
In FIG. 5, the display data is written in the frame memory at a time period twice that of the standard mode.

Read address counter 42 (see FIG. 5)
Input the low power mode setting signal, and input D of sync signal (2).
Start counting based on the ISP signal (2). At that time, read addresses are sequentially generated at the same time cycle as in the standard mode. Frame memory access controller 43 (FIG. 5)
Reads the data in the frame memory according to the frame memory cycle and transfers the read display data to the liquid crystal display device 33.

The read address is generated in the order of the upper half address 1, the lower half address 201, the upper half address 2 and the lower half address 202 of the liquid crystal, and 160 is set during one horizontal synchronizing signal (2). indicate. During this time, display data of one line (80 blocks) is written in the frame memory.

When the processing of 400 lines (one screen) is completed, the vertical synchronizing signal (2) is generated, and the same processing as described above is repeated for the next display data.

[0044]

According to the present invention, a liquid crystal display driven by a battery can be displayed with low power consumption in a low power mode. Therefore, even if the electromotive force of the power supply battery is lowered, the liquid crystal display can be performed. The battery life can be extended.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing a method of transferring display data according to the present invention.

FIG. 3 is an operation explanatory diagram of the basic configuration of the present invention (in the low power mode).

FIG. 4 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a frame memory control unit of the present invention.

FIG. 6 is a time chart of the configuration of the embodiment.

FIG. 7 is a diagram showing a configuration of a conventional display device.

FIG. 8 is a diagram showing a two-divided liquid crystal display screen.

FIG. 9 is a diagram showing a time chart of a conventional liquid crystal display.

[Explanation of symbols]

 1: Display control unit 1 2: Display control unit (1) (CRTC (1)) 2 ': Display control unit (2) (CRTC (2)) 3: Selection unit (1) 4: Low power mode setting signal generation Part 5: Graphic / character memory 6: Memory control unit 7: Selection unit (2) 8: Frame memory control unit 9: Write address generation unit 10: Read address generation unit 11: Frame memory access control unit 12: Frame memory 13: Liquid crystal display

Claims (3)

[Claims] 1. A liquid crystal display device (13), a frame memory (12) for storing display data for one screen, and a frame memory
Write the display data to (12) and
The data written in 2) is read and the liquid crystal display device (13)
The frame memory control unit (8) for controlling the display of the display, the frame memory (12) and the liquid crystal display device (1
In the method of displaying display data on a liquid crystal display device (13), the frame memory control unit (8) comprises a frame memory (12)
Write address generator that generates the write address of
(9), a read address generator that generates a read address of the frame memory (10), and a write address generator
The display control unit includes a frame memory access control unit (11) for writing display data to a write address generated from (9) and reading display data at a read address.
(1) is a display control unit that generates a synchronization signal with a standard cycle (2)
In addition, in the low power mode for driving the liquid crystal display device with low power, a display control unit (2 ') that generates a synchronization signal with a cycle slower than the standard cycle is provided. In the low power mode, the writing control to the frame memory is standard. A display method for a liquid crystal display device, characterized in that a sync signal having a cycle slower than the cycle is used and readout control is carried out with a sync signal having a standard cycle. 2. The low power mode setting signal according to claim 1, wherein the low power mode is set when the power supply voltage drops.
The display control unit (1) selects the display control unit (2 ') by the low power mode setting signal (4).
A display method for a liquid crystal display device, comprising: (3), wherein a display control unit (2 ') is selected based on a low power mode setting signal, and a synchronization signal having a cycle slower than a standard cycle is generated. 3. The read address generator (10) according to claim 1, wherein the write address generator (9) generates a write address in a cycle slower than a standard cycle in the low power mode.
Is a display method of a liquid crystal display device characterized in that a read address is generated at the same cycle as the standard cycle even in the low power mode.