JPH03257492A - Display system - Google Patents

Abstract

PURPOSE:To decrease the transmission frequence of display data to a half as high as a refreshment rate to reduce the power consumption by storing the display data in a frame memory through a shift resister and reading them out at a frequency twice as high as the input frequency. CONSTITUTION:In the display system which displays the display data on a display part through a driver, a timing control means 10 performs control so that a write and a read address do not conflict with each other and the display data DA and stored in the frame memory 3 through the shift register 20, read out of the frame memory 30 at the frequency twice as high as the frequency with which the display data DA are inputted, and displayed on the display part 60 through the driver 50. In this constitution, the transmission rate of the display data is set a half as high as the refreshment rate to reduce the transmission frequency to a half, thereby reducing power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a display system in which transmission signals of a display device are improved.

<Prior Art> Conventionally, CRTs and flat panel displays have generally had a refresh rate of 60 Hz in consideration of the frequency at which flicker is not felt.

Therefore, display data transmission is also performed at 60 Hz.

On the other hand, what makes a moving image display feel smooth is that around 30 Hz is practical, as can be seen in TVs with 60 Hz x 1/2 interlace and movies with 24 times per second. be.

<Problems to be Solved by the Invention> However, in the case of a 60 Hz non-interlaced display, updating display data at an update rate of 30 Hz means sending the same data twice. In recent years, the resolution of display devices has been increasing,
Since the transmission frequency is becoming higher, transmitting data twice poses a problem in that it increases cost and power consumption.

The present invention has been made in view of these problems of the conventional technology, and its purpose is to make the display data transmission rate 172 times the refresh rate (the display data transmission rate is 172 times the refresh rate). For example, set the rate to 30H
z, the refresh rate is doubled to 60 Hz), thereby providing a display system in which the transmission frequency can be halved compared to the conventional one.

Means for Solving the Problems> In order to achieve the above object, the present invention provides a display system that displays display data on a display unit via a driver, in which writing and successive addresses are controlled using timing control means. The display data is stored in a frame memory via a register means so as not to collide with each other, and the driver is then read out from the frame memory at a frequency twice the frequency at which the display data is input. The display unit is configured to display the information on the display unit via the display unit.

Function> Display data is stored in a frame memory via a shift register, read out from the frame memory at a frequency twice the frequency at which the display data is input, and displayed on a display unit via a driver.

Example Examples will be described with reference to the drawings.

FIG. 1 is a block system diagram of a specific embodiment of the display system of the present invention, FIG. 2 is a specific block circuit diagram of the display system of the present invention that further embodies FIG. 1, and FIGS. FIG. 4 is a time chart for explaining FIGS. 1 and 2.

In Figure 1, 10 indicates VSYNC (vertical synchronization signal), H8YNC (horizontal synchronization signal) and clock (CLOCK).
), 20 is a register means for serial-in/parallel-out operation, 30 is a frame memory, 40 is a register means for parallel-in/serial-out operation, 50 is a driver, 60 is the display section.

At this time, the display data D^ is stored in the frame memory 30 via the shift register 20, read out from the frame memory 40 at a frequency twice the frequency at which this display data is input, and displayed on the display unit 60 via the driver 50. be done. At this time, the timing control means 10 controls so that the writing and successive addresses do not collide. Therefore, the timing control means 10 and the register means 20 are
The circuit will look like the example shown in the figure.

In FIG. 2, the timing control means 10
, H8YNC and tarok are input to the timing control section 11. A counter 12 which inputs vsyNCI from the timing control section 11 to a reset terminal RES and inputs a timing signal to a counter terminal to generate and output a write address signal Aw. VSYN from timing control section 11
A counter 13 which inputs C2 to a reset terminal RES and also inputs a timing signal to a counter terminal to generate and output a read address signal AR. Then, it inputs the write address signal AW and the read address signal AR, selects these signals, outputs the address signal AD to the address terminal ADDR of the frame memory 30, and outputs the signal R/W for controlling read/write. It can be configured with a multiplexer 14 that outputs. Further, the register means 20 is composed of a shift register 21 and a buffer 22.
Serial data SO is led to the input clock, and after registering the serial data So, the data signal is output to the buffer 22, and the buffer 22 is connected to the multiplexer 1.
Shift 1 by read/write timing signal R/W from 4
- Read or stop the data sent from the register 21. Further, the register means 40 is constituted by a shift register, and the data from the frame memory 30 is inputted from the timing control section 11 to a timing signal (two clocks frequency: 2 clocks), and then the data is inputted to the registers 1 to 10. Data registered in the driver 50 can be output.Furthermore, in the frame memory 30, the address signal 〇 is input to the address terminal ADDR, data from the register means 20 is input to the data terminal DATA, and a memory read signal is input to the address terminal ADDR. RD and memory write signal WD are input from the timing control section 11 to respective terminals.

When configured in this way, the timing in units of frames is shown in Figure 3, and at this time, as shown in (11) in the figure, the serial data (SDATA) which is the transmission data (-human display data) VS where sD is shown in the same figure (1)
1.2.3 so that the frame changes for each YNCI.・・・
・When it is closed, the display data (read data) is "
In the second half of the transmission period of 1゛'' transmission data, 1'° is changed to ``2''.
In the first half of the transmission period of the transmission data, °゛1'° is changed again to “2”.
In the latter half of the transmission period of the transmission data of ``2'', ``2'' is read out, and the same sequence of data is read out thereafter. At this time, the address of the frame memory required to perform the writing/reading is a graph as shown in FIG.

This is because, for example, when the frame memory 30 is configured with an 8-bit wide memory, the display data is written once every 8 clocks of the transmission lock at a transmission rate of, for example, 30 Hz, and then read at that time. refresh rate 2
In order to double the frequency to 60Hz, it is necessary to repeat it twice.

FIG. 4 shows the timing. At this time, the memory read signal RD is applied twice during the period when the signal R/W controlling read/write is "H'', and the write WR is performed once during the period "L''.

<Effects of the Invention> Since the present invention is configured as described above, it produces the following effects.

The present invention transmits data transmitted from the display to 1/1/2 of the refresh rate.
By setting the frequency to 2, the transmission frequency can be reduced to 1/2 of the conventional frequency, thereby reducing the cost and power consumption of the device.

[Brief explanation of drawings]

FIG. 1 is a block system diagram of a specific embodiment of the display system of the present invention, FIG. 2 is a specific block circuit diagram of the display system of the present invention that further embodies FIG. 1, and FIGS. FIG. 4 is a time chart for explaining FIGS. 1 and 2. DESCRIPTION OF SYMBOLS 10... Timing control means, 20... Register means, 30... Frame memory, 40... Register means, 50... Driver, 60... Display unit.

Claims (1)

[Claims] In a display system that displays display data on a display unit via a driver, the display data is stored in a frame memory via register means using a timing control means to prevent write and read addresses from colliding, The display system is configured to read out the stored contents from the frame memory at a frequency twice as high as the frequency at which the display data is inputted, and display the stored contents on the display unit via the driver.