JPH053192A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable an insulating film on a solid intersection of two conductive paths to be formed thick and the conductive paths to be lessened in resistance. CONSTITUTION:An N-type epitaxial layer 3 formed on a P-type silicon substrate 1 is separated into island regions 30 and 31 by a P-type isolating region 4. N-type buried layers 2 and 21 are selectively formed spreading over the P-type silicon substrate 1 in the island regions 30 and 31 and the N-type epitaxial layer 3, and an N-type high concentration region 12 is formed in the island region 30 as linked to the buried layer 2. Electrode wiring layers 7 and 71 are formed on contact widows located on both sides of the high concentration region 12, and a wiring layer 8 is arranged on the N-type high concentration region 12 through the intermediary of a silicon oxide film 17. The silicon oxide film 17 on the high concentration region 12 is formed as thick as a silicon oxide film 10 of the N-type epitaxial layer 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides an insulating film on a first conductive path formed in a semiconductor substrate, and further forms a second conductive path on the insulating film so as to three-dimensionally intersect the two. The present invention relates to a semiconductor integrated circuit capable of preventing a surge breakdown of an insulating film in the case of being made to have a low resistance and a conductive path formed in a semiconductor substrate.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, two conductive paths often cross each other. When the two conductive paths are crossed three-dimensionally, one conductive path is formed in a silicon substrate simultaneously with the emitter of a transistor. A structure in which the two conductive paths are three-dimensionally crossed by forming a wiring layer on the silicon oxide film covering the n-type diffusion layer and forming the other conductive path on the other side is widely adopted.

FIG. 5 is a sectional view showing an example of a conventional structure of a three-dimensional intersection of two conductive paths. In this structure, a buried layer 2 is formed on a p-type single crystal silicon substrate 1, an n-type silicon epitaxial layer 3 is further grown, and then the n-type silicon epitaxial layer 3 is penetrated to reach the p-type single crystal silicon substrate 1. The p-type isolation layer 4 is formed to a depth reaching the n-type silicon epitaxial layer to form a predetermined number of island regions, and the p-type diffusion layer 5 is simultaneously formed in the step of forming the transistor base region in one of the island regions. To form p
In the step of forming the transistor emitter region in the n-type diffusion layer, the high-concentration n-type diffusion layer 6 is formed at the same time, and finally, contact windows are opened on both sides of the n-type diffusion layer 6 to form the electrode wiring layers 7 and 71. Of the n-type diffusion layer 6 on the silicon oxide film 9 located on the n-type diffusion layer 6.
It is obtained by going through the process of forming the wiring layer 8 in a relationship orthogonal to. As a result, the wiring layer 7 and the n-type diffusion layer 6
Further, a structure in which the conductive path formed by the wiring layer 71 and the conductive path formed by the wiring layer 8 are three-dimensionally intersected is obtained.

[0004]

By the way, in this structure, when the n-type diffusion layer 6 is formed, the silicon oxide film covering the silicon surface on the n-type diffusion layer 6 is removed, and in the process of forming the n-type diffusion layer 6. Since the silicon oxide film 9 is formed, n
The silicon oxide film 9 (thickness 0.1 to 0.5 μm) covering the n-type diffusion layer 6 becomes thinner than the silicon oxide film 10 (thickness about 1 μm) on the silicon epitaxial layer 3. Therefore, when a surge voltage is applied between the two conductive paths insulated by the silicon oxide film 9, the silicon oxide film 9 which insulates the two conductive layers from each other is inconveniently damaged by the surge.

The present invention is capable of eliminating the above-mentioned inconvenience, that is, the thickness of the silicon oxide film on the diffusion layer related to the three-dimensional intersection of two conductive paths is less likely to cause surge breakdown. (EN) Provided is a semiconductor integrated circuit which can have a thickness and can reduce the resistance value of a semiconductor formed in a silicon substrate.

[0006]

According to the semiconductor integrated circuit of the present invention, an epitaxial layer of opposite conductivity type formed on a silicon substrate of one conductivity type is separately formed in a plurality of island regions. A buried layer having a reverse conductivity type is selectively formed over the substrate and the epitaxial layer, and a high concentration region having a reverse conductivity type and having a higher concentration than the epitaxial layer is formed in the buried layer in at least one of the island regions. Electrodes are formed in contact windows on both sides of the high concentration region, a wiring layer is formed on the high concentration region via an insulating film, and the insulating film on the high concentration region is epitaxially formed. It has the same film thickness as the insulating film on the layer.

[0007]

According to this structure, since the cross wiring is formed by using both the high-concentration region and the buried layer, the resistance value can be reduced and the thickness of the insulating film between two intersecting conductive paths can be reduced. Since it is thick, this insulating film can be protected from surge damage or the like.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A cross-sectional view of one embodiment of the semiconductor integrated circuit of the present invention is shown on the left side of FIG.

In this structure, the n-type silicon epitaxial layer 3 formed on the p-type single crystal silicon substrate 1 is p-type.
Is separated into island regions 30 and 31 by the p-type isolation region 4 reaching the p-type single crystal silicon substrate 1, and n is formed across the p-type single crystal silicon substrate 1 and the n-type silicon epitaxial layer 3.
Shaped buried layers 2 and 21 are selectively formed to form island regions 30.
An n-type high-concentration region 12 is connected to the buried layer 2, and electrode wiring layers 7 and 71 are formed in contact windows on both sides of the high-concentration region 12. And the wiring layer 8 is formed via the silicon oxide film 17, and the silicon oxide film 17 on the high concentration region 12 is formed on the n-type silicon epitaxial layer 3.
It has the same film thickness as.

Next, a manufacturing method for obtaining the above structure will be specifically described with reference to process sectional views of FIGS.

First, in the p-type single crystal silicon substrate 1,
Using the silicon oxide film as a mask, antimony (Sb) or arsenic (As) is selectively doped by the spin-on method, the ion implantation method, or the encapsulation method to form the n-type buried layers 2 and 21, and then the silicon oxide film on the surface. Are removed, and the specific resistance is continuously 0.5 to 5 over the entire surface.
0.5-10 n-type silicon epitaxial layer 3 of Ωcm
Grow to a thickness of μm. Then, a silicon oxide film 11 having a thickness of 0.3 to 2 μm is formed on the entire surface of the n-type silicon epitaxial layer 3. The exposed n-type silicon epitaxial layer 3 is formed by selectively removing the silicon oxide film 11 so as to surround the n-type buried layers 2 and 21.
Then, a p-type isolation region 4 is formed by doping boron (B) by a thermal diffusion method or an ion implantation method, and the n-type silicon epitaxial layer 3 is separated into island regions 30 and 31 (FIG. 2).

Next, n forming a three-dimensional intersection of the conductive paths.
The silicon oxide film 11 on almost the entire area of the island region 30 of the silicon epitaxial layer and a part of the surface of the island region 31 of the n-type silicon epitaxial layer forming a transistor is removed, and phosphorus () is formed by a thermal diffusion method or an ion implantation method. P) is doped and phosphorus is diffused to a depth reaching the n-type buried layers 2 and 21 to form high-concentration n-type regions 12 and 13. The high-concentration n-type region 13 is a collector wall diffusion region connected to the n-type buried layer 21 during transistor formation (FIG. 3).

Next, after all the silicon oxide film 11 is removed, a silicon oxide film 10 having a thickness of 0.8 to 2 μm is newly formed on the surface. Then, the base region 14 and the emitter region 15 are formed in the island region 31 of the n-type silicon epitaxial layer for forming a transistor. In this process, a difference occurs in the silicon oxide film (FIG. 4).

Thereafter, contact windows are formed on both sides of the high-concentration n-type region 12 and in the high-concentration n-type region 13 serving as the emitter region 15, the base region 14, and the collector region of the transistor, and the contact portion and the high-concentration n-type region are formed. On the silicon oxide film 17 covering the region 12, high-purity aluminum (A
l) Alternatively, as shown in FIG. 1, the electrode wiring layers 7, 71, 16 and the wiring layer 8 are formed by using aluminum containing silicon in an amount of 1 to 2% by weight. A semiconductor integrated circuit having a structure in which the first conductive path formed by the shaped region 12 and the electrode wiring layer 71 and the second conductive path formed by the wiring layer 8 are insulated by the thick silicon oxide film 17 and intersect with each other is formed. To be done.

[0015]

According to the present invention, the first conductive path formed by utilizing the diffusion layer in the silicon substrate and the second conductive path formed by the wiring layer located above the diffusion layer. And the thickness of the insulating film that insulates the two is equal to the thickness of the insulating film that covers the n-type silicon epitaxial layer.
Since it is much thicker than the insulating film formed by the conventional structure, it is effective in eliminating the problem of breakdown due to surge voltage.

Further, since the diffusion layer forming the conductive path is formed by burying the high concentration region, the impurity concentration is high and the diffusion depth is deep, so that the sheet resistance is 5 to 15.
Ω / □, and the effect of realizing an intersection where the resistance value of the conductive path is lower than that of the conventional structure in which the emitter diffusion layer having a sheet resistance of 15 to 20 Ω / □ is used as the conductive path.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a three-dimensional intersection of two conductive paths and a transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process for obtaining the structure of the present invention.

FIG. 3 is a sectional view of a manufacturing process for obtaining the structure of the present invention.

FIG. 4 is a sectional view of a manufacturing process for obtaining the structure of the present invention.

FIG. 5 is a cross-sectional structure diagram of a three-dimensional intersection of two conventional conductive paths using a conventional emitter diffusion layer as a conductive path.

[Explanation of symbols]

 1 p-type single crystal silicon substrate 2,21 n-type buried layer 3 n-type silicon epitaxial layer 4 p-type isolation region 5 p-type diffusion layer 6 n-type diffusion layer 7,71 electrode wiring layer 8 wiring layer 9 n-type diffusion layer Upper silicon oxide film 10 Silicon oxide film on n-type epitaxial layer 11 Silicon oxide film 12 High concentration n-type region 13 High concentration n-type region (collector wall) 14 Base region 15 Emitter region 16 Transistor electrode 17 On high concentration region Oxide silicon film 30, 31 Island region

Claims (1)

Claims: What is claimed is: 1. An epitaxial layer of opposite conductivity type formed on a silicon substrate of one conductivity type is separately formed into a plurality of island regions, and is formed on the silicon substrate and the epitaxial layer in the first half. A buried layer of opposite conductivity type is selectively formed over
A high-concentration region having a reverse conductivity type and a concentration higher than that of the epitaxial layer is formed in at least one of the island regions so as to be connected to the buried layer, and electrodes are formed in contact windows on both sides of the high-concentration region at the same height. A wiring layer is formed on the concentration region via an insulating film, and the insulating film on the high concentration region has the same thickness as the insulating film on the epitaxial layer.