JPH05315754A - Forming method for circuit on low temperature baked ceramic multilayer circuit board - Google Patents
Forming method for circuit on low temperature baked ceramic multilayer circuit boardInfo
- Publication number
- JPH05315754A JPH05315754A JP4142185A JP14218592A JPH05315754A JP H05315754 A JPH05315754 A JP H05315754A JP 4142185 A JP4142185 A JP 4142185A JP 14218592 A JP14218592 A JP 14218592A JP H05315754 A JPH05315754 A JP H05315754A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- ceramic multilayer
- low temperature
- paste
- baked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000000919 ceramic Substances 0.000 title claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 36
- 238000007650 screen-printing Methods 0.000 claims abstract description 8
- 238000010304 firing Methods 0.000 claims description 15
- 239000003990 capacitor Substances 0.000 claims description 11
- 238000000206 photolithography Methods 0.000 claims description 8
- 238000001035 drying Methods 0.000 claims description 5
- 239000012298 atmosphere Substances 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 description 13
- 239000007864 aqueous solution Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M sodium hydroxide Inorganic materials [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 238000007606 doctor blade method Methods 0.000 description 2
- 238000007731 hot pressing Methods 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000005554 pickling Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、低温焼成セラミック多
層配線基板上に、Ｃｕ導体を高密度に回路形成させる方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a circuit of Cu conductors on a low temperature fired ceramic multilayer wiring board at high density.
【０００２】低温焼成セラミック多層配線基板上に、Ｃ
ｕ導体を形成する方法は公知である。その代表的な方法
は、内部配線にＡｇ系導体を使用したセラミックグリー
ンシートを積層し、低温焼成して得た基板表面にＣｕペ
ーストを所定の配線パターンになるようにスクリーン印
刷し、乾燥したのち、非酸化雰囲気中、基板焼成温度以
下で再び焼成することにより、外部Ｃｕ導体の回路基板
を製造していた（特開昭６２−２６５７９６）。また、
外部Ｃｕ導体をフォトリソグラフィ技術を利用して配線
パターンに形成する方法も知られている。たとえば、グ
リーンシートを低温焼成して得た基板表面を酸性液で粗
化し、触媒付与し、次いで無電解Ｃｕめっき、その上に
さらに電界めっきを施したのち、所定の配線パターンに
なるように、フォトリソグラフィ技術によってＣｕ導体
を形成させる方法がある（特開平１−１７３６９７）。On a low temperature fired ceramic multilayer wiring board, C
Methods of forming u conductors are known. A typical method is to stack a ceramic green sheet using an Ag-based conductor on the internal wiring, screen print a Cu paste on the surface of the substrate obtained by low-temperature firing so as to form a predetermined wiring pattern, and then dry. A circuit board having an external Cu conductor was manufactured by firing again in a non-oxidizing atmosphere at a temperature not higher than the firing temperature of the board (JP-A-62-265796). Also,
A method of forming an external Cu conductor in a wiring pattern using a photolithography technique is also known. For example, the substrate surface obtained by firing the green sheet at a low temperature is roughened with an acid solution, a catalyst is applied, electroless Cu plating is then performed, and then electric field plating is further applied thereto, so that a predetermined wiring pattern is obtained. There is a method of forming a Cu conductor by a photolithography technique (Japanese Patent Laid-Open No. 1-173697).
【０００３】[0003]
【発明が解決しようとする課題】前記の従来によっても
Ｃｕ配線パターンは形成できる。しかし、スクリーン印
刷法によると、Ｃｕ導体の線間隔・線幅を最小になるよ
うに努力しても、せいぜい７５μｍ止りであり、それ以
下に線間隔を小さくし、表面配線密度を高めることはで
きない。一方、フォトリソグラフィ技術を利用する方法
は、Ｃｕめっき技術を併用する点に特徴を有するが、そ
のために、基板表面を酸洗いする粗面化工程、Ｃｕめっ
きの付着を強固にするための触媒付与工程など、複雑な
前処理工程を欠かすことができない。このように、従来
の方法はいずれも欠点を有していた。The Cu wiring pattern can be formed by the above-mentioned conventional method. However, according to the screen printing method, even if efforts are made to minimize the line spacing and line width of the Cu conductor, the line spacing is at most 75 μm, and it is not possible to reduce the line spacing below that and increase the surface wiring density. .. On the other hand, the method using the photolithography technique is characterized in that the Cu plating technique is used in combination, but for that reason, a roughening step of pickling the surface of the substrate and a catalyst addition for strengthening the adhesion of the Cu plating are performed. Intricate pretreatment processes such as processes are indispensable. As described above, all the conventional methods have drawbacks.
【０００４】[0004]
【課題を解決するための手段】本発明者らは、より簡易
な工程で、Ｃｕ導体の線間隔・線幅の狭小化を目的とし
て開発を重ねた結果、意外にも最も卑近な技術を組合わ
せた方法が最適であることを知見して、本発明を完成さ
せた。The inventors of the present invention have surprisingly developed the most popular technique as a result of repeated development for the purpose of narrowing the line spacing and line width of Cu conductors in a simpler process. The present invention has been completed by finding that the combined method is optimal.
【０００５】すなわち本発明は、内部にＡｇ系導体を形
成したセラミックグリーンシートを低温焼成して得た基
板表面に、スクリーン印刷法でＣｕペーストを印刷し、
乾燥し、およそ６００℃〜７５０℃程度の低温で焼成し
たのち、フォトリソグラフィ技術を用いて配線パターン
を形成する低温焼成セラミック多層配線基板への回路形
成方法を提供するものである。That is, according to the present invention, a Cu paste is printed by a screen printing method on the surface of a substrate obtained by firing a ceramic green sheet having an Ag conductor formed therein at a low temperature.
The present invention provides a method for forming a circuit on a low-temperature fired ceramic multilayer wiring board, which comprises drying and firing at a low temperature of about 600 ° C. to 750 ° C., and then forming a wiring pattern using a photolithography technique.
【０００６】本発明の最大の特徴は、スクリーン印刷法
とフォトリソグラフィ技術とを組合わせた点にあり、こ
れによってＣｕ導体の線間隔を従来より大幅に狭くする
ことができる。The greatest feature of the present invention lies in the combination of the screen printing method and the photolithography technique, whereby the line spacing of the Cu conductor can be made narrower than ever before.
【０００７】スクリーン印刷法およびそれに用いるＣｕ
ペーストは、本発明では慣用の手段や市販のペーストを
採用することができ、特に限定されない。Screen printing method and Cu used therefor
In the present invention, the paste may be a conventional means or a commercially available paste and is not particularly limited.
【０００８】スクリーン印刷法で印刷し乾燥されたＣｕ
ペーストは、６００℃〜７５０℃で低温焼成されるの
で、基板表面にＣｕ厚膜として密着する。焼成温度が６
００℃以下では基板との密着強度が低下し、７５０℃以
上ではＡｇ系導体へのＣｕ導体の拡散が顕著になり、接
続不良が発生する。このように本発明は、印刷・乾燥・
焼成という単純な工程でＣｕ導体を基板上に形成した
後、フォトリソグラフィ技術を用いて配線パターンを形
成するといった比較的簡易な方法で、低温焼成セラミッ
ク多層配線基板上へＣｕ導体配線パターンを形成するこ
とができる。Cu printed and dried by screen printing
Since the paste is fired at a low temperature of 600 ° C. to 750 ° C., it adheres to the surface of the substrate as a Cu thick film. Firing temperature is 6
If the temperature is 00 ° C. or lower, the adhesion strength with the substrate decreases, and if the temperature is 750 ° C. or higher, the diffusion of the Cu conductor into the Ag-based conductor becomes remarkable, resulting in defective connection. As described above, the present invention is capable of printing, drying,
The Cu conductor wiring pattern is formed on the low temperature fired ceramic multilayer wiring board by a relatively simple method of forming the Cu conductor on the substrate by a simple process of firing and then forming the wiring pattern by using the photolithography technique. be able to.
【０００９】本発明によれば、フォトリソグラフィ技術
によって、配線パターンの線間隔を３０μｍ程度まで狭
小にすることができるため、従来法に比べ、線間隔で約
２／５にすることができ、したがって表面配線密度の向
上を著しく高めることができる。According to the present invention, the line spacing of the wiring pattern can be narrowed down to about 30 μm by the photolithography technique, so that the line spacing can be reduced to about 2/5 as compared with the conventional method. It is possible to remarkably improve the surface wiring density.
【００１０】[0010]
【実施例】実施例１ アルミナーホウケイ酸鉛ガラス（５０−５０重量％）を
主成分としたセラミックグリーンシート（日本セメント
社製）をドクターブレード法により作製したのち、一定
の大きさに裁断し、さらにパンチングによってグリーン
シートの所定箇所にスルーホールを形成する。スルーホ
ール充填用Ａｇペースト（６１４１Ｄ：デュポンジャパ
ン社製）および内部配線用Ａｇペースト（ＮＡＧ−２０
２：日本セメント社製）をそれぞれスクリーン印刷し、
それらのグリーンシートを積層し、熱プレスにより一体
化する。この積層体を、空気中で８５０℃、１０分間保
持して焼成し、図１に示す低温焼成セラミック多層配線
基板１を得る。図中２はスルーホール充填Ａｇ導体、３
は内部配線Ａｇ導体である。焼成基板１の表面の所定箇
所に、厚膜Ｃｕペース（ＱＳ１９０：デュポンジャパン
社製）をスクリーン印刷し、１２０℃で１０分間乾燥
後、窒素雰囲気中、６００℃、５分間保持して焼成し、
厚膜Ｃｕ導体を形成する。この時の厚膜Ｃｕ導体の焼成
膜厚は１５〜２０μｍである。次に、基板表面全体にア
ルカリ現像タイプのフォトレジストドライフィルム（Ｐ
ＨＴ−８８７Ａ−２５：日立化成工業社製）をラミネー
トし、フォトマスクを介して照射量４０ミリジュールの
紫外線照射によりパターン露光を行う。さらに１ｗｔ％
−Ｎａ2 ＣＯ3 水溶液にてレジストの現像を行い、室温
乾燥後、露出した厚膜Ｃｕ導体を３５〜４０ｗｔ％の塩
化第二鉄水溶液でエッチングする。最後に、不要のフォ
トレジストを２．５ｗｔ％−ＮａＯＨ水溶液にて除去
し、所要の厚膜Ｃｕ導体パターン４を低温焼成セラミッ
ク多層配線基板１の表面に形成する。上記の実施例に基
づいて形成された厚膜Ｃｕ導体の線間隔および線幅は、
共に３０μｍであり、微細化が可能となり、低温焼成セ
ラミック多層配線基板の外部Ｃｕ配線の高密度化が図れ
た。Example 1 A ceramic green sheet (manufactured by Nippon Cement Co., Ltd.) containing alumina-lead borosilicate glass (50-50% by weight) as a main component was prepared by a doctor blade method and then cut into a certain size. Further, through holes are formed at predetermined locations on the green sheet by punching. Through-hole filling Ag paste (6141D: manufactured by DuPont Japan) and internal wiring Ag paste (NAG-20).
2: screened by Nippon Cement Co., Ltd.,
The green sheets are laminated and integrated by hot pressing. This laminated body is held in air at 850 ° C. for 10 minutes and fired to obtain the low temperature fired ceramic multilayer wiring board 1 shown in FIG. In the figure, 2 is a through-hole filled Ag conductor, 3
Is an internal wiring Ag conductor. Thick film Cu pace (QS190: manufactured by DuPont Japan) was screen-printed on a predetermined portion of the surface of the baked substrate 1, dried at 120 ° C. for 10 minutes, and then baked at 600 ° C. for 5 minutes in a nitrogen atmosphere, and baked.
A thick film Cu conductor is formed. The firing film thickness of the thick Cu conductor at this time is 15 to 20 μm. Then, an alkali development type photoresist dry film (P
HT-887A-25 (manufactured by Hitachi Chemical Co., Ltd.) is laminated, and pattern exposure is performed by irradiating an ultraviolet ray having an irradiation amount of 40 millijoules through a photomask. 1 wt%
-Na 2 CO 3 performs resist development with an aqueous solution, after drying at room temperature to etch the exposed thick Cu conductors 35～40Wt% ferric chloride aqueous solution. Finally, the unnecessary photoresist is removed with a 2.5 wt% -NaOH aqueous solution, and the required thick film Cu conductor pattern 4 is formed on the surface of the low temperature fired ceramic multilayer wiring substrate 1. The line spacing and line width of the thick film Cu conductor formed based on the above-mentioned embodiment are
Both are 30 μm, which enables miniaturization, and the external Cu wiring of the low temperature fired ceramic multilayer wiring board can be densified.
【００１１】実施例２ アルミナ−ホウケイ酸鉛ガラス（５０−５０重量％）を
主成分としたセラミックグリーンシート（日本セメント
社製）をドクターブレード法により作製した後、一定の
大きさに裁断し、さらにパンチングによってグリーンシ
ートの所定箇所にスルーホールを形成する。スルーホー
ル充填用Ａｇペースト（６１４１Ｄ：デュポンジャパン
社製）、内部配線用Ａｇペースト（ＮＡＧ−２０２：日
本セメント社製）および鉛ペロブスカイト系の誘電体ペ
ースト（ＣＦＡ−５０１：日本セメント社製）をそれぞ
れスクリーン印刷し、それらのグリーンシートを積層
し、熱プレスにより一体化する。そのさい、一枚のグリ
ーンシート内にコンデンサを内蔵させる。この積層体
を、空気中で８５０℃、１０分間保持して焼成し、図２
に示すようにコンデンサを内蔵した低温焼成セラミック
多層配線基板１０を得る。図中、１１はコンデンサ、１
２はコンデンサ用Ａｇ電極である。コンデンサを内蔵し
た低温焼成セラミック多層配線基板１０の表面上の所定
箇所に、厚膜Ｃｕペースト（ＱＳ１９０：デュポンジャ
パン社製）をスクリーン印刷し、１２０℃で１０分間乾
燥後、窒素雰囲気中、６００℃、５分間保持の条件で焼
成を行い、厚膜Ｃｕ導体を形成した。この時の厚膜Ｃｕ
導体の焼成膜厚は１５〜２０μｍである。次に、基板表
面全体にアルカリ現像タイプのフォトレジストドライフ
ィルム（ＰＨＴ−８８７Ａ−２５：日立化成工業社製）
をラミネート形成し、フォトマスクを介して照射量４０
ミリジュールの紫外線照射によりパターン露光を行った
のち、１ｗｔ％−Ｎａ2 ＣＯ3 水溶液にて現像し、室温
乾燥後、露出した厚膜Ｃｕ導体を３５〜４０ｗｔ％の塩
化第二鉄水溶液にてエッチングする。最後に、不要のフ
ォトレジストを２．５ｗｔ％−ＮａＯＨ水溶液にて除去
し、所要の厚膜Ｃｕ導体パターン４がコンデンサを内蔵
した低温焼成セラミック多層配線基板の表面に形成でき
る。上記の実施例に基づいて形成された厚膜Ｃｕ導体の
線間隔および線幅は、実施例１と同様の３０μｍの微細
化が可能となり、コンデンサを内蔵した低温焼成セラミ
ック多層配線基板の外部Ｃｕ配線の高密度化が図れた。Example 2 A ceramic green sheet (manufactured by Nippon Cement Co., Ltd.) containing alumina-lead borosilicate glass (50-50% by weight) as a main component was prepared by the doctor blade method, and then cut into a certain size. Furthermore, through holes are formed at predetermined locations on the green sheet by punching. Through-hole filling Ag paste (6141D: manufactured by DuPont Japan), internal wiring Ag paste (NAG-202: manufactured by Nippon Cement Co., Ltd.), and lead perovskite-based dielectric paste (CFA-501: manufactured by Nippon Cement Co., Ltd.), respectively. Screen printing is performed, the green sheets are laminated, and integrated by hot pressing. At that time, a capacitor is built in one green sheet. This laminate was held in air at 850 ° C. for 10 minutes for firing,
As shown in (1), a low temperature fired ceramic multilayer wiring board 10 having a built-in capacitor is obtained. In the figure, 11 is a capacitor, 1
2 is an Ag electrode for capacitors. A thick film Cu paste (QS190: made by DuPont Japan) is screen-printed on a predetermined location on the surface of the low temperature fired ceramic multilayer wiring substrate 10 having a built-in capacitor, dried at 120 ° C. for 10 minutes, and then 600 ° C. in a nitrogen atmosphere. Firing was performed under the condition of holding for 5 minutes to form a thick film Cu conductor. Thick film Cu at this time
The firing film thickness of the conductor is 15 to 20 μm. Next, an alkali development type photoresist dry film (PHT-887A-25: manufactured by Hitachi Chemical Co., Ltd.) is formed on the entire surface of the substrate.
Is laminated and the irradiation dose is 40
After pattern exposure by irradiation of millijoules of ultraviolet rays, development was performed with a 1 wt% -Na 2 CO 3 aqueous solution, and after drying at room temperature, the exposed thick film Cu conductor was etched with a 35-40 wt% ferric chloride aqueous solution. To do. Finally, unnecessary photoresist is removed with a 2.5 wt% -NaOH aqueous solution, and the required thick-film Cu conductor pattern 4 can be formed on the surface of the low-temperature fired ceramic multilayer wiring board containing the capacitor. The line spacing and line width of the thick film Cu conductor formed based on the above-described embodiment can be miniaturized to 30 μm as in the case of the first embodiment, and the external Cu wiring of the low temperature firing ceramic multilayer wiring board with the built-in capacitor can be achieved. Higher density was achieved.
【００１２】[0012]
【発明の効果】本発明の方法によれば、簡易な工程によ
って、低温焼成セラミック多層配線基板上にＣｕ導体回
路を極めて高密度に形成することができる。According to the method of the present invention, Cu conductor circuits can be formed in extremely high density on a low temperature fired ceramic multilayer wiring substrate by a simple process.
【図１】図１は本発明基板の実施例１に関する断面図で
ある。FIG. 1 is a sectional view of a first embodiment of a substrate of the present invention.
【図２】図２は実施例２の断面図である。FIG. 2 is a sectional view of a second embodiment.
１ 低温焼成セラミック多層配線基板 ２ スルーホール充填Ａｇ導体 ３ 内部配線Ａｇ導体 ４ 厚膜Ｃｕ導体パターン １０ コンデンサ内蔵低温焼成セラミック多層配線基板 １１ コンデンサ １２ コンデンサ用Ａｇ電極 1 Low-Temperature Ceramic Multilayer Wiring Board 2 Through Hole Filling Ag Conductor 3 Internal Wiring Ag Conductor 4 Thick Film Cu Conductor Pattern 10 Low Temperature Firing Ceramic Multilayer Wiring Board with Built-in Capacitor 11 Capacitor 12 Capacitor Ag Electrode
フロントページの続き (72)発明者 菅野 修 東京都江東区清澄１−２−23 日本セメン ト株式会社中央研究所内Front Page Continuation (72) Inventor Osamu Kanno 1-2-23, Kiyosumi, Koto-ku, Tokyo Inside of Central Research Institute, Nippon Cement Co., Ltd.
Claims (2)
ック多層配線基板の表面にＣｕ導体回路を形成する方法
において、該表面にＣｕペーストをスクリーン印刷し、
乾燥し、非酸化雰囲気において６００℃〜７５０℃で焼
成したのち、フォトリソグラフィ技術を用いてＣｕ導体
回路のパターニングを行なうことを特徴とする低温焼成
セラミック多層配線基板の回路形成方法。1. A method for forming a Cu conductor circuit on the surface of a low-temperature fired ceramic multilayer wiring board having an Ag-based internal conductor, screen-printing a Cu paste on the surface,
A method for forming a circuit for a low-temperature-fired ceramic multilayer wiring board, which comprises drying and firing at 600 ° C. to 750 ° C. in a non-oxidizing atmosphere, and then patterning a Cu conductor circuit using a photolithography technique.
内部に、コンデンサを形成したことを特徴とする請求項
１に記載の低温焼成セラミック多層配線基板の回路形成
方法。2. The method for forming a circuit of a low temperature fired ceramic multilayer wiring board according to claim 1, wherein a capacitor is formed inside the low temperature fired ceramic multilayer wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4142185A JPH05315754A (en) | 1992-05-07 | 1992-05-07 | Forming method for circuit on low temperature baked ceramic multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4142185A JPH05315754A (en) | 1992-05-07 | 1992-05-07 | Forming method for circuit on low temperature baked ceramic multilayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05315754A true JPH05315754A (en) | 1993-11-26 |
Family
ID=15309361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4142185A Pending JPH05315754A (en) | 1992-05-07 | 1992-05-07 | Forming method for circuit on low temperature baked ceramic multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05315754A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6521069B1 (en) * | 1999-01-27 | 2003-02-18 | Matsushita Electric Industrial Co., Ltd. | Green sheet and manufacturing method thereof, manufacturing method of multi-layer wiring board, and manufacturing method of double-sided wiring board |
| JP2011044683A (en) * | 2009-08-24 | 2011-03-03 | Samsung Electro-Mechanics Co Ltd | Ceramic substrate, and manufacturing method therefor |
-
1992
- 1992-05-07 JP JP4142185A patent/JPH05315754A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6521069B1 (en) * | 1999-01-27 | 2003-02-18 | Matsushita Electric Industrial Co., Ltd. | Green sheet and manufacturing method thereof, manufacturing method of multi-layer wiring board, and manufacturing method of double-sided wiring board |
| US6696139B2 (en) | 1999-01-27 | 2004-02-24 | Matsushita Electric Industrial Co., Ltd. | Green sheet and manufacturing method thereof, manufacturing method of multi-layer wiring board and manufacturing method of double-sided wiring board |
| JP2011044683A (en) * | 2009-08-24 | 2011-03-03 | Samsung Electro-Mechanics Co Ltd | Ceramic substrate, and manufacturing method therefor |
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