JPH05315607A - Field-effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To realize a field effect transistor equipped with a gate electrode having the gate length reduced by forming the gate electrode in such a manner that the gate electrode is extended above a trapezoidal insulation film from the surface of an active layer along a slope. CONSTITUTION:A resist pattern 7 is formed on an active layer 2 on the main surface of semiconductor substrate 1, subjected to etching and a recess 8 is formed, the resist pattern is melted and removed, and an insulation film 6 is formed to flat with the thickness of 0.3 to 0.5mum from the bottom surface 8a of the recess 8. Then, a resist is applied over it, a resist pattern 9 is used as mask, an opening 6a is formed by anisotropy dry etching from a diagonal direction, a metal 10 for forming a gate electrode is subjected to vapor deposition, and a gate electrode 5a is formed and extended to the upper portion of the insulation film 6 along a sloped surface 6b from the bottom surface 8a of the recess. And the unnecessary metal 10, pattern 9 and insulation film 6 are removed, and source and drain electrodes 3 and 4 are formed, by which a field effect transistor with excellent high frequency characteristics can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly to improvement of a gate electrode structure.

[0002]

2. Description of the Related Art Generally, in order to improve the performance of a field effect transistor applied to a high frequency signal, it is common to shorten the gate length (Lg) of the gate electrode.

FIG. 5 is a cross-sectional view showing a step of forming a gate electrode in a manufacturing process of a field effect transistor having a conventional recess type gate electrode, for example, in which 1 is a semiconductor substrate and 2 is an active layer. Layers, 5 is a gate electrode,
8 is a recess, 9 is a resist pattern, 10 is a gate metal, Lg is a gate length, and W is an opening width of an opening portion of the resist pattern 9.

In this gate electrode forming step, in order to shorten the gate length (Lg) of the gate electrode 5, a resist having an opening so that the opening width (W) of the opening is as small as possible. The pattern 9 is formed on the active layer 2, and then the gate metal 10 is deposited on the entire surface of the substrate 1 to form the gate electrode 5.

[0005]

However, it is not easy to reduce the opening width (W) of the opening portion of the resist pattern 9 in the conventional gate electrode forming step, and the opening portion of the opening portion is not easily formed. There is a limit to the reduction of the opening width (W), and there is a problem that the gate electrode 5 having a sufficiently short gate length (Lg) cannot be formed on the active layer 2 in a stable and reproducible manner. It was

In the above step, that is, when the opening width (W) of the opening of the resist pattern 9 is made as small as possible and the gate metal 10 is deposited on the entire surface of the substrate 1 to form the gate electrode 5. As shown in the figure, the gate metal 1 is usually formed so that the shape of the gate electrode 5 is trapezoidal (triangular).
Since 0 is vapor-deposited, the cross-sectional area [height in the direction perpendicular to the gate length (Lg) in the figure] of the gate electrode 5 is limited by the width (W) of the opening of the resist pattern 9. However, when the width (W) of the opening of the resist pattern 9 is reduced, the cross-sectional area of the gate electrode 5 is also reduced, and the gate resistance (Rg) is increased.

The present invention has been made in order to solve the above problems, and the gate length (Lg) is significantly shortened as compared with the conventional one, and the increase of the gate resistance (Rg) is suppressed. It is an object of the present invention to provide a field effect transistor having a gate electrode and a manufacturing method capable of manufacturing the field effect transistor with good reproducibility.

[0008]

In the field effect transistor according to the present invention, the gate electrode is formed from the surface of the active layer along the slope of the trapezoidal insulating film formed in a predetermined region of the active layer. It is formed so as to extend above the shape insulating film.

Further, in the field effect transistor according to the present invention, a recess is formed in a predetermined region of the active layer, and the gate electrode and the trapezoidal insulating film are formed in the recess.

Further, in the field effect transistor according to the present invention, a recess having a two-step structure is formed in a predetermined region of the active layer, and the gate electrode and the trapezoidal insulating film are provided on the source side of the recess having the two-step structure. It was formed.

Further, according to the method of manufacturing a field effect transistor of the present invention, an insulating film having a flat surface is formed on an active layer, and the insulating film is subjected to anisotropic etching from an oblique direction. After forming an opening reaching from the surface to the surface of the active layer, a gate metal is deposited along the inclined surface of the opening so as to extend from the surface of the active layer to above the insulating film. It is a thing.

Further, in the method for manufacturing a field effect transistor of the present invention, after forming a recess in a predetermined region of the active layer, the opening portion of the insulating film formed on the recess is inclined in the same manner as above. The gate metal is vapor-deposited so as to extend along the surface from the bottom surface of the recess to above the insulating film.

Further, in the method for manufacturing a field effect transistor of the present invention, after forming a recess in a predetermined region of the active layer, the insulating film formed on the recess is processed from the source side in the same manner as above. Anisotropic etching is performed in an oblique direction to form an opening from the surface of the insulating film to the center of the bottom surface of the recess, and then the insulating film in which the opening is formed is used as a mask for the recess. After etching the central portion to form the recess into a two-step structure recess, a gate is formed along the inclined surface of the opening of the insulating film from the bottom surface of the two-step structure recess toward the upper side of the insulating film. The metal is vapor-deposited.

[0014]

In the present invention, the surface of the insulating film whose surface is flattened is aligned with the inclined surface of the opening of the insulating film in which the opening is formed obliquely from the surface of the active layer to the surface of the active layer. In addition, since the gate metal is vapor-deposited so as to extend above the insulating film, the gate length (Lg) of the gate electrode obtained with respect to the opening width of the mask pattern for vapor-depositing the gate metal is obtained as compared with the conventional case. Can be reduced, and the cross-sectional area of the gate electrode can be increased by the amount that it extends above the insulating film. As a result, the gate resistance (Rg) is increased as the gate length (Lg) of the gate electrode is shortened. Can be suppressed. Moreover, since the trapezoidal insulating film is provided along the side portion below the gate electrode, the strength of the gate electrode is also improved.

Further, in the present invention, the gate electrode is formed so as to have a so-called offset gate structure in which the gate electrode is close to the source side in the recess of the active layer, so that the gate-source resistance (Rs) is reduced. In addition, high breakdown voltage can be achieved.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing the structure of a field effect transistor according to the first embodiment of the present invention.
The same reference numerals as those in FIG. 5 denote the same or corresponding portions, 3 is a source electrode, 4 is a drain electrode, 5a is a gate electrode, and 6
c is a trapezoidal insulating film, 6b is an inclined surface, and 8a is a bottom surface of the recess.

As shown in the figure, the gate electrode 5a of the field-effect transistor is formed from the bottom surface 8a of the recess 8 along the slope of the vertically long trapezoidal insulating film 6c provided in a predetermined portion of the recess 8. It is formed in a structure extending above the insulating film 6c.

FIG. 2 is a cross-sectional view showing the manufacturing process of the field-effect transistor shown in FIG. 1, in which the same reference numerals as those in FIG. 1 designate the same or corresponding parts.
6 is an insulating film made of a SiN film or the like, 6a is an opening portion, 7, 9
Is a resist pattern.

The manufacturing process will be described below with reference to FIG. First, as shown in FIG. 2A, a resist pattern 7 having an opening having a predetermined width is formed on the active layer 2 provided on one main surface of the semiconductor substrate 1. Next, using the resist pattern 7 as a mask, as shown in FIG.
The active layer 2 on the semiconductor substrate 1 is etched using, for example, a phosphoric acid-based or sulfuric acid-based etching agent, and the active layer 2 has a width of 1.0 to 1.3 μm, for example.
m, the recess 8 having a depth of 0.2 to 0.3 μm is formed. Next, after the resist pattern 7 is dissolved and removed by using an etching agent such as acetone, as shown in FIG. 2 (c), the active layer 2 is covered with, for example, ECR plasma CV.
Using D, the insulating film 6 made of a SiN film is formed so that the surface thereof is flat so that the thickness of the recess 8 from the bottom surface 8a is, for example, 0.3 to 0.5 μm. Next, a resist having a thickness of about 0.5 μm is applied on the insulating film 6, and then, as shown in FIG. 2 (d), the opening width is reduced by using ordinary photoengraving and etching techniques. 0.5 μm
A resist pattern 9 having approximately openings is formed.
Next, using the resist pattern 9 as a mask, anisotropic dry etching such as ion beam etching is performed on the insulating film 6 from an oblique direction with respect to the surface of the insulating film 6, as shown in FIG. As shown in FIG. 5, the insulating film 6 forms an opening 6a in which the insulating film 6 is engraved in an oblique direction. Then, in this state, a metal 10 for forming a gate electrode such as Ti / Pt / Au, WSi, Ti / Mo / Al is vacuum-deposited on the entire surface of the semiconductor substrate 1 as shown in FIG.
As shown in FIG. 5, the gate electrode 5a is formed by depositing the metal 10 for forming the gate electrode so as to extend from the bottom surface 8a of the recess along the inclined surface 6b on one side of the opening 6a of the insulating film 6 to the upper portion of the insulating film 6. Is formed. Next, the unnecessary gate electrode forming metal 10 and the resist pattern 9 are removed using acetone or the like, and further, the insulating film 6 is removed by dry etching, and then a source and a source are formed at predetermined positions of the active layer 2. When the drain electrodes 3 and 4 are formed, as shown in FIG. 2 (g), from the bottom surface 8a of the recess 8 to the base along the slope 6b of the vertically long trapezoidal insulating film 6c arranged at a predetermined position of the recess 8. A field effect transistor having the gate electrode 5a formed so as to extend above the shaped insulating film 6c is obtained.

In the step of forming the gate electrode according to the present embodiment as described above, from the opening of the resist pattern 9 to the insulating film 6,
Anisotropic dry etching is performed obliquely on the surface of the insulating film 6 to form the opening 6a, and the metal 10 for forming the gate electrode is vapor-deposited in this state, and thereafter, an unnecessary portion of the insulating film 6 is formed. That is, by removing a portion where the metal 10 for forming the gate electrode is not attached, the trapezoidal insulating film 6c is formed from the bottom surface 8a of the recess 8 along the slope 6b of the vertically long trapezoidal insulating film 6c.
Since the gate electrode 5a having a structure extending to the upper part of the gate electrode 5a is formed, the gate length (Lg) of the gate electrode 5a is smaller than the opening width (W) of the opening of the resist pattern 9 and its height is also It becomes higher by the amount of the trapezoidal insulating film 6c,
The cross-sectional area of the gate electrode 5a becomes larger than that of the gate electrode 5 formed by using the resist pattern 9 having the opening having the same opening width (W) by the conventional method, and as a result, the gate length ( It is possible to obtain a high-performance field effect transistor in which Lg) is shortened and the increase in gate resistance (Rg) is suppressed. Further, since the trapezoidal insulating film 6c is formed on the lower side portion of the gate electrode 5a, the trapezoidal insulating film 6c reinforces the strength of the gate electrode 5a.

A second embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a sectional view showing the structure of a field effect transistor according to a second embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 denote the same or corresponding portions, 5b is a gate electrode, and 8b is 2 Stepped recess, 8c
Is the bottom of the recess. In this field effect transistor, as shown in the figure, the recess is a recess 8b having a two-step structure, and the gate electrode 5b is a recess 8b having a two-step structure.
From the bottom surface 8c of the bottom of the recess on the first side of the source side 8
It is formed so as to extend above the trapezoidal insulating film 6c along the slope 6b of the vertically elongated trapezoidal insulating film 6c.

FIG. 4 is a cross-sectional view showing the manufacturing process of the field effect transistor shown in FIG. 3 by process. In the drawing, the same symbols as those in FIG. 2 indicate the same or corresponding portions.

The manufacturing process will be described below with reference to FIG. First, as shown in FIG. 4A, a resist pattern 7 having an opening of a predetermined width is formed on the active layer 2 provided on one main surface of the semiconductor substrate 1. Next, FIG. 4 (b)
As shown in FIG.
The active layer 2 is etched using, for example, a phosphoric acid-based or sulfuric acid-based etching agent, and its width is, for example, 1.5.
A recess 8 having a depth of -1.8 μm and a depth of 0.1-0.2 μm is formed. Next, the resist pattern 7 is dissolved and removed by using an etching agent such as acetone, and then, as shown in FIG.
As shown in FIG. 5, an insulating film made of a SiN film is formed on the active layer 2 by using, for example, ECR plasma CVD so that the thickness from the bottom surface 8a of the recess 8 is, for example, 0.3 to 0.5 μm. 6 is formed so that its surface becomes flat. Next, a resist having a thickness of about 0.5 μm is applied on the insulating film 6, and then, as shown in FIG. The resist pattern 9 having a hole is formed so that the hole is located above the source side of the recess 8. Next, as shown in FIG. 4 (e), using the resist pattern 9 as a mask, the insulating film 6 is subjected to anisotropic dry etching such as ion beam etching from an oblique direction with respect to the surface thereof. Then, an opening 6a is formed in the insulating film 6 so as to penetrate in an oblique direction with respect to the surface of the insulating film 6, and then the insulating film 6 having the opening 6a is used as a mask to form a bottom surface 8a of the recess 8 in the recess 8a. Etching is carried out on a part using, for example, a phosphoric acid-based or sulfuric acid-based etching agent, and the depth of this part is 0.1 to 0.2 μm.
A groove of a certain degree is formed, and a recess 8b having a two-step structure is formed.
Then, for example, Ti is applied to the entire surface of the semiconductor substrate 1.
When a metal 10 for forming a gate electrode, such as / Pt / Au, WSi, or Ti / Mo / Al, is vacuum-deposited, the insulating film 6 is opened from the bottom surface 8c of the recess 8b having a two-step structure as shown in FIG. 4 (f). A gate electrode 5b formed so as to extend above the insulating film 6 is obtained along the slope 6b on one side of the hole 6a. Next, the unnecessary gate electrode forming metal 10 and the resist pattern 9 are removed using acetone or the like, and further, the unnecessary portion of the insulating film 6 is removed by dry etching, and then a predetermined portion on the active layer 2 is removed. When the source and drain electrodes 3 and 4 are formed at the positions, as shown in FIG. 4 (g),
A vertically long trapezoidal insulating film 6c is provided on the bottom surface 8a of the first-step recess located on the source side of the recess 8b having the two-step structure.
A gate electrode 5b formed along the slope 6b of the trapezoidal insulating film 6c so as to extend from the bottom surface 8c of the recess of the second step of the recess 8b having the two-step structure to the upper part of the trapezoidal insulating film 6c.
A field effect transistor having is obtained.

In the step of forming the gate electrode of the present embodiment as described above, the opening is formed above the recess 8 on the source side of the insulating film 6 provided on the active layer 2 in which the recess 8 is formed. Forming a resist pattern 9 positioned on the insulating film 6 and forming an opening 6a obliquely penetrating from the surface of the insulating film 6 in the insulating film 6 by anisotropic dry etching using the resist pattern 9 as a mask. A groove is formed in a predetermined portion of the bottom surface 8a of the recess 8 of the active layer 2 by wet etching using the insulating film 6 having the opening 6a as a mask to form a recess 8b having a two-step structure. In this state, the metal 10 for forming the gate electrode is vapor-deposited, and thereafter, an unnecessary portion of the insulating film 6, that is, a portion to which the metal 10 for forming the gate electrode is not attached is removed to form the vertically long trapezoidal insulating film 6c. 2 along the slope 6b Since the gate electrode 5b extending from the bottom surface 8c of the second recess of the recess 8c of the structure to the upper portion of the trapezoidal insulating film 6c is formed, the gate length (Lg) of the gate electrode 5b is the opening portion of the resist pattern 9. Of the trapezoidal insulating film 6c and the cross-sectional area of the gate electrode 5b becomes
It becomes larger than that of the gate electrode 5 formed by using the resist pattern 9 having the opening having the same opening width (W) by the conventional method, and as a result, the gate length (Lg) is shortened, and further, It is possible to obtain a high-performance field effect transistor in which the increase in gate resistance (Rg) is suppressed. Further, since the gate electrode 5b is formed close to the source electrode 3 side, it has a so-called off-gate structure, which is a resistance between the gate and the source as compared with the field effect transistor according to the first embodiment shown in FIG. (Rs) is reduced, and
High breakdown voltage can be achieved.

Although the recess type gate electrode is formed in each of the above embodiments, the present invention is also applicable to a field effect transistor having a structure in which a recess is not formed in the active layer and the gate electrode is directly formed on the surface of the active layer. It goes without saying that the invention can be applied.

In the second embodiment, the recess is formed as a recess having a two-step structure. However, it is needless to say that the present invention can be applied to the case where three or more steps are formed.

[0027]

As described above, according to the present invention, the gate electrode is formed from the surface of the active layer along the slope of the trapezoidal insulating film formed in a predetermined region of the active layer. Since it is formed so as to extend upward, there is an effect that it is possible to obtain a field effect transistor excellent in high frequency characteristics in which an increase in gate resistance due to a reduction in gate length is suppressed.

Further, according to the present invention, since the recess is formed in the predetermined region of the active layer and the gate electrode and the trapezoidal insulating film are formed in the recess, the gate length is shortened as described above. In addition, it is possible to obtain a high-performance field effect transistor in which the increase in gate resistance is suppressed and the resistance between gate and source (Rs) is reduced.

Further, according to the present invention, the recess having a two-step structure is formed in a predetermined region of the active layer, and the gate electrode and the trapezoidal insulating film are formed on the source side of the recess having the two-step structure. Similarly to the above, a high-performance field effect transistor in which an increase in gate resistance due to a reduction in gate length is suppressed, a resistance between gate and source (Rs) is reduced, and a withstand voltage is increased is provided. There is an effect that can be obtained.

Further, in the present invention, an insulating film having a flattened surface is formed on the active layer, and the insulating film is subjected to anisotropic etching from an oblique direction to form the active layer from the surface of the insulating film. After forming the opening reaching the surface, the gate metal is deposited along the inclined surface of the opening so as to extend from the surface of the active layer to above the insulating film. The mask pattern has a gate length (Lg) which is smaller than the width of the opening of the mask pattern, and the cross-sectional area thereof is not restricted by the width of the opening and is larger than the conventional one. There is an effect that the gate electrode can be formed stably and with good reproducibility.

Furthermore, in the present invention, after forming a recess in a predetermined region of the active layer, the recess is formed along the inclined surface of the opening of the insulating film formed on the recess in the same manner as described above. Since the gate metal is deposited so as to extend from the bottom surface of the recess to above the insulating film, similar to the above,
The field effect transistor in which the gate length (Lg) of the gate electrode is shortened, the increase in gate resistance is suppressed, and the gate-source resistance (Rs) is reduced can be easily obtained.

Further, in the present invention, after forming a recess in a predetermined region of the active layer, in the same manner as described above, the insulating film formed on the recess is anisotropy obliquely from the source side. Etching is performed to form an opening from the surface of the insulating film to reach the center of the bottom surface of the recess, and then the center of the recess is etched using the insulating film having the opening as a mask. After molding the recess into a two-step structure recess, along the inclined surface of the opening of the insulating film,
Since the gate metal is deposited from the bottom surface of the two-step structure recess toward the upper side of the insulating film, the gate length (Lg) of the gate electrode is shortened and the gate resistance is increased in the same manner as above. In addition to being suppressed, the resistance between the gate and the source (Rs) is reduced, and moreover, there is an effect that a field effect transistor having a high breakdown voltage can be easily obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a field effect transistor according to a first embodiment of the present invention.

2A to 2D are cross-sectional views for each process showing a manufacturing process of the field effect transistor of FIG.

FIG. 3 is a sectional view showing a structure of a field effect transistor according to a second embodiment of the present invention.

4A to 4D are cross-sectional views for each manufacturing step showing a manufacturing process of the field effect transistor of FIG.

FIG. 5 is a cross-sectional view showing one step in a gate electrode forming step of the conventional field effect transistor manufacturing step.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Active Layer 3 Source Electrode 4 Drain Electrode 5, 5a, 5b Gate Electrode 6 Insulating Film 6a Opening 6b Sloping Surface 6c Trapezoidal Insulating Film 7 Resist Pattern 8 Recess 8a Recess Bottom 8b Two-Step Recess 8c Bottom of recess 9 Resist pattern 10 Metal for forming gate electrode Lg Gate length W Width of opening of resist pattern

Claims (6)

[Claims] 1. A field effect transistor comprising a source electrode, a drain electrode and a gate electrode provided on a surface of an active layer on a semiconductor substrate, wherein a trapezoidal insulating film formed on a predetermined region of the surface of the active layer has a sloped surface. A field effect transistor, wherein a gate electrode is formed so as to extend from the surface of the active layer to above the trapezoidal insulating film. 2. The field effect transistor according to claim 1, wherein a recess is formed in the active layer, and the trapezoidal insulating film and the gate electrode are formed in a predetermined region in the recess. And a field effect transistor. 3. The field effect transistor according to claim 2, wherein the recess is formed in a two-step structure, and the trapezoidal insulating film is formed on a bottom surface of the first step of the two-step structure recess on the source side. ,
A field effect transistor, wherein the gate electrode is formed along the slope of the trapezoidal insulating film from the central portion of the bottom surface of the two-step structure recess. 4. A method of manufacturing a field effect transistor, comprising a source electrode, a drain electrode and a gate electrode provided on the surface of an active layer on a semiconductor substrate, wherein an insulating film having a flat surface is provided on the active layer. A step of forming, a step of forming a resist pattern having an opening portion with a predetermined opening width on the insulating film, and anisotropic etching from an oblique direction to the surface of the insulating film using the resist pattern as a mask. A step of forming, in a predetermined region of the insulating film, an opening portion penetrating the insulating film and having a side surface thereof formed by an inclined surface; and using the resist pattern as a mask on the entire surface of the semiconductor substrate. Forming a gate electrode extending from the surface of the active layer along the sloped surface of the opening of the insulating film to above the insulating film, and forming a gate electrode forming metal. An electric field characterized by including a step of removing an unnecessary metal for forming a gate electrode attached to the upper part of the resist pattern together with the pattern, and a step of etching away a portion of the insulating film outside the region covered with the gate electrode. Effect transistor manufacturing method. 5. The method of manufacturing a field effect transistor according to claim 4, wherein a recess is formed in a predetermined region of the active layer prior to forming the insulating film, and the insulating film is formed from a bottom surface of the recess. A method of manufacturing a field effect transistor, comprising forming a gate electrode extending above the insulating film along an inclined surface of the opening formed in the. 6. A method of manufacturing a field effect transistor comprising a source electrode, a drain electrode, and a gate electrode provided on the surface of an active layer on a semiconductor substrate, wherein the active layer has an opening having a predetermined opening width. Forming a first resist pattern and forming a recess in a predetermined region of the active layer by wet etching using the first resist pattern as a mask; and the surface of the active layer being flattened. A step of forming an insulating film, and forming a second resist pattern having an opening portion of a predetermined opening width on the insulating film so that the opening portion is located above the source side of the recess. Step, and using the second resist pattern as a mask, anisotropic etching is performed on the surface of the insulating film from an oblique direction to penetrate the insulating film to a predetermined region of the insulating film and to perform the reset process. And a side surface of which is formed with an inclined surface to form an opening portion, and wet etching is performed on the central portion of the recess using the insulating film in which the opening portion is formed as a mask. A step of forming a groove having a predetermined width in the central portion of the recess and molding the recess into a two-step structure recess; and a metal for forming a gate electrode on the entire surface of the semiconductor substrate using the second resist pattern as a mask. To form a gate electrode extending from the bottom surface of the two-step structure recess toward the source side of the two-step structure recess along the inclined surface of the opening of the insulating film and above the insulating film. And a step of removing unnecessary gate electrode forming metal attached to the upper portion of the resist pattern together with the second resist pattern, and etching away the area of the insulating film covered with the gate electrode. Method of manufacturing a field effect transistor which comprises a that step.