JPH0530449A - Method and device for clock generation - Google Patents

Abstract

PURPOSE:To match phases of an output clock and its horizontal synchronizing signal to each other at each time of the input of the horizontal synchronizing signal and to stabilize the frequency of the output clock. CONSTITUTION:A voltage controlled oscillation part 12 which includes a delay line 11 which delays the input horizontal synchronizing signal by a prescribed time, a two-input NAND circuit 4, and an LC oscillating circuit 5 and takes the delayed horizontal synchronizing signal as the gate signal of the NAND circuit 4 and outputs a clock having a prescribed frequency in accordance with the input horizontal synchronizing signal, a counter part 13 which counts the output clock, a decoder part 14 which decodes the counted value and outputs a pulse signal at the time of arrival of the counted value at a prescribed value, a one shot circuit 15 which outputs a signal whose pulse width is longer than the delay time by the input horizontal synchronizing signal, and a phase comparing part which dsetects the phase difference between the signal having this pulse width and the output pulse signal of the decoder part 14 are provided, and a voltage is fed back to the voltage controlled oscillation part 12 in accordance with the phase difference, and the frequency of the output clock of this part 12 is stabilized by variable control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation method and apparatus used in a television receiver, for example, a timing generation circuit for a liquid crystal driver of a liquid crystal TV, a generation circuit of a clock for digital convergence of a projection TV, and the like. .

[0002]

2. Description of the Related Art Conventionally, as this type of clock generator,
For example, as shown in FIG. 4, some have a PLL configuration. In this figure, a voltage controlled oscillation circuit (VCO circuit) 1 for generating a clock of a predetermined frequency in synchronization with an input horizontal synchronization signal (external), and an output clock of this voltage controlled oscillation circuit 1 are divided by a predetermined frequency. The phase difference between the frequency division oscillator 2 and the input horizontal synchronizing signal is detected, and the output clock phase of the voltage controlled oscillator circuit 1 is corrected according to this difference to stabilize the frequency of the clock. The phase comparison loop filter unit 3 is provided.

In order to obtain a stable clock in the clock generator having the above PLL configuration, the voltage controlled oscillator circuit 1 having a high Q factor must be used.
It has a drawback that it cannot cope with a sharp change of the input signal, it is difficult to immediately follow the temporal discontinuity (skew) of the input signal, and the frequency range in which the phase can be locked is narrow.

Therefore, for example, a clock generator having the configuration shown in FIG. 5 has been proposed. In this figure, 2 NAN
A voltage-controlled oscillator unit (2) that combines the logic circuit of the D circuit (NAND circuit) 4 and the LC oscillation circuit 5 to generate a clock of a predetermined frequency in synchronization with the input horizontal synchronizing signal (HD signal) of the NAND circuit 4. VCO section) 6, a frequency dividing section 7 for multiplying an output clock of the voltage controlled oscillator section 6 by a predetermined number, a timing control section 8 for outputting various signals synchronized with an input vertical synchronization signal (VD signal), and this timing control The output signal of the section 8 and the output signal of the frequency dividing section 7 are compared in phase, and the phase comparison section 9 that outputs this phase difference signal and the output signal of the timing control section 8 turn it on and off. There is provided a switching unit 10 which is turned on only during the synchronizing signal, corrects the phase of the output clock of the LC oscillation circuit 5 by the phase difference signal, and makes the frequency controllable.

In the clock generator, since the output signal of the phase comparator 9 is fed back to the voltage controlled oscillator 6 for each vertical synchronizing signal, the frequency of the output clock can be stabilized. Further, since the Q factor of the voltage controlled oscillator 6 becomes low, the above-mentioned drawback can be solved.

[0006]

However, in the above clock generator, the circuits such as the timing controller 8 and the phase comparator 9 are complicated, and the frequency of the output clock is controlled only for each vertical synchronizing signal. However, there may be a problem in the stability of the frequency of the output clock.

The present invention has been made in view of the above problems, and its object is simple and can be constituted by an inexpensive circuit, and moreover, the phase of the output clock can be adjusted for each input horizontal synchronizing signal, and It is an object of the present invention to provide a clock generator capable of further stabilizing the frequency of the output clock.

[0008]

In order to achieve the above object, the present invention delays the horizontal synchronizing signal by a predetermined time when generating a clock synchronized with the horizontal synchronizing signal of an input television signal, and delays the horizontal synchronizing signal. The clock is output based on the horizontal synchronizing signal, the phase difference between the generated clock and the input horizontal synchronizing signal is detected by the count number of this clock, and the frequency of the clock is changed according to this phase difference, The gist is that the phase of the output clock and the input horizontal sync signal are matched for each input of the sync signal, and the frequency of the output clock is stabilized independently of the phase matching.

Therefore, the clock generator of the present invention includes a delay line for delaying the horizontal synchronizing signal of the input television signal for a predetermined time, a logic circuit and an LC oscillating circuit,
A voltage controlled oscillator that outputs a clock of a predetermined frequency using the horizontal synchronizing signal delayed by the delay line as a gate signal of its logic circuit, and the output clock of this voltage controlled oscillator is counted and reset by at least the input horizontal synchronizing signal. A counter section for inputting a count value of the counter section, and outputting a signal when the number of clocks generated between the horizontal synchronizing signals reaches a predetermined number,
A one-shot circuit for converting the horizontal sync signal of the input television signal into a signal having a pulse width longer than the delay, and detecting the phase difference between the output signal of the one-shot circuit and the output signal of the decoder section to control the voltage. A phase comparison unit for feeding back to the oscillation unit, the phase of the output clock and the input horizontal synchronization signal are matched for each input of the horizontal synchronization signal, and the voltage controlled oscillation is performed according to the phase difference by the phase comparison unit. The frequency of the output clock of the unit can be variably controlled independently of the phase matching.

[0010]

With the above method and configuration, since the delayed horizontal synchronizing signal is used as the gate signal, the phase of the output clock of the voltage controlled oscillator is guaranteed with respect to the delayed horizontal synchronizing signal (that is, the input horizontal synchronizing signal). To be done.

A signal having a pulse width longer than the delay time is obtained in the one-shot circuit by the input horizontal synchronizing signal, and the signal having the pulse width is used as an up / down mode switching signal of the up / down counter section.

Further, when the count number of the output clock is decoded, and a pulse signal is obtained when the count number reaches a preset value, the pulse signal increases the count value of the up / down counter section. / Downed.

The count value of the up / down counter section is converted into an analog signal by the D / A conversion section and fed back to the voltage controlled oscillation section.

As a result, the phase difference between the output clock and the input horizontal synchronizing signal is detected, and an analog voltage corresponding to this phase difference is obtained. The analog voltage value determines the frequency of the output clock of the voltage controlled oscillator. Variably controlled,
And since the above operation is repeated for each input of the horizontal synchronizing signal, the followability to the input horizontal synchronizing signal is good,
The frequency of the output clock is stabilized.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION A clock generation method of the present invention counts clocks generated in a VCO section between input horizontal synchronizing signals, generates a pulse signal at a predetermined count number, and outputs the pulse signal and its horizontal synchronizing signal. Is detected, and the frequency of the output clock of the VCO section is controlled by the detection signal of this phase difference.

Therefore, as shown in FIG. 1, in this clock generator, a delay line 11 for delaying an input horizontal synchronizing signal by a predetermined time and a horizontal synchronizing signal delayed by the predetermined time are used as a gate signal of a 2-nand circuit 4. LC oscillator circuit 5
Voltage controlled oscillator (VCO) that outputs a clock
12, a counter unit 13 that counts the output clock of the voltage control oscillator 12, a decoder unit 14 that decodes the count value of the counter unit 13, and a one that outputs a signal of a predetermined pulse width by the input horizontal synchronization signal. The shot circuit 15 and an output pulse signal of the one-shot circuit 15 are used as an up / down mode switching signal, and an up / down pulse signal from the decoder section 14 is counted.
A down counter section 16 and a D / A conversion section 17 for converting the count value of the up / down counter section 16 into an analog signal and feeding it back to the voltage controlled oscillation section 12.
It has and. In FIG. 1, the same parts as those in FIG. 5 are designated by the same reference numerals, and duplicate description will be omitted.

Further, since the counter section 13 is reset by the delayed horizontal synchronizing signal, the phase comparing section constituted by the up / down counter section 16 and the D / A converting section 17 is input for each input horizontal synchronizing signal. A phase comparison operation is performed for each horizontal synchronizing signal to detect the phase between the input horizontal synchronizing signal and the output clock of the voltage controlled oscillator 12, and an analog signal (voltage) corresponding to the phase difference is detected by the voltage controlled oscillator 1.
Give feedback to 2.

Therefore, the voltage controlled oscillator 12 is
A buffer circuit (voltage follower circuit) 12a for inputting the output analog signal of the D / A converter 17.
Is equipped with.

As the delay line 11,
It is preferable to use a highly accurate one.

FIG. 2 shows the operation of the clock generator having the above configuration.
This will be described with reference to the time chart of FIG. First, it is assumed that the horizontal synchronizing signal of the television signal is input to the delay line 11 (shown in (a) of the same figure).

Then, since the input horizontal synchronizing signal is delayed by a predetermined time τ (shown in (b) of the figure), the 2 NAND circuit 4 inhibits the gate circuit during the "L" level of the delayed horizontal synchronizing signal. Therefore, the clock is not output from the voltage controlled oscillator 12.

During the "H" level of the delayed horizontal synchronizing signal, a clock is output from the voltage controlled oscillator 12 (shown in (e) of the same figure), and the logic of the oscillation clock and the delayed horizontal synchronizing signal is set. The calculation ensures the phase at the start of oscillation of the clock, that is, at the start of output of the clock.

At this time, since the counter section 13 is reset by the input horizontal synchronizing signal, the output clock of the voltage controlled oscillator section 12 can be counted. On the other hand, the one-shot circuit 15 is driven at the falling timing of the input horizontal synchronizing signal, and a signal having a pulse width longer than the delay time τ of the delay line is output (shown in FIG. 7C). It is input to the up / down mode switching terminal of the up / down counter section 16 of the phase comparison section.

The count value of the counter section 13 is decoded by the decoder section 14. When the preset value, that is, the set value of the count number of the output clock is reached, the pulse signal is output from the decoder section 14. Is output (shown in (d) of the figure). In this case, the decoder unit 1
The set value of 4 is near T = Th-τ, that is, the pulse signal is generated near that value.

As a result, when the voltage controlled oscillator 12 outputs a clock, the clock is counted by the counter 13, and when the counter 13 counts up, the decoder 14 outputs a pulse signal. To be done.

At this time, if the signal input to the up / down mode switching terminal is "L" level, that is, if the horizontal synchronizing signal is input at the next timing, the up / down counter section 16 The up mode is set and the output pulse signal of the decoder section 14 is counted up.

Due to this count-up, the output analog value of the D / A converter 17 is increased, that is, the output voltage value is increased and fed back to the voltage controlled oscillator 12. Then, in the voltage controlled oscillator 12, the frequency of the oscillation clock is increased according to the voltage applied through the buffer circuit 12a.

When the signal input to the up / down mode switching terminal of the up / down counter section 16 is "H" level when the counter section 13 counts up, that is, at the next timing, If the sync signal is not input, the up / down counter section 16
Is set to the down mode and the output pulse signal of the decoder section 14 is counted down.

By this countdown, the output analog value of the D / A converter 17 is reduced, that is, the output voltage value is lowered and fed back to the voltage controlled oscillator 12. Then, in the voltage controlled oscillator 12, the frequency of the oscillation clock is lowered according to the voltage via the buffer circuit 12a.

As shown in FIGS. 3C and 3D, the timing of the fall of the output pulse signal of the one-shot circuit 16 (that is, the fall of the input horizontal synchronizing signal) is the rise of the output pulse signal of the decoder section 14 ( That is, when the counter 13 counts up),
The output voltage value of the A / A converter 17 is increased or decreased, and the frequency of the output clock of the voltage controlled oscillator 12 is changed.

Therefore, since the above operation is repeated for each input horizontal synchronizing signal, the followability to the input signal is good, and for example, the frequency of the output clock of the voltage controlled oscillator 12 is set to a constant value between the vertical synchronizing signals. It is possible to converge and generate a clock with a stable frequency.

Further, as shown in FIG. 3, instead of the phase comparator of the above embodiment, a D type flip-flop circuit 1 is used.
8 and the integrating circuit 19 may be used. In this case, if the output pulse signal of the one-shot circuit 16 is "L" level, the output voltage value of the integrating circuit 19 is low, and conversely, if the output pulse signal is "H" level, the integrating circuit is The output voltage value of 19 becomes high. Therefore, the same operation and the same effect as those of the above embodiment can be obtained.

[0033]

As described above, according to the clock generation method and the apparatus thereof of the present invention, the input horizontal synchronizing signal is delayed by the delay line for a predetermined time, and the voltage controlled oscillation constituted by the logic circuit and the LC oscillation circuit is provided. The delayed horizontal synchronizing signal is used as a gate signal by the section to output a clock of a predetermined frequency, the counter section counts the output clock, the decoder section decodes the count value, and the input horizontal synchronizing signal is input. A signal having a pulse width longer than the delay time is obtained by the one-shot circuit, the signal having the pulse width is used as an up / down mode switching signal of the up / down counter section, and the decode output signal (pulse signal) of the decoder section is changed to The count signal of the up / down counter section is used, and this count value is converted to an analog signal by the D / A conversion section. The frequency of the output clock of the voltage controlled oscillator is variably controlled by feeding back to the voltage controlled oscillator, so that the timings of the horizontal synchronizing signal and the count-up time (decode output signal) of the output clock match. By doing so, it is possible to match the phases of the output clock and the horizontal synchronizing signal, and to further stabilize the frequency of the output clock, and further, there is an effect that the circuit is simple and inexpensive.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a clock generator showing an embodiment of the present invention.

FIG. 2 is a time chart diagram for explaining the operation of the clock generator shown in FIG.

FIG. 3 is a schematic partial circuit diagram of a clock generator showing a modified embodiment of the present invention.

FIG. 4 is a schematic block diagram of a conventional clock generator.

FIG. 5 is a schematic block diagram of a conventional clock generator.

[Explanation of symbols]

42 NAND circuit 5 LC oscillator circuit 11 delay line 12 Voltage controlled oscillator 12a Buffer circuit (voltage follower circuit) 13 Counter part 14 Decoder section 15 One-shot circuit 16 Up / Down counter section 17 D / A converter 18 D type flip-flop circuit 19 Integrator circuit

Claims (2)

[Claims] 1. When a clock synchronized with a horizontal synchronizing signal of an input television signal is generated, the horizontal synchronizing signal is delayed by a predetermined time, a clock is output based on the delayed horizontal synchronizing signal, and the count number of the clock is counted. The phase difference between the generated clock and the input horizontal synchronizing signal is detected by, and the frequency of the clock is varied according to the phase difference, and the output clock and the input horizontal synchronizing signal are input for each input of the horizontal synchronizing signal. The clock generation method is characterized in that the frequencies of the output clocks are stabilized independently of the phase synchronization. 2. A delay line for delaying a horizontal synchronizing signal of an input television signal by a predetermined time, a logic circuit and an LC oscillating circuit, and the horizontal synchronizing signal delayed by the delay line is used as a gate signal of the logic circuit at a predetermined frequency. A voltage controlled oscillator for outputting the clock, a counter for counting the output clock of the voltage controlled oscillator and resetting it with at least the input horizontal synchronizing signal, and a count value of the counter for inputting the horizontal synchronizing signal. A decoder unit that outputs a signal when the number of clocks generated between them reaches a predetermined number, a one-shot circuit that converts the horizontal sync signal of the input television signal into a signal having a pulse width longer than the delay, and the one-shot circuit. The phase difference between the output signal of the shot circuit and the output signal of the decoder is detected and fed back to the voltage controlled oscillator. A phase comparison unit, for each input of the horizontal synchronization signal, the phase of the output clock and the input horizontal synchronization signal is matched, and the output clock of the voltage controlled oscillator according to the phase difference by the phase comparison unit. A clock generator characterized in that the frequency can be variably controlled independently of its phase matching.