KR950012833B1 - The circuit of adjusting vertical and horizontal phase on digital convergence - Google Patents

Abstract

a phase detector for comparing an input horizontal blank signal and a frequency-division signal to detect the compared result; a frequency-divider for dividing a horizontal frequency with an oscillating frequency clock corresponding to the slow voltage through a lowpass filter and a voltage control oscillator regarding the detected signal of the phase detector; a first comparator for comparing output data of the frequency-divider with output data of a central processing unit; a horizontal address generator for generating a horizontal address in accordance with an output of the first comparator; a counter for counting the output data of the frequency-divider under the control of the horizontal blank signal; a second comparator for comparing the counted output of the counter with the output data of the central processing unit; a vertical address generator for generating a vertical address in accordance with an output of the second comparator; and an adder for adding the outputs of the horizontal and vertical address generators to output the added result to a memory and a test pattern generator.

Description

Horizontal and Vertical Phase Adjuster for Digital Convergence

1 is a block diagram of a general digital convergence system.

2 is a block diagram of a conventional horizontal and vertical phase control device.

3 is a raster change diagram when the horizontal position is adjusted in FIG. 2;

4 is a horizontal blank (H _BLK ) and a comparator output waveform diagram in FIG.

5 is a block diagram of a horizontal and vertical phase control device of the present invention.

6 is a raster change diagram in the vertical phase adjustment in FIG.

FIG. 7 is a diagram of raster change at the time of horizontal phase adjustment in FIG.

8 and 5, the horizontal blank (H _BLK ) and the frequency divider output waveform diagram.

9 is a characteristic diagram of a 4-bit comparator.

* Explanation of symbols for main parts of the drawings

1: PLL 2: Test Pattern Generator

3: address generator 4: memory

5: CPU 6: Keyboard

7: Digital (D) / Analog (A) conversion unit 9: Amplification unit

10: horizontal vertical phase control unit 11, 21: phase detection unit

12,22: low pass filter 13, 23: voltage controlled oscillator

14: comparator 15, 25: divider

26: horizontal address generator 27: counter

24, 28: 1st, 2nd comparator 29: vertical address generator

30: adder

The present invention relates to a digital convergence that adjusts convergence by selecting a horizontal and vertical adjustment point of a color TV receiver, and then changing a digital value of the adjustment point. The present invention relates to a horizontal and vertical phase adjusting device of a digital convergence device which freely adjusts horizontal and vertical phases so that the center of gravity on the screen can be tasted clearly.

As shown in FIG. 1, a general digital convergence system includes a PLL (1) for phase-locking an input horizontal blank (H _BLK ) signal and a clock pattern generated using the clock generated by the PLL (1). A test pattern generator 2 to generate, an address generator 3 for generating an address according to a clock generated by the PLL 1, and a key signal from a keyboard 6 are inputted to change the data of the memory 4; A CPI 5, a memory 4 for outputting data of an address applied from the address generator 3, a digital / analog converter 7 for analog-converting digital data output from the memory 4, And a low pass filter 8 for correcting the waveform with a step component from the output signal of the digital / analog converter 7 and outputting it to the amplifier 9 and the converged yoke CY. PLL (1), Test Pattern Generator (2) And a portion of the address generator 3 constitutes the horizontal and vertical phase adjusting unit 10, and a detailed configuration thereof is compared with the phase of the input horizontal blank (H _BLK ) signal and the comparison signal as shown in FIG. The voltage detecting oscillator 13 for oscillating a frequency corresponding to the output voltage suppression of the phase detecting unit 11 that is detected by the low pass filter 12 and the voltage controlled oscillator 13 The frequency divider 15 divides the horizontal frequency using the oscillation frequency as a clock, the comparator 14 which compares the data of the frequency divider 15 with the data coming from the CPI, and the output data of the frequency divider 15. It consists of an address generator and a test pattern generator (3) (2) which generate an address, output it to a memory, and generate a test pattern.

In the apparatus configured as described above, the PLL (1) generates a clock necessary for the system synchronized with the horizontal blank signal (H _BLK ) and sends it to the test pattern generator (2) and the address generator (3). A pattern is generated and generated by the video portion, and the address generator 3 generates an address to be applied to the memory 4.

On the other hand, the CPI 5 receives a signal from the keyboard 6, changes the data in the memory 4, and when the adjustment is completed, an address generated by the address generator 3 is applied to the memory 4 to output the data. The output data is converted into an analog waveform by the digital analog converter 7, the waveform of the step component is corrected by the low pass filter 8, and then amplified by the amplifier 9 and passed to the conversion coil CY. . Therefore, the change of the current causes the change of the magnetic field so that the convergence is corrected.

As described above, the horizontal and vertical phase adjustment is performed in the PLL 1, the test pattern generator 2, and the address generator 3 in the configuration of the convergence correction. As shown in FIG.

The phase detector 11 compares the phase of the horizontal blank (H _BLK ) signal and the output waveform of the comparator 14 as shown in FIG. 4 and generates a voltage corresponding to the difference. 12 is made of a gentle waveform and the voltage controlled oscillator 13 oscillates at a predetermined frequency by the magnitude of the output voltage of the low pass filter 12. Using this oscillation frequency as a clock, the frequency divider divides the frequency into a horizontal frequency. The comparator 14 compares the data applied from the CPI (Fig. 1) with the data applied from the frequency divider 15, and generates square wave pulses and sends them to the phase detector 11 if the compared data is the same.

If the data from the CPI to the comparator 14 is changed, the output waveform of the comparator 14 is not equal to the phase of the horizontal blank (H _BLK ) signal. The oscillation frequency of 13 changes the data from the frequency divider 15 to the comparator 14.

However, the phase of the output of the comparator 14 can be adjusted by adjusting the data of the CPI.

Therefore, changing the data of Cfiille, as shown in FIG. 3, the horizontal line moves to the left and right, so that the horizontal sensor can be fitted.

However, in the prior art, only the horizontal position is controlled by data control of the CPI, but the vertical position is also linked because the horizontal address and the vertical address are made together by the output of the divider when the horizontal position is changed. In addition, the comparator output phase changes when the CPI data changes, which causes the phase detection unit to become unstable momentarily by causing the output voltage to move up and down to match the phase of the horizontal blank signal and the comparator output. There was this.

Therefore, in order to solve the conventional problems, the present invention provides a data value from CPI to a comparator, and the comparator compares the value of the frequency divider to control the operation point of the address generator so that the desired adjustment position can be purified to see a stable screen. Invented a horizontal and vertical phase adjusting device for digital convergence, which will be described below in detail with reference to the accompanying drawings.

5 is a configuration diagram of a horizontal and vertical phase adjusting device according to the present invention. As shown therein, a phase detector 21 for detecting and comparing a phase of an input horizontal blank (H _BLK ) signal and a fraction signal and a low pass filter ( 22) a divider 25 for dividing the horizontal frequency by using the oscillation frequency corresponding to the voltage smoothed through the voltage controlled oscillator 23 as a clock, and output data of the divider 25 and output data of the CPI. The first comparator 24 to be remarked, the horizontal address generator 26 to generate a horizontal address according to the remarks output of the first comparator 24, and the divided output of the frequency divider 25 are vertically blanked (V _BLK). A counter 27 for counting under the control of a signal, a second comparator 28 for comparing the count output of the counter 27 and the output data of the CPI, and a vertical output according to the comparison output of the second comparator 28. Vertical address generator (29) for generating addresses ) And an adder 30 that adds the outputs of the horizontal and horizontal vertical address generators 26 and 29 to the memory 31 and the test pattern generator 32.

Referring to the operation and effect of the present invention configured as described above in detail.

As shown in FIG. 8, the horizontal blank signal H _BLK and the output signal of the divider 25 are input to compare the phases of the two signals, and the low-pass filter is applied by the phase detector 21 by a comparison difference. 22), the voltage component is filtered into a gentle waveform and sent to the voltage controlled oscillator 23 to oscillate at the oscillation frequency by the magnitude of the suppression through the low pass filter 22. This oscillation frequency is divided by the frequency divider 25 and the divided output is sent to the first comparator 24. The first comparator 24 outputs the horizontal address generator 26 if it is the same as the data of CPI. The operating point of the generator 26 is determined. In other words, when the CPI data is changed, the output phase of the first comparator 24 is changed, and accordingly the operation time of the horizontal address generator 26 is changed as shown in FIG. That is, as shown in FIG. 9, when the output data of the frequency divider 25 (FIG. 9B) and the data designated from the CFI (FIG. 9A) are input, the CFI data of FIG. A rectangular pulse as shown in (c) is generated to determine the operation time of the horizontal address generator 26.

Similarly, the counter 27 counts the horizontal frequency of the frequency divider 25 and sends the counted value to the second comparator 28 to compare it with the data of the CAPIU. If the compared values are the same, the vertical address generator 29 outputs the vertical address value. Clearing the value counted by the counter 27 is cleared by the vertical blank (V _BLK ) signal.

In this case, when the data of CPI is changed, the output phase of the second comparator 28 is changed and the operation time of the vertical address generator 29 is changed accordingly, as shown in FIG.

Therefore, the outputs of the horizontal and vertical address generators 26 and 29 are added to the adder 30 and sent to the test pattern generator 32 and the memory 31.

As described in detail above, the present invention provides data values to each comparator in CPI, and the comparator controls the operation time of the horizontal and vertical address generators by comparing the values of the frequency divider so that the adjustment width can be adjusted to the desired adjustment position. It has the effect of getting an increased and stable picture.

Claims (1)

A phase detector 21 for comparing and detecting a phase of an input horizontal blank (H _BLK ) signal and a divided signal, and a low pass filter 22 and a voltage controlled oscillator for the signal detected through the phase detector 21. 23, a divider 25 for dividing the horizontal frequency using the oscillation frequency corresponding to the voltage smoothed through the clock, and a first comparator 24 for comparing the output data of the divider 25 with the output data of the CPI. And a horizontal address generator 26 which generates a horizontal address according to the comparison output of the first comparator 24, and the division output of the frequency divider 25 under the control of a vertical blank (V _BLK ) signal. A second comparator 28 for comparing the counter 27, the count output of the counter 27 and the output data of the CPI, and a vertical address generator for generating a vertical address according to the comparison output of the second comparator 28. 29, the horizontal and vertical address It adds the output of the generator 26 (29) memory 31 and the test pattern generator 32, the horizontal and vertical phase adjustment at the time of digital convergence consisting of the adder 30 for output to.