JP2588584B2 - Digital convergence correction device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a convergence correction device for a television receiver or a display using a cathode ray tube, and more particularly to a digital convergence correction device capable of performing convergence correction with high accuracy. Things.

[Conventional technology]

As is well known, a digital convergence correction device capable of performing convergence correction with high accuracy is to determine a convergence correction amount required at each point on a screen in advance and store the convergence correction data in a digital format in a memory as convergence correction data. This convergence correction data is read out in synchronization with the raster scan in the cathode ray tube, and the convergence correction data is converted into an analog signal to obtain a convergence correction signal, thereby performing convergence correction of the electron beam. The required convergence correction amount can be determined independently for each point (convergence adjustment point) requiring the above convergence correction, and a convergence correction signal having a desired waveform can be easily obtained.

However, in the digital convergence correction device, it is not necessary to simply synchronize the convergence correction signal with the raster scan in the cathode ray tube, but to adjust the phase relationship between the raster scan and the convergence correction signal in the cathode ray tube to obtain a desired phase relationship. It must be.

For example, in a conventional digital convergence correction device, as shown in JP-A-61-222392, the generation timing of an address signal for specifying an address for reading convergence correction data from a memory is controlled by a variable resistor. The timing is adjusted using an analog delay circuit as timing setting means composed of the above, and is synchronized with the reference horizontal scanning signal corresponding to the center position of the horizontal scanning retrace period, whereby the frequency of the horizontal or vertical synchronizing signal and the effective The convergence adjustment point and the position of the convergence correction amount on the screen are always kept the same for different signal specifications such as the display period (that is, the phase between the raster scan and the convergence correction signal in the cathode ray tube). Improve the accuracy of convergence correction (by ensuring that the relationship is a predetermined phase relationship) Which was.

Other conventional examples include, for example,
As shown in Japanese Patent Application Laid-Open No. 159996, a digital delay circuit as a timing adjusting means including a switch, a data selector, and the like is used to generate a horizontal address signal for specifying a horizontal address for reading convergence correction data from a memory. By adjusting using
The convergence correction signal compensates for a phase delay caused by passing through the low-pass filter (that is, a phase delay with respect to the raster scan in the cathode ray tube).

[Problems to be solved by the invention]

As described above, in the prior art, as a timing adjusting means for adjusting the generation timing of an address signal designating an address for reading convergence correction data from a memory, an analog delay circuit comprising a variable resistor or the like, or a switch or data A digital delay circuit including a selector and the like has been used.

However, an analog delay circuit using a variable resistor or the like has a problem that its operation is unstable and it is difficult to incorporate the digital convergence correction device into an IC when the device is formed into an IC.

In addition, digital delay circuits using switches and data selectors use digital convergence correction devices as ICs.
In such a case, there is a problem in that if it is to be incorporated into the IC, a large number of adjusting terminals are required outside, and thus it becomes impossible to integrate the IC or the cost will increase.

In addition, it is necessary to adjust a variable resistor in an analog delay circuit and a switch in a digital delay circuit, and there is a problem in that the cost increases due to the provision of the variable resistor and the switch.

Therefore, an object of the present invention is to solve the above-described problems of the related art, and to use a switch or a variable resistor without using a switch or a variable resistor, thereby enabling a desired relationship between a raster scan and a convergence correction signal in a cathode ray tube. Moreover, IC
It is an object of the present invention to provide a digital convergence correction device which does not require a large number of adjustment terminals even when the digital convergence is realized.

[Means for solving the problem]

In order to achieve the above object, according to the present invention, a digital convergence correction device is provided for each of a plurality of convergence adjustment points obtained as cross points of a grid pattern composed of a combination of horizontal lines and vertical lines assumed on a screen of a cathode ray tube. The digital memory means which stores the convergence correction amount in advance as convergence correction data, and an address signal designating a horizontal address and a vertical address in the digital memory means are synchronized with a raster scan in the cathode ray tube. An address signal generating means for generating the convergence correction data read from an address specified by the address signal in the digital memory means, and converting the convergence correction data into an analog signal and outputting the analog signal as a convergence correction signal And a digital-to-analog conversion means, and adjusts the digital memory means so that, apart from the convergence correction data, the phase relationship between the raster scan in the cathode ray tube and the convergence correction signal has a desired phase relationship. And phase adjusting means for adjusting the generation timing of the address signal in the address signal generating means in accordance with the phase adjusting data read from the digital memory means. .

Here, the phase adjusting means includes a holding means for holding the phase adjustment data read from the digital memory means, and a phase adjustment data held by the holding means, and a timing corresponding to the phase adjustment data. Timing signal generating means for generating a signal;
Can be configured.

When the hold unit holds abnormal data as the phase adjustment data at the time of power-on or input of external noise, the phase adjustment operation in the present invention, that is, the raster scan in the cathode ray tube and the convergence correction signal There is a possibility that the operation of adjusting the phase relationship to the desired phase relationship may malfunction and a normal convergence correction signal may not be obtained.

Therefore, in addition to the above-described configuration, a first determining unit that determines whether or not the timing signal generating unit has stopped generating the timing signal, and the determining unit stops generating the timing signal. If it is determined that
Means for renewing the hold of the phase adjustment data in the hold means, or inputting the address signal generated from the address signal generating means, and setting an address designated by the address signal to a predetermined value. The second to determine whether or not it is within the range of
And a means for renewing the holding of the phase adjustment data in the holding means when the determining means determines that the address specified by the address signal is not within a predetermined range. Or a means for renewing the hold of the phase adjustment data in the hold means at the time of power-on, or providing the phase adjustment data given to the timing signal generation means by the hold means to the timing signal generation means. May be limited to a range in which the generation of the timing signal does not stop.

[Action]

The digital memory means previously stores the phase adjustment data together with the convergence correction data. The address signal generating means generates an address signal designating a horizontal address and a vertical address in the digital memory means in synchronization with a raster scan in the cathode ray tube. The digital-analog conversion means converts the convergence correction data read from an address specified by the address signal in the digital memory means into an analog signal and outputs the analog signal as a convergence correction signal.

On the other hand, among the phase adjustment means, the hold means holds the phase adjustment data read from the digital memory means, and the timing signal generation means stores the phase adjustment data held by the hold means. And generates a timing signal corresponding to the phase adjustment data. Then, the address signal generating means receives the timing signal and adjusts the generation timing of the address signal according to the timing signal.

Thereby, the read timing of the convergence correction data stored in the digital memory means is adjusted, and the phase relation between the convergence correction signal obtained from the convergence correction data and the raster scan in the cathode ray tube becomes a desired phase relation. It is adjusted as follows.

As described above, according to the present invention, the phase relationship between the raster scan and the convergence correction signal in the cathode ray tube can be set to a desired relationship without providing a switch, a variable resistor, and the like. Therefore, there is no need to perform an operation of adjusting a switch, a variable resistor, and the like, and there is an effect that a highly accurate convergence correction can be performed without a fear of an increase in cost.

Further, according to the present invention, it is easy to make an IC, and
Since a large number of adjustment terminals are not required even in the case of using an IC, there is no possibility that the use of an IC becomes impossible or the cost increases.

When the first determining means and the re-holding means are newly provided, the first determining means determines whether or not the timing signal generating means has stopped generating the timing signal. This is based on the fact that when the hold unit holds abnormal data as the phase adjustment data and the phase adjustment operation malfunctions, the timing signal generation unit stops generating the timing signal. That is, it is determined whether or not a phase adjustment malfunction has occurred by determining the stop of the generation of the timing signal. The re-holding means renews the hold of the phase adjustment data in the holding means when the determination means determines that the generation of the timing signal has stopped, that is, that a phase adjustment malfunction has occurred.

As a result, the normal phase adjustment data read from the digital memory means is newly held by the hold means, and the phase adjustment operation returns to the normal operation.

A second determination unit that receives the address signal generated by the address signal generation unit and determines whether an address specified by the address signal is within a predetermined range; If it is determined that the address specified by the address signal is not within a predetermined range,
Means for renewing the hold of the phase adjustment data in the hold means, or means for renewing the hold of the phase adjustment data in the hold means at power-on, or Even if the phase adjustment data given to the timing signal generating means is limited to a range in which generation of the timing signal in the timing signal generating means does not stop, as described above, finally, Normal phase adjustment data is held by the holding means, and the phase adjustment operation returns to a normal operation.

As described above, according to the present invention, it is possible to prevent a phase adjustment malfunction that occurs when power is turned on or external noise is input.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

 First, the configuration of the present embodiment will be described.

In FIG. 1, reference numerals 1 and 2 denote input terminals for inputting a horizontal blanking pulse H.BLK and a vertical blanking pulse V.BLK in synchronization with a raster scan in a cathode ray tube (not shown).

3 is a phase detector (PD), 4 is a low-pass filter (LPF), 5 is a voltage controlled oscillator (VCO), and 6 is a division ratio 1 / n.
A PLL with these 3, 4, 5, and 6 elements
(Phase Locked Loop).

Reference numeral 7 denotes an address clock generator, 8 denotes an H reference pulse generator that generates an H reference pulse HD having a horizontal (hereinafter abbreviated as H) cycle using an output from the frequency divider 6, and 9 denotes an H phase. H phase data latch for holding adjustment data, 10 is a V phase data latch for holding vertical (hereinafter abbreviated as V) phase adjustment data, 11 and 12 are H phase adjustment counter, V phase adjustment counter, 13 and Reference numeral 14 denotes a matching circuit, and reference numerals 15 and 16 denote H address counters and V address counters for respectively generating an H address signal and a V address signal for designating an H address and a V address as read addresses of a memory 17 described later.

Reference numeral 18 denotes a data converter, 19 denotes a digital-analog converter (DAC), 20 denotes a low-pass filter (LPF) for interpolating a signal, 21 denotes an amplifier (AMP) for driving a convergence yoke 22 described later, and 22 denotes A convergence yoke (CY) for generating a convergence magnetic field.

Reference numerals 23 and 24 denote an H-phase address decoder and a V-phase address decoder, respectively. 25 denotes a V reference pulse generator for generating a V reference pulse VD having a V period using the vertical blanking pulse V.BLK from the input terminal 2, 26 is H phase adjustment counter
Reference numeral 27 denotes an H phase adjustment circuit including the V phase adjustment counter 12 and the coincidence circuit 14.

Now, the output of the voltage controlled oscillator 5 constituting the PLL, clock is generated having a frequency phase-synchronized with n × f _H the horizontal blanking pulse H.BLK with a horizontal deflection frequency f _H from an input terminal 1 It is assumed that

The clock generated by the voltage controlled oscillator 5 is frequency-divided by the frequency divider 6, and then becomes an H-synchronized H reference pulse HD in the H reference pulse generator 8. H-synchronized H reference pulse HD is H
The phase is adjusted by the phase adjustment circuit 26, and the H phase adjustment output is output.
HD ′ and is input to the H address counter 15.

The phase adjustment amount of the H phase adjustment circuit 26 is controlled by the H phase adjustment data from the memory 17 held by the H phase data latch 9.

The H phase adjustment data stored in the memory 17 is
The timing that the phase data latch 9 holds is H, V
The timing signal generated by the H-phase address decoder 23 based on the outputs of the address counters 15 and 16
Controlled.

On the other hand, the vertical blanking pulse V.BLK input from the input terminal 2 is shaped by the V reference pulse generator 25,
It becomes the V reference pulse VD of the V synchronization. V-synchronized V reference pulse
The VD is phase-adjusted by the V-phase adjustment circuit 27, output as a V-phase adjustment output VD ', and becomes an input to the V address counter 16.

The phase adjustment amount of the V-phase adjustment circuit 27 is controlled by V-phase adjustment data from the memory 17 held by the V-phase data latch 10, as in the H-phase adjustment circuit 26.

Further, the V phase adjustment data stored in the memory 17 is
The timing that the phase data latch 10 holds is H, V
The timing signal generated by the V-phase address decoder 24 based on the outputs of the address counters 15 and 16
Controlled.

Next, in the H address counter 15, the clock generated by the address clock generator 7 is counted, and the H phase adjusted output HD 'of the H cycle whose phase has been adjusted is used as a reset pulse, so that the read address in the memory 17 is obtained. An H address signal for designating the H address is generated. Also, the V address counter 16 counts the clock of the H cycle from the H address counter 15,
By using the V-phase adjustment output VD 'of the V cycle whose phase has been adjusted as a reset pulse, a V address signal for specifying a V address as a read address in the memory 17 is generated. As a result, the convergence correction data stored in the memory 17 is read out in synchronization with a raster scan of a cathode ray tube (not shown).

The read convergence correction data is converted from a digital signal to an analog signal by a digital-to-analog converter 19 via a data converter 18 and then converted to a convergence yoke 2 via a low-pass filter 20 and an amplifier 21.
2 is driven to perform convergence correction.

Next, the H and V phase adjustment circuits 26 and 27 will be described with reference to FIGS.
This will be described in more detail with reference to the drawings.

In FIG. 1, the H and V phase adjustment counters 11 and 12 respectively receive the clock from the address clock generator 7 or the H or V phase adjustment counter.
The phase adjustment output HD 'is counted, and the output is reset by the H reference pulse HD or the V reference pulse VD. Also,
The matching circuits 13 and 14 are respectively provided with H and V phase adjustment counters 11 and 1
2 and H, V phase data latches 9 and 10 hold
When the H and V phase adjustment data match, an output is generated.

FIG. 2 is a timing chart showing the timing of the main part signals in FIG.

In FIG. 2, a is an H phase adjustment output HD 'input as a clock from the H phase adjustment circuit 26 to the V phase adjustment counter 12, and b is an input as a reset pulse from the V reference pulse generator 25 to the V phase adjustment counter 12. V reference pulse
VD and c are the outputs of the V phase adjustment counter 12, and d is the coincidence circuit 14.
, The output of the V-phase data latch 10 (that is, the V-phase adjustment data held by the V-phase data latch 10), and e is the V-phase adjustment output V output from the matching circuit 14.
D 'and f are the outputs of the V address counter 16 (that is, the above-mentioned V address signal), and g is the output of the V phase address decoder 24 (that is, the above-mentioned timing signal).

The V phase adjustment counter 12 counts the H phase adjustment output HD 'shown in FIG. 2A generated by the H phase adjustment circuit 26 once during one horizontal scanning period, and the V reference pulse generator 25 performs one vertical scanning. It is reset by the V reference pulse VD shown in FIG. 2 (b) which occurs once during the period. At this time, as shown in FIG. 2D, the V-phase data latch 10 is assumed to hold a value of, for example, 3 as V-phase adjustment data.

When the output of the V-phase adjustment counter 12 shown in FIG. 2 (c) matches the output of the V-phase data latch 10 shown in FIG. 2 (d), the matching circuit 14 switches to the state shown in FIG. A phase adjustment output VD 'as shown is output, and the V address counter 16 is reset. That is, the count start position of the V address counter 16 with respect to the V reference pulse VD shown in FIG. 2B can be adjusted to an arbitrary phase according to the value of the V phase adjustment data.

Incidentally, the data stored in the memory 17 from address 0 to several tens of addresses are output during the vertical flyback period and do not contribute to the convergence correction.

Therefore, the V-phase adjustment data used in the present invention is written in advance at address 0 of the memory 17, and the V-address counter 16 stores 0 as the V-address as shown in FIG.
Immediately after outputting the V address signal designating the address, the V phase address decoder 24 receives the V address signal and raises the output timing signal as shown in FIG. 2 (g). When the timing signal rises, it is stored at address 0 of the memory 17 as shown in FIG. 2 (d). The V-phase adjustment data (for example, a value of 3) is held, and the V-phase adjustment data is captured.

The operation of the H-phase adjustment circuit 26 is also performed in the same manner as the V-phase adjustment circuit 27, based on the H-phase adjustment data written in the address 17 of the memory 17 in advance.

As described above, according to the present embodiment, at the time of convergence adjustment, arbitrarily settable phase adjustment data is stored in advance in the memory 17 together with the convergence correction data, and when the convergence correction is actually performed. To
As described above, by reading the phase adjustment data during the vertical blanking period, the raster scan and convergence of the cathode ray tube (not shown) can be performed without increasing the memory capacity and without affecting the convergence on the screen. The desired phase relationship with the correction signal can be obtained.

However, in this embodiment, there is a possibility that a malfunction of phase adjustment as described below may occur.

FIG. 3 is a timing chart showing the timing of the main signal when a phase adjustment malfunction occurs in FIG.

In FIG. 3, a to g are the same as a to g described in FIG. 2, respectively.

As described above, the V-phase adjustment counter 12 counts the H-phase adjustment output HD ′ from the H-phase adjustment circuit 26, and is reset by the V reference pulse VD from the V reference pulse generator 25, whereby the third As shown in FIG.
0 to 0 according to the number of scanning lines for one field in the system
It is assumed that the count up to 262 has been performed.

In such a case, the V phase data latch 10
As shown in the figure, a value (for example, 511) larger than the maximum count value (ie, 262) of the V-phase adjustment counter 12 is held as an initial value at the time of turning on the power or due to the influence of external noise or the like. Then, FIG. 3 (c),
As shown in (d), the output of the V phase adjustment counter 12 and V
The output of the phase data latch 10 does not match, and the matching circuit 14 outputs the V-phase adjustment output V as shown in FIG.
D 'is not output, and as a result, the V address counter 16 cannot be reset. Therefore, when the count value of the V address counter 16 precedes the V address of the V phase adjustment data stored in the memory 17 (for example, the address 0 described above), the correct V stored in the memory 17 is used. The phase adjustment data is not held in the V phase data latch 10, and finally, the count value of the V address counter 16 becomes the maximum count value (for example, 51
After stopping at 1), the V address counter 16 continues to output the V address signal based on the count value. For this reason, the convergence magnetic field generated by the convergence yoke 18 becomes abnormal, and the convergence is greatly disturbed.

As described above, in the present embodiment, there is a possibility that a phase adjustment malfunction may occur when the power is turned on or when external noise is input.

Therefore, next, an embodiment of the present invention which prevents the above-described malfunction of the phase adjustment will be described.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

In FIG. 4, the same elements as those in FIG. 1 (ie, 1 to 27) are denoted by the same reference numerals as those in FIG. In addition, reference numeral 30 denotes a D-FF (D-type flip-flop) that is set at the falling edge of the clock input and reset by the CLR input. That is, the Q output of the D-FF 30 is set at the falling edge of the V reference pulse VD, and is reset by the Q output of the D-FF 35 described later. Also, 31
Is an AND circuit for deriving the logical product of the V reference pulse VD and the Q output of the D-FF 30, and 32 is the output of the AND circuit 31 and the H phase adjustment output H
An OR circuit 33 for conducting a logical sum with D ', an OR circuit 33 for conducting a logical sum of the output of the AND circuit 31 and the V-phase adjustment output VD', 34, 35
Are D-FFs that send the outputs of the OR circuits 32 and 33 to the reset inputs of the H and V address counters 15 and 16, respectively, when the clock from the address clock generator 7 rises. In this embodiment, the components 30 to 35 constitute a phase adjustment malfunction prevention circuit. Note that the output of the AND circuit 31 is a malfunction detection output of the phase adjustment malfunction prevention circuit.

FIG. 5 is a timing chart showing the timing of the main signal in FIG.

In FIG. 5, a to g are the same as a to g described in FIG. In addition, h is the Q output of D-FF30,
i is the output of the AND circuit 31, j is the output of the OR circuit 33, and k is DF
Q output of F35.

Now, as in the case of FIG.
Performs counting from 0 to 262 as shown in FIG. 5C, and stores the maximum count value (V) of the V-phase adjustment counter 12 in the V-phase data latch 10 as shown in FIG. That is, it is assumed that a value larger than 262) (for example, 511) is held as an initial value at the time of turning on the power or due to the influence of external noise or the like, thereby causing a phase adjustment malfunction.

Therefore First, D-FF30 at time t _1, is set by the falling edge of the V reference pulse VD shown in FIG. 5 (b), at time t _2, the when the next V reference pulse VD occurs, Figure 5 The output of the AND circuit 31 shown in (i) is reset via the OR circuit 33 and the D-FF 35 as shown in FIGS. 5 (j) and 5 (k), and the V address counter 16 is reset as shown in FIG. 5 (f). . At that time, the output of the AND circuit 31 is also reset via the OR circuit 32 and the D-FF 34 at the same time.

Then, the H and V address counters 15 and 16 store the H and V phase adjustment data in the memory 17 at addresses (addresses 0 and 1).
As a result, the phase data latch 10 stores the normal V-phase adjustment data (for example, a value of 3) in the memory 17.
Input from and hold. The operation of the V phase adjustment circuit 27 and the V address counter 16 returns to the normal operation by the operation of the phase adjustment malfunction prevention circuit.

Next, in the state where the phase adjustment operation is performed normally,
At time t _3, as shown in FIG. 5 (e), by generation of V phase adjustment output VD ', via the OR circuit 33, D-FF35, D
Since the FF 30 is reset as shown in FIG. 5 (h), no extra reset pulse is input to the V address counter 16.

Similarly, a value larger than the maximum count value of the H-phase adjustment counter 11 is held in the H-phase data latch 9 as an initial value at the time of turning on the power or by the influence of external noise or the like. If an adjustment malfunction has occurred, the H phase adjustment output HD ′ from the matching circuit 13 is output.
Stops, the operation of the V-phase adjustment counter 12 also stops, and the V-phase adjustment output VD 'is not output. As a result, D-
Since the reset operation of FF30 is not performed, next, D-FF30
When the V reference pulse VD is inputted to the AND circuit 31, the AND circuit 31, the OR circuit 3
H, V address counters 15,16 via 2,33, D-FF34,35
To reset the H and V address counters 15 and 16. As a result, the H-phase data latch 9 holds the normal H-phase adjustment data and returns to the normal operation.

As described above, according to the present embodiment, after preventing a phase adjustment malfunction that occurs at the time of power-on or input of external noise or the like, a cathode ray tube (not shown) is used in accordance with the phase adjustment data stored in the memory 17. The phase adjustment of the convergence correction signal for the raster scan can be performed.

Next, a method of preventing a phase adjustment malfunction by another means will be described.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

In the present embodiment, even if the phase data latch that holds the phase adjustment data holds abnormal data and the phase adjustment output that resets the address counter stops,
An address generation mechanism for holding normal phase adjustment data in the phase data latch prevents phase adjustment malfunction.

6, the same elements as those in FIG. 1 (ie, 1 to 27) are denoted by the same reference numerals as those in FIG. In addition, reference numeral 60 denotes a discrimination circuit that generates an output for resetting the H and V address counters 15 and 16 when the V address counter 16 outputs the maximum count value (for example, 511). The reset output of the discrimination circuit 60 and
An OR circuit for deriving the logical sum of the H and V phase adjustment circuits 26 and 27 with the H and V phase adjustment outputs HD 'and VD', respectively.

In the embodiment of FIG. 1, the V address counter 16
As shown in FIG. 3 (f), when the maximum count value (for example, 511) is reached, the counting is stopped. But,
In this embodiment, according to the configuration shown in FIG. 6, when the V address counter 16 outputs the maximum count value (for example, 511), the discrimination circuit 60 discriminates it and generates a reset output, and the OR circuit 32 , 33, the H, V address counter 15, 1
Force reset of 6.

Therefore, even if abnormal phase adjustment data is held in the V-phase address data latch 10 and the V-phase adjustment output VD 'for resetting the V-address counter 16 stops, when the address counter accesses the address 0, the normal phase The adjustment data is held by the V-phase data latch 10, and the circuit operation returns to normal.

Therefore, also in the present embodiment, it is possible to prevent a malfunction of the phase adjustment.

FIG. 7 is a block diagram showing a fourth embodiment of the present invention.

In this embodiment, the normal phase adjustment data is always held in the phase data latch when the power is turned on.

In FIG. 7, the same elements as those in FIG. 1 (ie, 1 to 27) are denoted by the same reference numerals as those in FIG. In addition, 70 is a reset pulse generator that generates a reset pulse when the power is turned on, and 32 and 33 are the outputs of the reset pulse generator 70 and H and V of the H and V phase adjustment circuits 26 and 27.
This is an OR circuit for guiding the logical sum of the V phase adjustment outputs HD 'and VD'.

7, a reset pulse generator 70 generates a reset pulse when power is turned on, and resets the H and V address counters 15 and 16 via OR circuits 32 and 33. Therefore, when the power is turned on, the H and V address counters 15 and 16 always output an address signal specifying the address where the phase adjustment data is stored, and hold the normal phase adjustment data in the H and V phase data latches 9 and 10. Let it.

According to the present embodiment, it is possible to prevent a phase adjustment malfunction when the power is turned on.

FIG. 8 is a block diagram showing a fifth embodiment of the present invention.

In this embodiment, the phase data latch holds only the phase adjustment data in the range where the phase adjustment does not malfunction.

8, the same elements as those in FIG. 1 (ie, 1 to 27) are denoted by the same reference numerals as those in FIG. In addition, 80 and 81 are H, V phase data latch
An H / V phase data discriminating circuit 82 for discriminating that 9, 9 has held a value larger than the maximum count value (for example, 262) of the H and V phase adjusting counters 11 and 12; OR circuit for deriving the logical sum of the output of the V phase data discriminating circuit 81 and the output of the V phase data discriminating circuit 81.
This is an OR circuit that guides the logical sum of the H and V phase adjustment outputs HD ′ and VD ′ of the phase adjustment circuits 26 and 27, respectively.

In FIG. 8, the outputs of the H and V phase data latches 9 and 10 are
The maximum count value of the H and V phase adjustment counters 11 and 12 (for example,
262) When the larger value is held, the H and V phase data discriminating circuits 80 and 81 discriminate it and reset the H and V address counters 15 and 16 via the OR circuit 82 or OR circuit 32 or 33. . As a result, similarly to the above-described second embodiment, since the H and V phase data 9 and 10 hold the normal phase adjustment data again, malfunction can be prevented.

In this embodiment, since the maximum count value of the H and V phase adjustment counters 11 and 12 changes depending on the specification of the input signal, the H and V phase data discriminating circuits 80 and 81 match the signal specifications. The setting in must also be changed.

FIG. 9 is a block diagram showing a sixth embodiment of the present invention.

This embodiment is a configuration in which the configuration of the above-described fifth embodiment is simplified.

In FIG. 9, the same components as those in FIG. 1 (ie, 1 to 27) have the same reference numerals as those in FIG. In addition, 90, 91 are H, V phase data latch 9,
A limiting circuit for limiting each of the ten outputs.

In this embodiment, the outputs of the H and V phase data latches 9 and 10 are:
By way of the limiting circuits 90 and 91, respectively, the phase adjustment data is limited to a range where no malfunction occurs (for example,
By masking the upper bits, it is limited to 0 to 127). For this reason, even if abnormal phase adjustment data
Even if it is held in H, V phase data latches 9, 10,
Since the outputs of the limiting circuits 90 and 91 and the outputs of the H and V phase adjustment counters 11 and 12 can be made coincident with each other, H, V
By resetting the address counters 15 and 16, normal phase adjustment data can be held again in the H and V phase data latches 9 and 10.

According to the present embodiment, a phase adjustment malfunction can be prevented with a simple configuration.

〔The invention's effect〕

As described above, according to the present invention, the phase relationship between the raster scan and the convergence correction signal in the cathode ray tube can be set to a desired relationship without providing a switch, a variable resistor, and the like. Therefore, there is no need to perform an operation of adjusting a switch, a variable resistor, and the like, and there is an effect that a highly accurate convergence correction can be performed without a fear of an increase in cost.

Further, according to the present invention, it is easy to make an IC, and
Since a large number of adjustment terminals are not required even in the case of using an IC, there is no possibility that the use of an IC becomes impossible or the cost increases.

Further, according to the present invention, it is possible to prevent a phase adjustment malfunction that occurs when power is turned on or when external noise is input.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
FIG. 3 is a timing chart showing the timing of the main signal in FIG. 1, FIG. 3 is a timing chart showing the timing of the main signal when a phase adjustment malfunction occurs in FIG. 1, and FIG. 2 is a block diagram showing an embodiment of FIG. 2, FIG. 5 is a timing chart showing timings of main signals in FIG. 4, and FIG.
FIG. 7 is a block diagram showing a fourth embodiment of the present invention, FIG. 8 is a block diagram showing a fifth embodiment of the present invention, and FIG. 9 is a block diagram showing the fifth embodiment of the present invention. FIG. 14 is a block diagram showing a sixth embodiment. Explanation of reference numerals 1,2 …… Input terminal, 8,25 …… H, V reference pulse generator, 9,10
…… H, V phase data latch, 11,12 …… H, V phase adjustment counter, 13,14 …… Match circuit, 15,16 …… H, V address counter, 17 …… Memory, 18 …… Data conversion Section, 19: Digital-to-analog converter, 22: Convergence yoke, 23, 24: H, V phase address decoder, 26, 27: H, V
Phase adjustment circuit.

Continued on the front page (72) Inventor Tadahiro Kawagishi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Within Hitachi Video Engineering Co., Ltd. (72) Inventor Makoto Shiomi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. In-house (72) Inventor Michitaka Osawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (56) References JP-A-62-159996 (JP, A)

Claims (7)

(57) [Claims] 1. A television receiver or display using a cathode ray tube according to a raster scan method, wherein a plurality of convergence obtained as cross points of a lattice pattern composed of a combination of horizontal lines and vertical lines assumed on a screen of the cathode ray tube. Digital memory means for storing in advance each convergence correction amount at the adjustment point as convergence correction data, and an address signal designating a horizontal address and a vertical address in the digital memory means are transmitted to a raster in the cathode ray tube. An address signal generating means generated in synchronization with scanning; and a convergence correction circuit for converting the convergence correction data read from an address designated by the address signal in the digital memory means into an analog signal. Digital-to-analog conversion means for outputting as a signal, and in the digital memory means, apart from the convergence correction data, a phase relation between the raster scan in the cathode ray tube and the convergence correction signal becomes a desired phase relation. And phase adjustment data for such adjustment is stored in advance,
A digital convergence correction device, comprising: a phase adjusting means for adjusting the generation timing of an address signal in the address signal generating means according to the phase adjustment data read from the digital memory means. 2. A digital convergence correction apparatus according to claim 1, wherein said phase adjustment data is an address signal generated by said address generation means in said digital memory means during a flyback period of a raster scan in said cathode ray tube. A digital convergence correction device, wherein the digital convergence correction device is stored at an address specified by (1). 3. The digital convergence correction apparatus according to claim 1, wherein said phase adjustment means holds said phase adjustment data read from said digital memory means, and holds said phase adjustment data. And timing signal generating means for generating a timing signal in accordance with the phase adjustment data, wherein the address signal generating means receives the timing signal and responds to the timing signal. A digital convergence correction device for adjusting the generation timing of the address signal. 4. A digital convergence correction apparatus according to claim 3, wherein said timing signal generating means determines whether or not said timing signal has been generated, and said determining means determines whether or not said timing signal has been generated. Means for resetting the hold of the phase adjustment data in the hold means when it is determined that the convergence has stopped. 5. The digital convergence correction apparatus according to claim 3, wherein said address signal generated by said address signal generating means is input, and whether an address specified by said address signal is within a predetermined range. Discriminating means for discriminating whether or not the address specified by the address signal is not within a predetermined range; and means for re-holding the phase adjustment data in the holding means. And a digital convergence correction device. 6. A digital convergence correction apparatus according to claim 3, further comprising means for renewing the hold of said phase adjustment data in said hold means when a power supply used in said digital convergence correction apparatus is turned on. A digital convergence correction device, characterized in that: 7. The digital convergence correction apparatus according to claim 3, wherein said hold means sets said phase adjustment data to be supplied to said timing signal generation means within a range where generation of said timing signal in said timing signal generation means does not stop. A digital convergence correction device characterized by being limited.