JP2973756B2 - Control waveform generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating various control waveforms for controlling a display monitor.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration of a conventional control waveform generation circuit of this kind. In the figure, reference numeral 1 denotes an input horizontal synchronizing signal HD and a voltage control generation circuit VC described later.
A phase comparison circuit 2 for comparing the phase with the feedback signal divided from the O3 output, a low-pass filter LPF 2 for converting a pulse output from the phase comparison circuit 1 to a DC level and removing noise, and a reference numeral 3 for an input signal A VCO 8 that oscillates by a fixed number, 8 is a frequency dividing circuit that divides the output pulse of VCO 3 for comparison with a horizontal synchronizing signal as an input signal, and 4 is a circuit that counts pulses output from VCO 3 and performs horizontal synchronization. A counter reset by the signal HD; 5 a memory for reading data stored in advance at the address using the count value output from the counter 4 as an address;
Is a latch circuit for temporarily holding data from the memory 5 at the timing of a pulse from the VCO 3, and 7 is a D / D for converting output data of the latch circuit 6 from digital to analog.
A converter.

Next, the operation will be described. First, an externally input horizontal synchronizing signal HD
And the feedback signal from the frequency divider 8 is compared. If the phases of both signals are different, DCF is applied by LPF2.
The voltage is corrected, and the voltage is input to the VCO 3 to control the output frequency. By the above feedback control, a pulse signal of a predetermined frequency is output as a clock.

The pulse signal serving as a clock causes the counter 4 to be incremented one by one. The previously stored data is read out from the memory 5 using the counter value at that time as an address, and the data is temporarily held by the latch circuit 6 and simultaneously stored in the memory 5.
/ A converter 7. Then, a waveform is generated by the D / A converter 7 and output to the drive circuit to be used as a horizontal control waveform. Here, when the input frequency greatly changes due to factors such as a change in the type of the computer to which the application is applied, a pulse signal having a specified frequency is obtained by switching between a resistor and a capacitor attached to the VCO 3.

[0005]

Since the conventional control waveform generation circuit is constructed as described above, it is necessary to provide a VCO with a plurality of types of capacitors and resistors and switch between them in order to cope with frequency changes. In order to cope with various frequencies, an increase in the number of parts and an increase in volume are inevitable. In addition, since it is an analog circuit, there is a problem that jitter is large, it is difficult to make an IC, and it is easily affected by noise.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a control waveform generating circuit capable of coping with a wide range of frequencies with a small number of components and a small space. .

[0007]

According to a first aspect of the present invention, there is provided a control waveform generating circuit comprising: a synchronizing circuit for synchronizing an input clock signal with a horizontal synchronizing signal; A frequency divider for dividing the clock signal by a plurality of different division ratios and outputting the same, a selector for selecting one of the clock signals from the divider and sending it to the counter, It is composed of a comparator that compares the value with a preset value and stops the input signal to the counter when the values become equal.

In a control waveform generating circuit according to a second aspect of the present invention, the pulse signal generating means receives the horizontal synchronizing signal as a clock signal, divides the clock signal by a plurality of different dividing ratios, and outputs the clock signal. A frequency divider, a selector for selecting one of the clock signals from the frequency divider and transmitting the clock signal to the counter, and comparing a count value from the counter with a preset value. It consists of a comparator that stops the input signal to the counter.

The control waveform generating circuit according to a third aspect of the present invention further receives a blanking signal for erasing the blanking of the scanning line, and writes the data into the memory on the condition that the blanking signal is present. It has a write permission circuit for permitting.

[0010]

In the control waveform generating circuit according to the first aspect,
The counter is operated by a signal obtained by dividing the frequency of the clock signal synchronized with the horizontal synchronization signal, and data stored in the memory is read from the output of the counter to generate a horizontal control waveform.

In a control waveform generating circuit according to a second aspect, a counter is operated by a signal obtained by dividing the frequency of a horizontal synchronizing signal, and data stored in a memory is read from an output of the counter to read a vertical control waveform. Generate

In the control waveform generating circuit according to the third aspect, since writing to the memory is performed during the output period of the blanking signal, the writing operation does not disturb the image display.

[0013]

【Example】

Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of a control waveform generation circuit according to Embodiment 1 of the present invention. In the figure, 4
7 to 7 are the same as or equivalent to those in the related art, and their individual descriptions are omitted. Reference numeral 9 denotes an input clock signal and a horizontal synchronizing signal H
A synchronizing circuit 10 for synchronizing with D. A frequency dividing circuit 10 divides the clock signal output from the synchronizing circuit 9 by a plurality of different dividing ratios and outputs the divided signal. A numeral 11 denotes an output from the frequency dividing circuit 10 by a clock select signal. A selector for selecting one clock signal from a plurality of clock signals to be generated; 12, a waveform shaping circuit for detecting a rising edge of the horizontal synchronizing signal HD to generate a signal having a fixed pulse width; and 13, a selector 11 and a waveform shaping circuit 12 And a NAND circuit 14 which operates using an output signal from a comparator 15 to be described later as an input. The NAND circuit 14 sets a count value calculated by a microcomputer based on the frequency of the horizontal synchronization signal HD and a clock select signal. The latch circuit 15 has a count value from the counter 4 and a count value set in the latch circuit 14. Compared to a comparator for outputting a signal that changes from "H" to "L" when they match.

Next, the operation will be described. FIG. 2 is a time chart for explaining the operation. The signals at points A to F in FIG. 1 are shown in FIGS. 2A to 2F, respectively. FIG. 2A shows an input reference clock signal.
It is a necessary high frequency signal. Note that, in this operation example, the selector 11 sets the frequency division ratio from the frequency division circuit 10 = 1.
Therefore, the output signal of the selector 11 is the same as that shown in FIG. FIG.
(B) is a horizontal synchronization signal HD, and (C) is a horizontal synchronization signal H.
A signal obtained from D through the waveform shaping circuit 12 and serves as a reset signal for the counter 4. (D) is the output signal of the comparator 15, (E) is the output signal of the NAND circuit 13, that is, the input signal of the counter 4, and (F) is the output signal of the counter 4, that is, the address signal to the memory 5. is there.

First, the microcomputer preliminarily sets the horizontal synchronization signal H
The frequency of D is counted, the optimum number of clocks for the frequency is calculated, the result is output to the selector 11 as a clock select signal, and the optimum clock signal is output by the frequency divider 10. . From the same calculation, the count value (for example, “F
F ") is set.

At time t ₀ in FIG. 2, the horizontal synchronizing signal H
When D (B) rises from "L" level to "H" level, the counter reset signal (C) falls from "H" level to "L" level. Therefore, the counter 4 is reset, and the value of the output signal (F) becomes “00”.
As a result, the count value of the count value and the counter 4 which is set in the latch circuit 14 becomes mismatched, at time t ₁ with a slight delay from time t _0, the output signal of the comparator 15 (D) is from the "L" level It changes to "H" level.

After time t ₂ , both the counter reset signal (C) and the comparator output signal (D) become “H”.
Level, and the NAND circuit 13 outputs a signal (E) obtained by inverting the clock signal from the selector 11. The signal (E) is counted by the counter 4, the count value is output in the form of a signal (F), and data having the value as an address is read from the memory 5. Memory 5
The data of the required horizontal control waveform is divided into a required number of data based on the cycle of the horizontal synchronizing signal HD and stored, and the latch circuit 6 converts the data stored in the memory 5 into the selector 11. , Latched at the rising edge of the clock signal, converted to an analog signal via the D / A converter 7, and output to the drive circuit. From the above,
It is possible to generate a control waveform of an arbitrary waveform having a constant peak value for an arbitrary frequency. Of course, it is also possible to change the peak value.

The counter 4 outputs a counter reset signal (C).
And the comparator output signal (D) continues the counting operation during the “H” level, but at time t ₃ when the set value of the latch circuit 14 and the count value of the counter 4 match, the output signal (D ) Goes from “H” level to “L” level, and the counting operation is stopped. Then, at time t ₄ , the horizontal synchronization signal HD (B) changes from “L” level to “H” level, and the operation after time t ₀ is repeated again.

As described above, in this embodiment, the frequency dividing circuit 10 is capable of outputting a required type of dividing ratio, thereby outputting a horizontal control waveform for an arbitrary frequency. Can be. In particular, since the stop operation for one cycle of the count is performed at the timing of the output of the comparator 15 described above, even if one cycle of the horizontal synchronizing signal HD does not become an exact integer multiple of the pulse width from the selector 11. In addition, the interval between the stop time and the next counter reset time absorbs a shift based on the two cycles, and promises a smooth operation. Further, since the pulse signal generation means 9 to 15 shown in FIG. 1 are all constituted by digital components, it is possible to form a gate array, and it is relatively easy to achieve a small and inexpensive device.

Embodiment 2 FIG. FIG. 3 is a block diagram showing a configuration of a control waveform generation circuit according to Embodiment 2 of the present invention. This generates a vertical control waveform. Here, the horizontal synchronizing signal HD is used as a clock signal in relation to the vertical synchronizing signal VD. Therefore, the synchronizing circuit 9 which is necessary in FIG. 1 becomes unnecessary. The counter 4 is of course reset by the vertical synchronizing signal VD. The other parts are the same as those in FIG. 1 and the description is omitted. However, as in the first embodiment, it is possible to cope with the generation of waveforms of various frequencies as they are, and furthermore, the miniaturization and cost reduction of the apparatus are further promoted. You.

Embodiment 3 FIG. FIG. 4 is a block diagram showing a configuration of a control waveform generation circuit according to Embodiment 3 of the present invention. The configuration is the same as that of FIG. 3 except that the write permission circuit 16 is provided. Here, writing and rewriting of data in the memory 5 are problematic. That is, as described above, the counter 4
The control waveform is generated by reading the data stored in advance in the memory 5 using the count value from the address as an address. For example, when the vertical deflection operation is actually performed by the output waveform based on the data obtained by the initial calculation, There may be a case where it is desired to partially correct the value of the data stored in the memory 5 in order to improve the obtained characteristics. In such a case, it is extremely convenient if the correction process can be performed during the image display operation.

The write permission circuit 16 of FIG. 4 realizes this problem. The write enable circuit 16 inputs a blanking signal generated for erasing blanking of a scanning line for displaying an image, and instructs writing. The access of the signal to the memory 5 is permitted only during the generation period of the blanking signal.

FIG. 5 is a timing chart showing the blanking signal. In response to the write signal from the microcomputer, if the instructed write processing is not completed within one blanking period of the blanking signal, the write signal is written. Permit circuit 1
Then, a stop signal is sent from the microcomputer 6 to the microcomputer, at which point the writing process is interrupted, unprocessed data is held, and the remaining process is continued in the next blanking period.
As described above, efficient waveform adjustment can be performed.

Embodiment 4 FIG. In the third embodiment, the case where the write permission circuit 16 is added to the vertical control waveform generation circuit of FIG. 3 has been described. However, the write permission circuit 16 is naturally added to the horizontal control waveform generation circuit of FIG. It is possible and has the same effect.

[0025]

Since the present invention is configured as described above, even if the target frequency changes, it can be dealt with simply by changing the software by the same device, and furthermore, since the digital processing is performed, the gate array and the like can be used. Miniaturization is easy and cost reduction is possible. Further, by providing the predetermined write permission circuit, the memory can be rewritten during the image display operation, and the efficiency of this operation can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a control waveform generation circuit according to Embodiment 1 of the present invention.

FIG. 2 is a time chart for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a block diagram showing a configuration of a control waveform generation circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a control waveform generation circuit according to Embodiment 3 of the present invention.

FIG. 5 is a timing chart for explaining the operation of the circuit of FIG. 4;

FIG. 6 is a block diagram illustrating a configuration of a conventional control waveform generation circuit.

[Explanation of symbols]

 4 Counter 5 Memory 6, 14 Latch circuit 7 D / A converter 9 Synchronization circuit 10 Divider circuit 11 Selector 15 Comparator 16 Write enable circuit HD Horizontal synchronization signal VD Vertical synchronization signal

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yu Tateishi 4-4 Maruomachi, Nagasaki City Mitsubishi Electric Control Software Co., Ltd. Nagasaki Office (56) References JP-A-5-66753 (JP, A) ( 58) Field surveyed (Int.Cl. ⁶ , DB name) G09G 5/12 G09G 5/18 H04N 3/16

Claims (3)

(57) [Claims] 1. A pulse signal generating means for receiving a horizontal synchronizing signal and generating a pulse signal of a predetermined frequency synchronized with the horizontal synchronizing signal, a counter for counting the pulse signal and resetting by the horizontal synchronizing signal, A memory that reads data stored in advance at the address using the count value of the address as a address, a latch circuit that temporarily holds data from the memory at the timing of the pulse signal, and converts the data of the latch circuit from digital to analog In a control waveform generating circuit having a D / A converter, a pulse signal generating means includes: a synchronizing circuit for synchronizing an input clock signal and the horizontal synchronizing signal; a plurality of frequency dividing ratios different from each other; A frequency divider circuit that divides and outputs a clock signal. Selector to be sent to the counter by selecting or Re,
And a comparator for comparing a count value from the counter with a preset value and stopping an input signal to the counter when the values are equal to each other. 2. A pulse signal generating means for receiving a vertical synchronizing signal and generating a pulse signal having a predetermined frequency synchronized with the vertical synchronizing signal, a counter counting the pulse signals and resetting by the vertical synchronizing signal. A memory for reading data stored in advance at the address using the count value from the memory as an address, a latch circuit for temporarily holding data from the memory at the timing of the pulse signal, and converting the data of the latch circuit from digital to analog A pulse signal generating means for inputting a horizontal synchronization signal as a clock signal, dividing the clock signal by a plurality of different division ratios, and outputting the divided clock signal. Select one of the clock signals from the frequency dividing circuit and send it to the counter. Selectors, and control waveform generating circuit characterized by comprising a comparator for stopping the input signals of both by comparing the preset value with the count value from the counter to the counter when the equal. 3. A control waveform output circuit comprising: a blanking signal for erasing a blanking of a scanning line; and a write enable circuit for allowing writing to a memory on the condition of the presence of the blanking signal. 3. The control waveform generation circuit according to claim 1, wherein the data in the memory can be rewritten during an image display operation based on the control waveform.