JPH06186947A - Control waveform generation circuit - Google Patents

Abstract

PURPOSE:To deal with the change in an input frequency with a circuit of simple constitution in the circuit generating a horizontal control waveform for a horizontal deflection circuit, etc., in a display monitor. CONSTITUTION:This circuit is provided with a synchronous circuit 9 synchronizing an inputted clock signal with an inputted horizontal synchronizing signal HD, a frequency divider circuit 10 frequency-dividing and outputting the clock signal from the synchronous circuit 9 at plural frequency division ratios different from each other, a selector 11 selecting any signal of the clock signals from the frequency divider circuit 10 and sending to a counter 4 and a comparator 15 comparing the count value from the counter 4 with a prescribed value and interrupting an input signal to the counter 4 when both values become equal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating various control waveforms for controlling a display monitor.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing the structure of a conventional control waveform generating circuit of this type. In the figure, reference numeral 1 denotes the input horizontal synchronizing signal HD and a voltage control generation circuit VC described later.
A phase comparison circuit 2 for comparing the phase with the feedback signal frequency-divided from the O3 output, 2 is a low-pass filter LPF for converting the pulse output from the phase comparison circuit 1 to a DC level to remove noise, and 3 is based on the input signal. A VCO that oscillates a fixed number of oscillations, 8 is a frequency divider circuit that divides the output pulse of the VCO 3 for comparison with the horizontal synchronization signal that is an input signal, and 4 is a horizontal synchronization signal that counts the pulses output from the VCO 3 A counter reset by the signal HD, 5 is a memory for reading data stored in advance at the address, using the count value output from the counter 4 as an address, 6
Is a latch circuit for temporarily holding the data from the memory 5 at the timing of the pulse from the VCO 3, and 7 is D / for converting the output data of the latch circuit 6 from digital to analog.
It is an A converter.

Next, the operation will be described. First, the phase comparison circuit 1 outputs a horizontal synchronization signal HD input from the outside.
And the feedback signal from the frequency dividing circuit 8 are compared. When the phases of both signals are different, DC is
The voltage is corrected, the voltage is input to the VCO 3, and the output frequency is controlled. With the above feedback control, a pulse signal of a predetermined frequency is output as a clock.

The pulse signal used as the clock causes the counter 4 to be incremented by one. Data stored in advance is read from the memory 5 by using the counter value at that time as an address and is temporarily held by the latch circuit 6 and at the same time D
It is input to the / A converter 7. Then, the D / A converter 7 generates a waveform and outputs the waveform to the drive circuit, which is used, for example, to generate a horizontal deflection output. here,
When the input frequency changes significantly due to factors such as the type of computer to which it is applied, the pulse signal of the specified frequency can be obtained by switching the resistor and capacitor attached to the VCO 3.

[0005]

Since the conventional control waveform generating circuit is configured as described above, it is necessary to provide a VCO with a plurality of types of capacitors and resistors to switch between them in order to cope with a change in frequency. However, when trying to cope with many kinds of frequencies, an increase in the number of parts and an increase in volume cannot be avoided. Further, since it is an analog circuit, there is a problem that it has a large jitter, is difficult to be integrated into an IC, and is easily affected by noise.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a control waveform generating circuit capable of supporting a wide range of frequencies with a small number of parts and a small space. .

[0007]

According to a first aspect of the present invention, there is provided a control waveform generating circuit for synchronizing a pulse signal generating means between an input clock signal and a horizontal synchronizing signal. A frequency divider circuit that divides and outputs a clock signal with a plurality of different frequency division ratios, a selector that selects one of the clock signals from the frequency divider circuit and sends it to a counter, and a count value from the counter. It is composed of a comparator which compares a preset value with each other and stops the input signal to the counter when both are equal.

In the control waveform generating circuit according to a second aspect of the present invention, the pulse signal generating means receives the horizontal synchronizing signal as a clock signal, divides the clock signal by a plurality of frequency division ratios different from each other, and outputs the divided frequency. Frequency dividing circuit, a selector for selecting any one of the clock signals from the frequency dividing circuit and sending it to the counter, and comparing the count value from the counter with a preset value, and when both are equal, the above It is composed of a comparator that stops the input signal to the counter.

The control waveform generating circuit according to a third aspect of the present invention further inputs a blanking signal for erasing the blanking of the scanning line, and writes to the memory on condition that the blanking signal exists. It is provided with a write permission circuit for permitting.

[0010]

In the control waveform generating circuit according to the first aspect,
The counter is operated by the signal obtained by dividing the frequency of the clock signal synchronized with the horizontal synchronizing signal, and the data stored in the memory is read from the output of the counter to generate the horizontal control waveform.

In the control waveform generating circuit according to the second aspect, the counter is operated by the signal obtained by dividing the vertical synchronizing signal, and the data stored in the memory is read from the output of the counter and the vertical control waveform is generated. To generate.

In the control waveform generating circuit according to the third aspect, since the writing is performed in the memory during the blanking signal output period, the image display is not disturbed by the writing operation.

[0013]

【Example】

Example 1. 1 is a block diagram showing the configuration of a control waveform generation circuit according to a first embodiment of the present invention. In the figure, 4
7 to 7 are the same as or equivalent to the conventional ones, and individual explanations are omitted. 9 is the input clock signal and horizontal synchronization signal H
A synchronizing circuit for synchronizing with D, 10 is a frequency dividing circuit for dividing the clock signal output from the synchronizing circuit 9 by a plurality of frequency division ratios different from each other, and outputting the same, and 11 is output from the frequency dividing circuit 10 by a clock select signal. A selector for selecting one clock signal from a plurality of clock signals to be generated, a waveform shaping circuit 12 for detecting a rising edge of the horizontal synchronizing signal HD and generating a signal having a constant pulse width, a selector 11, a waveform shaping circuit 12 A NAND circuit that operates by using an output signal from a comparator 15 described later as an input, and 14 sets a count value calculated by a microcomputer (hereinafter, referred to as a microcomputer) based on the frequency of the horizontal synchronizing signal HD and a clock select signal. The latch circuit, 15 indicates the count value from the counter 4 and the count value set in the latch circuit 14. Compared to a comparator for outputting a signal that changes from "H" to "L" when they match.

Next, the operation will be described. FIG. 2 is a time chart for explaining the operation. The signals at points A to F in FIG. 1 are shown in FIGS. 2 (A) to 2 (F), respectively. FIG. 2A shows an input reference clock signal,
It has the required high frequency signal. In this operation example, the selector 11 outputs the frequency division ratio from the frequency dividing circuit 10 to 1
The clock signal is selected according to the above, and therefore the output signal of the selector 11 is also the same as that shown in FIG. Figure 2
(B) is a horizontal synchronizing signal HD, and (C) is a horizontal synchronizing signal H.
It is a signal obtained from D through the waveform shaping circuit 12 and serves as a reset signal for the counter 4. The same (D) is the output signal of the comparator 15, the same (E) is the output signal of the NAND circuit 13, therefore the input signal of the counter 4, and the same (F) is the output signal of the counter 4, therefore the address signal to the memory 5. is there.

First of all, the microcomputer preliminarily detects the horizontal synchronizing signal H.
The frequency of D is counted, the optimum number of clocks for the frequency is calculated, the result is output to the selector 11 as a clock select signal, and the optimum clock signal is set to be output by the frequency dividing circuit 10. . Further, the count value “FF” is set in the latch circuit 14 from the similar calculation.

At time t ₀ in FIG. 2, the horizontal synchronizing signal H
When D (B) rises from "L" level to "H" level, the counter reset signal (C) falls from "H" level to "L" level. Therefore, the counter 4 is reset and the value of its output signal (F) becomes "00".
As a result, the count value of the count value and the counter 4 which is set in the latch circuit 14 becomes mismatched, at time t ₁ with a slight delay from time t _0, the output signal of the comparator 15 (D) is from the "L" level Changes to "H" level.

After time t ₂ , both the counter reset signal (C) and the comparator output signal (D) are "H".
As a result, the NAND circuit 13 outputs the signal (E) obtained by inverting the clock signal from the selector 11. The counter 4 counts this signal (E), the count value is output in the form of a signal (F), and the data having the value as an address is read from the memory 5. Memory 5
The necessary horizontal control waveform data is stored by dividing the data into the required number of data based on the period of the horizontal synchronizing signal HD, and the latch circuit 6 selects the data stored in the memory 5 from the selector 11 The clock signal is latched at the rising edge of the clock signal, converted to an analog signal through the D / A converter 7, and output to the drive circuit. From the above,
It is possible to generate a control waveform having an arbitrary waveform with a constant peak value for an arbitrary frequency. Of course, it is also possible to change the peak value.

The counter 4 has a counter reset signal (C).
And the comparator output signal (D) continue to count while both are at the “H” level, but at time t ₃ when the set value of the latch circuit 14 and the count value of the counter 4 match, the output signal (D ) Changes from "H" level to "L" level and the counting operation is stopped. Then, at time t ₄ , the horizontal synchronizing signal HD (B) changes from the “L” level to the “H” level, and the operation after the previous time t ₀ is repeated again.

As described above, in this embodiment, the frequency dividing circuit 10 is configured to be capable of outputting with a necessary type of frequency division ratio, so that the horizontal control waveform can be output for an arbitrary frequency. You can Especially, since the stop operation for one cycle of counting is performed at the timing of the output of the comparator 15 described above, even if one cycle of the horizontal synchronizing signal HD is not an exact integral multiple of the pulse width from the selector 11. In addition, the interval between the stop time and the next counter reset time absorbs the deviation based on the both cycles and promises a smooth operation. Further, since the pulse signal generating means 9 to 15 shown in FIG. 1 are all composed of digital parts, it is possible to form a gate array, and it is relatively easy to achieve a compact and inexpensive device.

Example 2. 3 is a block diagram showing the configuration of a control waveform generation circuit according to the second embodiment of the present invention. This generates a vertical control waveform, and here the horizontal synchronizing signal HD is used as a clock signal in relation to the vertical synchronizing signal VD. Therefore, the synchronizing circuit 9 required in FIG. 1 is not necessary. The counter 4 is of course reset by the vertical synchronizing signal VD. Others are the same as in the case of FIG. 1, so description thereof will be omitted, but as in the first embodiment, it is possible to directly cope with waveform generation of various frequencies, and further downsizing and cost reduction of the apparatus are further promoted. It

Example 3. Fourth Embodiment FIG. 4 is a block diagram showing the configuration of a control waveform generating circuit according to a third embodiment of the present invention. The configuration is the same as that of FIG. 3 except that the write permission circuit 16 is provided. Here, writing and rewriting of data in the memory 5 is a problem. That is, as described above, the counter 4
The data stored in advance in the memory 5 is read by using the count value from the address as the address to generate the control waveform. However, when the vertical deflection operation is actually performed by the output waveform based on the data obtained by the initial calculation, There may be a case where it is desired to partially modify the value of the data stored in the memory 5 in order to improve the obtained characteristics. In such a case, it would be extremely convenient if this correction process could be performed during the image display operation.

The write enable circuit 16 shown in FIG. 4 realizes this problem, and a write command is issued by inputting a blanking signal generated to erase the blanking of the scanning lines for image display. The access of the signal to the memory 5 is permitted only during the generation period of the blanking signal.

FIG. 5 is a timing chart showing the blanking signal. When the write signal instructed by the microcomputer does not end within one blanking period of the blanking signal, the write signal is written. Permission circuit 1
A stop signal is sent from 6 to the microcomputer, the writing process is interrupted at that point, unprocessed data is held, and the remaining process is continued in the next blanking period.
As described above, efficient waveform adjustment work can be performed.

Example 4. In the third embodiment, the case where the write permission circuit 16 is added to the vertical control waveform generation circuit of FIG. 3 has been described, but it goes without saying that the write permission circuit 16 is added to the horizontal control waveform generation circuit of FIG. It is possible and has the same effect.

[0025]

Since the present invention is configured as described above, even if the target frequency changes, it can be dealt with as it is by only changing the software by the same device, and because of the digital processing, the gate array, etc. Miniaturization is easy and cost can be reduced. Further, by providing a predetermined write permission circuit, the memory can be rewritten during the image display operation, and the efficiency of this work can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a control waveform generation circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the circuit of FIG.

FIG. 3 is a block diagram showing a configuration of a control waveform generation circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a control waveform generation circuit according to a third embodiment of the present invention.

5 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 6 is a block diagram showing a configuration of a conventional control waveform generation circuit.

[Explanation of symbols]

 4 counter 5 memory 6, 14 latch circuit 7 D / A converter 9 synchronization circuit 10 frequency divider circuit 11 selector 15 comparator 16 write enable circuit HD horizontal synchronization signal VD vertical synchronization signal

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[Procedure amendment]

[Submission date] May 13, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

The pulse signal used as the clock causes the counter 4 to be incremented by one. Data stored in advance is read from the memory 5 by using the counter value at that time as an address and is temporarily held by the latch circuit 6 and at the same time D
It is input to the / A converter 7. Then, a waveform is generated by the D / A converter 7 and output to the drive circuit for use as a horizontal control waveform. Here, when the input frequency changes greatly due to a change in the type of computer to which it is applied, a resistor and a capacitor attached to the VCO 3 are switched to obtain a pulse signal of a specified frequency.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

In the control waveform generating circuit according to the second aspect of the present invention, the counter is operated by the signal obtained by dividing the horizontal synchronizing signal, and the data stored in the memory is read from the output of the counter and the vertical control waveform is generated. To generate.

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (3)

[Claims] 1. A pulse signal generating means for inputting a horizontal synchronizing signal to generate a pulse signal of a predetermined frequency synchronized with the horizontal synchronizing signal, a counter for counting the pulse signal and resetting with the horizontal synchronizing signal, from this counter. A memory for reading the data stored in advance at the address using the count value of the memory, a latch circuit for temporarily holding the data from the memory at the timing of the pulse signal, and the data of the latch circuit is converted from digital to analog. In the control waveform generating circuit including a D / A converter, the pulse signal generating means includes a synchronizing circuit for synchronizing the input clock signal and the horizontal synchronizing signal, and a plurality of frequency division ratios for different clock signals from the synchronizing circuit. A frequency divider circuit that divides the frequency by and outputs the clock signal from this frequency divider circuit. Selector to be sent to the counter by selecting or Re,
And a comparator for comparing a count value from the counter with a preset value and stopping an input signal to the counter when the two values are equal to each other. 2. A pulse signal generating means for inputting a vertical synchronizing signal and generating a pulse signal of a predetermined frequency synchronized with the vertical synchronizing signal, a counter for counting the pulse signals and resetting with the vertical synchronizing signal, and this counter. A memory that reads the data stored in advance at the address using the count value from the memory, a latch circuit that temporarily holds the data from the memory at the timing of the pulse signal, and the data in this latch circuit is converted from digital to analog. In the control waveform generating circuit including the D / A converter, the pulse signal generating means inputs a horizontal synchronizing signal as a clock signal and divides the clock signal by a plurality of frequency division ratios different from each other to output the divided frequency. , Select one of the clock signals from this divider and send it to the counter Selectors, and control waveform generating circuit characterized by comprising a comparator for stopping the input signals of both by comparing the preset value with the count value from the counter to the counter when the equal. 3. A control waveform output by providing a write enable circuit for inputting a blanking signal for erasing a blanking line of a scanning line and permitting writing to a memory on condition of the presence of the blanking signal. 3. The control waveform generating circuit according to claim 1, wherein the data in the memory can be rewritten during the image display operation based on the above.