JP2880012B2 - Digital convergence device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital convergence apparatus for correcting a color shift of a CRT type color image receiving device.

[0002]

2. Description of the Related Art FIG. 14 shows an example of the configuration of a digital convergence device in a multi-scan type three-tube video projector. In the drawing, reference numeral 1 denotes an input terminal for correction data, and 2 denotes an address for writing correction data to a memory. Input terminal 3, memory for storing convergence correction data, 4 serial-parallel conversion circuit for converting serial data for 6 channels (hereinafter referred to as 6CH) read from the memory into parallel data for 6CH, 5 serial-parallel conversion circuit D / A converters for converting digital data output from 4 into analog correction signals, 6 to 8 are low-pass filters (hereinafter referred to as LPFs), 9 is a selector for selecting LPFs 6 to 8, and 10 is amplifying the correction signals. Amplifier, 11
Is a convergence yoke for applying a correction magnetic field to the electron beam of the receiver, and 12 is D / A per correction signal CH.
The conversion blocks 13 to 17 are the same as the D / A conversion block 12, respectively. 18 to 22 are convergence yokes that are the same as the convergence yoke 11, 23 is an input terminal for an erase pulse (hereinafter, referred to as an H-BLK pulse) during a horizontal retrace period, 24 is an input terminal for a window signal for measuring a horizontal frequency, 25 is an input terminal of an erase pulse (hereinafter, referred to as V-BLK pulse) during a vertical blanking period, 26 is a phase comparator, 27 is a loop filter, 28 to 30 are voltage controlled oscillators (hereinafter, VCO), 31 is VCO
A selector for selecting 28 to 30; 32, a horizontal frequency detecting circuit for detecting an input horizontal frequency by an H-BLK pulse input from the input terminal 23; 33, based on information obtained by the detecting circuit of the horizontal frequency detecting circuit 32; , 31 are circuits for generating control signals for controlling the selectors.
Is a horizontal address generating circuit for adjusting points for reading out the correction data stored in the memory, and 35 is a vertical address generating circuit.

Next, the operation will be described. When a CRT projector projects a signal source whose input horizontal frequency (fH) changes from 15 KHz to 150 KHz, three colors of red (R), green (G), and blue (B) are displayed on the screen. There is a digital convergence method for color matching with accuracy.

As shown in FIG. 15, when the adjustment points of digital convergence are 32 points in the horizontal direction and 16 points in the vertical direction, the correction data in one horizontal scanning period (1H) is R, G per adjustment point. , B are moved in the horizontal and vertical directions to perform color matching, so that a total of 6 CHs (RH, RV, GH, GV, BH, B
V) minutes.

In order to process this correction data in series, a clock that is six times as long as one adjustment point interval is required. If this clock is fs, fs is as follows. fs = nH × 6 × fH (Hz) Expression 1 where nH is the number of horizontal adjustment points fH is the horizontal scanning frequency FIG. 16 is a timing chart showing the above relationship.
fs = 192 · fH.

Next, FIG. 14 will be described. The input terminals 1 and 2 are connected to an external data writing device, from which correction data for correcting color misregistration is written to the memory 3. The correction data stored in the memory 3 is
The data is read out in synchronization with the horizontal and vertical main deflections of the projector, and is converted into parallel data of 6CH by the serial / parallel conversion circuit 4. Of these, the red horizontal correction data (RH) enters the D / A converter 5. After being converted to analog signals, interpolation between adjustment points is performed through LPFs 6 to 8, the output of the LPF is selected by the selector 9, and the output of the selector 9 is amplified by the amplifier 10, and then the convergence yoke 1
In step 1, color shift is corrected. RV, GH, GV, BH, BV
, D / A conversion block 12
After passing through the same blocks 13 to 17 as above, color misregistration correction is performed by the Yombesence yokes 18 to 22.

Next, the read address control of the correction data memory will be described. The phase comparator 26 compares the phase of the horizontal scanning reference signal input from the input terminal 23 with the comparison pulse (HP) obtained by dividing fs by 192, and the error is converted into a voltage and output. This voltage is applied to the loop filter 27
And is input to the VCOs 28 to 30. The VCO changes the oscillation frequency with respect to the input error voltage (VI) and oscillates. Only the output of the VCO selected by the selector 31 becomes the system clock of the horizontal address generation circuit 34. The horizontal address generation circuit 34 is constituted by a 192 counter, counts up by fs, outputs a reset pulse (HP) after 192 counts, and is reset. Since the phases of the HP and the H-BLK input from 23 are compared, fs is always 192 times the H-BLK, that is, fH
192 times the frequency of Therefore, the correction data is always read at 192 times fH.

Here, the input horizontal frequency (fH) is 1
If you have changed to 5KHz~150KHz, fs is 192 times of fH, that is 2.88MHz~28.8MHz
Must be controlled in a wide range of oscillation frequency range for the error voltage output from the 26 of the phase comparator is very wide, less favorable In terms of stability of the oscillator. Therefore, 2.88 MHz to 28.8 M
Hz range divided into 3.88 MHz to 11.52 MH
28 VCO1, 11.53 MHz to 20.1 for z
29 VCO2 for 20MHz, 20.17MHz ~ 2
Allocate 30 VCOs for 8.8 MHz. As a result, the oscillation frequency range of one VCO is 8.64 MHz.
Is within the allowable range. This switching of the VCO is performed by detecting the input horizontal frequency, fH is 0 Hz to 51 KHz,
52KHz ~ 102KHz, 103KHz ~ 153KH
Perform in the range of z. As described above, the correction data is fs
, The LPF characteristics in the twelve blocks need to be linearly varied, but here, L
Switch between three types of PF.

Next, a horizontal frequency detection circuit and a VCO
And a control circuit of the LPF will be described. FIG. 17 shows an example of an input horizontal frequency detection circuit and a VCO control circuit. In the figure, reference numeral 32 denotes an 11-bit up counter which counts the number of H-BLKs during a window signal (TW) of a positive polarity. The up counter 32 has a maximum of 204
Up to 8 counts are possible. For example, if TW is set to 10 ms, the actual frequency is 100 times the value counted during the TW period, and fH can be counted from 0 Hz to 204.8 KHz. This output is decoded in a predetermined frequency range by a decode circuit 33, and select signals (SEL1, SE
L2, SEL3). These results are summarized in Table 1. In this table, "H" is logic 1 and "L" is O
Is shown.

[0010]

[Table 1]

FIG. 18 is a graph showing the relationship between the control voltage (VI) input to the VCOs 28 to 30 and the oscillation frequency of each VCO. As can be seen from this graph, one VCO covers an oscillation frequency range of about 10 MHz,
For example, when the oscillation frequency (fs) is to be controlled within ± 1%, the control voltage is at worst ± 12 mV, requiring very high-precision voltage control, and is a system that is weak against noise.

FIG. 19 shows the characteristics of the LPF after D / A conversion switched by the select signal. LPF1,
The characteristics of LPF2 and LPF3 are VCO1 and VCO, respectively.
2, the ideal characteristic is set at the center frequency at which the VCO 3 oscillates, and the wider the oscillation frequency range of each VCO is, the more the LPF deviates from the ideal characteristic.

[0013]

The digital convergence device in the conventional multi-scan video projector is constructed as described above, and the VCO and the LPF after D / A must be switched according to the input horizontal frequency. However, there is a problem that the accuracy is insufficient and the circuit scale becomes very large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is not necessary to switch the VCO and the LPF after D / A even if the input horizontal frequency to the receiver changes over a wide range. It is an object of the present invention to provide a digital convergence device that can realize high-precision digital convergence with a minimum circuit size and a small correction data memory, and that an LPF is always optimal for a convergence correction data rate.

[0015]

A digital convergence apparatus according to the present invention comprises a means for detecting a horizontal frequency input to a receiver, and a plurality of means for interpolating convergence correction data in real time for one horizontal period. An interpolation filter, a selector for switching between a plurality of interpolation filters, and a means for controlling the selector, controlling an adjustment point of digital convergence that does not exist on the memory according to the detected horizontal frequency, When the number of controlled adjustment points is an integral multiple of a predetermined number of adjustment points, an interpolation filter for performing interpolation data interpolation calculation in a horizontal cycle is switched.

[0016]

Furthermore, of the correction data for one horizontal period,
The correction data in the horizontal retrace period is obtained by interpolation from the correction data in the scanning period, and an interpolation filter used for the interpolation is switched according to the input horizontal frequency.

[0018]

The horizontal interpolation filter according to the present invention calculates data for interpolating between the convergence correction data stored in the memory in real time.

The selector in the present invention selects the output of a predetermined horizontal interpolation filter according to the input horizontal frequency.

The horizontal blanking period correction data creating circuit according to the present invention creates convergence correction data of the horizontal blanking period from the correction data of the scanning period according to the input horizontal frequency.

[0021]

[Embodiment 1] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of a digital convergence device according to this embodiment. In FIG. 1, reference numeral 1 denotes an input terminal for correction data, 2 denotes an address input terminal for writing correction data to a memory, and 3 denotes convergence correction data. A memory for storing, 4 is a serial-parallel conversion circuit for converting 6CH serial data read from the memory into parallel data for 6CH, and 51 is an interpolating data between the correction data output from the serial-parallel conversion circuit 4 and the correction data. , A selector 52 for selecting the output of the horizontal interpolation filter, 5 a D / A converter for converting the digital data selected by the selector 52 into an analog correction signal, 40 a low-pass filter, 10 a correction An amplifier for amplifying the signal, 11 is a convergence yoke, and 53 is water for one correction signal Correction blocks after interpolation, 54 to 58 are the same blocks as the correction block 53, 18 to 22 are convergence yokes the same as the convergence yoke 11, 23 is an input terminal of a video blanking pulse during a horizontal retrace period, and 24 is a horizontal frequency. Is a window signal input terminal for measuring a vertical blanking period, 25 is a PLL circuit that generates a clock synchronized with H-BLK, and 34 is a correction stored in the memory 3. A horizontal address generation circuit for adjusting points for reading data, 35 is a vertical address generation circuit, 32 is a horizontal frequency detection circuit, 48 is a horizontal address generation circuit control circuit, and 50 is a horizontal interpolation filter control circuit.

Next, the operation will be described. For Figure 1, the input terminals 1 and 2 is connected to a data writing device external, correction data for correcting the color shift from here are written in the memory 3. The correction data stored in the memory 3 is read out in synchronization with the horizontal and vertical main deflections of the projector, and is converted by the serial-parallel conversion circuit 4 into parallel data of 6CH. R
For H), the horizontal interpolation filter 51, 1 the correction data between the horizontal <br/> period, new correction data correlated with the memory data between the correction data and the next correction data read from the memory Is interpolated. The interpolation filter has a plurality of outputs according to the input horizontal frequency to the projector, and the selector 52 selects the output of the horizontal interpolation filter 51. The selected digital data is D /
After entering the A converter 5 and being converted to an analog signal,
Interpolation between horizontal adjustment points is performed through the LPF 40, amplified by the amplifier 10, and corrected for color misregistration by the convergence yoke 11. Similarly, RV, GH, GV, BH, and BV are the same as the correction blocks 53, respectively.
After passing through 58, the convergence yokes 18 to 22 correct the color misregistration.

Next, read address control of the correction data memory will be described. Reference signal of the horizontal scanning inputted from the input terminal 23 (hereinafter, referred to as H-BLK) PLL N times the clock fs horizontal frequency synchronized with the (fH)
Generated by the circuit 49, system of the horizontal address generating circuit 34
For an indefinite clock. This horizontal address generating circuit 34
It is composed of an N-ary counter, counts up by fs, outputs a load pulse (HP) after N counts, and is preset. Since the phase of this HP is compared with that of the H-BLK input from the input terminal 23, fs is always fH
Becomes N times the oscillation frequency of Therefore, the correction data is always read at a data rate N times fH.
If this fs is always constant irrespective of the change in the input horizontal frequency, or if the range of change is very small with respect to the center frequency of the VCO oscillation of the PLL circuit, the VCO or D / A
There is no need to switch the LPF later.

Next, a method for keeping the reading rate of the correction data substantially constant irrespective of the input horizontal frequency will be described. Now, assuming that the input horizontal frequency changes from 15 KHz to 150 KHz, the frequency is measured by 32 horizontal frequency detection circuits, and based on the result, a predetermined control value is supplied to 34 horizontal address generation circuits by 48 address control circuits. give.

FIG. 2 shows an example of the frequency detection circuit and the address control circuit. In the figure, reference numeral 32 denotes an 11-bit up counter, which is H-B during a window signal (TW) of a positive polarity.
Count the number of LKs. The counter 32 has a maximum of 204
Up to 8 counts are possible. For example, if TW is set to 10 ms, 100 times the value counted during the TW period becomes the actual frequency, and fH can be measured from 0 Hz to 204.8 KHz. In this embodiment, fs = 6 × nH × fH,
(Where nH is the number of horizontal adjustment points), and to keep fs constant, change nH to nH = fs with respect to a change in fH.
/ (6 · fH).

Since the horizontal address generating circuit is composed of an 11-bit counter, the number of adjustment points can be controlled by controlling the start offset value (P) of the counter. This value (P) is given by the following equation. FH measured by the counter 32 value of fH to ROM482 held by latches circuit 481 is output. ROM4
At 82, an inverted output of fs / fH with respect to the input fH is output and enters the adding circuit 483. 483 of addition result P becomes a value satisfying Equation 2, using the P, controls the horizontal adjustment point add-less.

Now, if fs = 21.6 MHz is set,
The desired control value P is P = 2047-21.6 × 10 ⁶ / f
H (Hz), which is the value shown in the graph of FIG. However, since the frequency division ratio N = 6 · nH is an integer, f
s is not constant and has a certain width.

Next, horizontal data interpolation will be described. As described above, among the 1H adjustment points set according to the input horizontal frequency fH, the minimum adjustment point is 24 points, the maximum adjustment point is 240 points, and the adjustment points during the 1H period stored in the memory of 3 are 24 points. If the number of adjustment points is n times the number of 24 points, 24 × n correction data are interpolated. When n is an integer, n is 1 to 9. The state of the data at this time is shown in FIG.

FIG. 5 is a block diagram of the horizontal interpolation filter. In the figure, F101 to F918 are interpolation filters,
fSD is a data rate of correction data per CH, and has a relationship of fSD = 24 · fH. n = 1, i.e., when interpolating one data between data read from the memory, between該補 is the output of the interpolation filter F101,
It carried out by switching a direct output and an output of the interpolation filter F102 in switch 511. By performing this switching at the timing of 2 · fSD, the selector 52
, Correction data at the 2 · fSD rate subjected to data interpolation is input.

Hereinafter, similarly when n = 2 to 9, f
The correction data of the SD rate is obtained by interpolation filters F201 to F9.
After entering the switch 18 and passing the switches 512 to 519, the selector 52 enters B to J of the selector 52.

FIG. 6 shows the configuration of the interpolation filter when n = 2 among the above filters. The correction data input at fSD is delayed by D flip-flops 5101 to 5103, and their outputs are output from coefficient ROMs 5014 to 5024.
After adding predetermined coefficients, adders 5025 to 50
28, and the output is switched by the switch 512 and output.

Next, the selector 52 for selecting a horizontal interpolation filter will be described. FIG. 7 is an example of a horizontal frequency detection circuit and a control circuit of an interpolation filter in the present embodiment. In the figure, reference numeral 32 denotes an 11-bit up counter, which counts the number of H-BLK signals during a positive window signal (TW). This kautan can be up to 2048 counts. For example, if TW is set to 10 ms,
The actual horizontal frequency is 100 times counted during the TW period, and fH can be measured from 0 Hz to 204.8 KHz. The output of the counter 32 is latched by the D flip-flop 501 and input to the ROM 502. ROM 502
Then, a 4-bit control signal is output for the measured fH, and the selector of the interpolation filter is switched by this output. FIG. 8 shows the relationship between the control signal S, the horizontal frequency fH, and the output (S) of the selected filter.

Next, the correction data for the horizontal flyback period will be described. FIG. 9 shows a screen created by scanning. The hatched portion in the figure is a blanking period of the scanning and there is no video signal. FIG. 10 shows the state of the correction data before and after the retrace period. It is necessary to interpolate the correction data (memory data) of the n-th line and the correction data of the (n + 1) -th line from the data in the scanning period, but if the number of memory data in one horizontal period is fixed, However, if the value is changed in accordance with the input horizontal frequency, the number of correction data in the retrace period also changes, so this data is interpolated.
It is also necessary to switch the filter for this. FIG. 11 shows a simple configuration of a block for creating correction data to be written into the memory. The correction data for the video period is input from the terminal 601, and the horizontal blanking period correction data generation circuit 603 receives the data from the synthesis circuit 602. Horizontal scanning reference signal (HD)
Based on, create correction data blanking interval, the adder 604
In, interpolated to the input data that created the data from the terminal 601, and outputs a memory write write data only.

With the above digital convergence device, the oscillation frequency of the VCO in the PLL,
The data rate of the correction data has characteristics as shown in FIG. In the figure, the oscillation frequency may be ± 2% of the center frequency with respect to the control voltage of the VCO of 4 V, so that highly accurate control is possible.

Embodiment 2 FIG. FIG. 13 shows another embodiment of the present invention. In the above embodiment, the horizontal interpolation filter 51
And the selector 52 are provided after the serial-parallel data conversion circuit 4, but may be provided after the correction data memory.
The clock for the interpolation operation is performed at a rate six times that of the first embodiment. In this embodiment, only one set of horizontal interpolation filters is required, which is more advantageous than the first embodiment in terms of circuit scale.

[0036]

As described above, according to the present invention, the number of convergence adjustment points that do not exist in the memory is controlled according to the horizontal input frequency, and the correction data is adjusted by the horizontal interpolation filter. Is interpolated, so that the data stored in the memory and the position of the adjustment point on the screen are always constant regardless of the horizontal water wave number. In addition, since an output of a predetermined horizontal interpolation filter is selected and interpolated in accordance with the input horizontal frequency, it is not necessary to switch the LDF after D / A, and a digital convergence device with a small circuit scale can be obtained. effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a digital convergence device according to one embodiment of the present invention.

FIG. 2 is a diagram showing a horizontal frequency detection circuit and an address control circuit according to the present invention.

FIG. 3 is a graph showing an address control value in the present invention.

FIG. 4 is a diagram illustrating data interpolation of a horizontal interpolation filter according to the present invention.

FIG. 5 is a configuration diagram of a horizontal interpolation filter according to the present invention.

FIG. 6 is a configuration diagram of an interpolation filter.

FIG. 7 is a diagram showing a control circuit of a selector according to the present invention.

FIG. 8 is a diagram illustrating a correspondence relationship between an input horizontal frequency, a filter selection signal, and an output of a selector.

FIG. 9 is a diagram for explaining a screen scanning period and a blanking period.

FIG. 10 is a diagram illustrating correction data before and after a retrace period.

FIG. 11 is a diagram illustrating a correction data creation unit for a flyback period.

FIG. 12 is a graph showing characteristics of a control voltage of a VCO and an oscillation frequency in the present invention.

FIG. 13 is a circuit diagram showing a configuration of a digital convergence device showing another embodiment of the present invention.

FIG. 14 is a circuit diagram showing a configuration of a conventional digital convergence device.

FIG. 15 is a diagram for explaining adjustment points of a conventional digital convergence device.

FIG. 16 is a timing chart of interpolation data for one horizontal period.

FIG. 17 is a diagram showing a horizontal frequency detection circuit and a VCO control circuit in a conventional digital convergence device.

FIG. 18 is a graph showing a control voltage of a VCO and an oscillation frequency characteristic of each VCO in a conventional example.

FIG. 19 is a diagram showing characteristics of a conventional LPF.

[Explanation of symbols]

 24 Input terminal of horizontal frequency detection window signal 34 Horizontal address control circuit 50 Filter control circuit 51 Horizontal interpolation filter 52 Selector

Claims (3)

(57) [Claims] 1. A point where a screen of a color receiver is divided into a grid pattern is used as an adjustment point for convergence correction, and correction data for correcting a color shift of the color receiver is stored in a memory for each adjustment point. A digital convergence device having horizontal frequency detection means for detecting an input horizontal frequency to the receiver, wherein the readout rate of the correction data of the adjustment point on the memory is substantially constant even if the input horizontal frequency changes. Variable adjustment point setting means for variably setting the number of small adjustment points for convergence correction which do not exist in the memory according to the input horizontal frequency; and a plurality of digital filters for performing interpolation calculation in real time;
A selector for switching the digital filter in accordance with a variable setting state of the small adjustment point set by the variable adjustment point setting means. When the adjustment point is set to an integral multiple of the adjustment point, the selector performs the interpolation calculation. A digital convergence device comprising: a correction data interpolating means for performing interpolation by switching a digital filter for performing the correction and calculating the correction data of the small adjustment point. 2. A digital convergence apparatus according to claim 1 Symbol placement, a small adjustment points are variably set by the variable adjustment point setting means of
Variably set the small adjustment point of the retrace period as
The line period variable adjustment point setting means, and the correction data of the small adjustment point in the retrace period
Actual time using the correction data of the adjustment point of the subsequent scanning period
A retrace interval correction data interpolation means for calculating and interpolating between
A digital convergence device further provided . 3. The digital convergence apparatus according to claim 2 , wherein said blanking period correction data interpolation means performs an interpolation calculation in real time.
Multiple digital filters to perform
When the number of small adjustment points is variably set by the
Selector for switching the digital filter
And a digital convergence device comprising: