JPH0834592B2 - Digital correction signal generator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital correction signal generator for digitally performing convergence correction of a color television receiver (monitor receiver or projection type color television), for example.

[Outline of Invention]

The present invention relates to an address for performing interpolation and extrapolation of correction data with respect to first and second address generation circuits in a digital correction signal generator for digitally performing convergence correction of a color television receiver, for example. An address conversion ROM that stores the conversion table is provided, and the data in the memory that stores the correction data is read at the address converted by this address conversion ROM, so that there is no increase in hardware and high accuracy is achieved. The correction is made possible.

[Conventional technology]

Conventionally, the convergence correction of a color television has been performed by analog processing using a correction signal formed from a horizontal deflection signal and a vertical deflection signal. However, on a large screen such as a projection type color television, the distance between the screen and the projection type color television may change, the screen surface may have irregularities, or the number of horizontal scanning lines may be twice as large as that of the conventional one. In the case of the high-definition television system, the tolerance range for misconvergence and misregistration (in the case of a three-tube projection type color television) is narrow, and a convergence correction device with higher accuracy than before is required. It

In order to meet such a request, a pattern such as a dot pattern or a crosshatch pattern is displayed on the screen, the convergence correction amount at each dot point or crossing point is calculated with digital data, and this correction data is used to digitally convert it. A digital convergence device that performs convergence adjustment has been proposed.

FIG. 10 shows an example of a conventional convergence correction device. In FIG. 10, 51 is a memory and 52 is an address generation circuit. The address generation circuit 52 includes a phase comparison circuit 53, VCO
(Voltage Controlled Oscillator) 54 It is composed of a PLL consisting of a prescaler 55. A synchronization signal is supplied to the phase comparison circuit 53 from the terminal 56, and the oscillation frequency of the VCO 54 is controlled by the output of the phase comparison circuit 53. VCO54 output is prescaler 5
It is supplied to the phase comparison circuit 53 via 5, and the count output of the prescaler 55 is output as an address signal.

Correction data is written in the memory 51 in advance. Since the adjustment points are not present on all lines, the correction data for the lines without adjustment points are obtained by interpolation from the correction data for the two adjustment points arranged in the vertical direction. In the memory 51, the interpolation data obtained by these interpolations are written in the address together with the correction data of the adjustment points. In addition to this, linking is likely to occur unless the correction data at the left end of the next line is output during the blanking interval. Therefore, extrapolation data to be read during the blanking interval is written in the address of the memory 1.

The output of the address generation circuit 52 is supplied to the address of the memory 51, and the correction data of the address is read from the memory 51. The output of the memory 51 is supplied to the D / A converter 57 and converted into an analog signal. D / A converter 57
Is supplied to the deflection coil 59 via the drive amplifier 58, and the convergence correction is performed.

[Problems to be solved by the invention]

In the conventional digital convergence correction device shown in FIG. 10, in addition to the correction data in the effective screen, in order to prevent the occurrence of ringing, extrapolation data outside the effective screen, which is created from the correction data in the effective screen, is specified. Need to write to the address. Therefore, special hardware for writing the extrapolation correction data at a predetermined address is required.

In addition, television systems include high-definition television and NTSC systems. For example, in a three-tube projection television, screens different in these systems may be switched and projected. For example, when the high definition television with 1025 scanning lines is switched to the non-interlaced NTSC system with 1050 scanning lines, the address configuration of the memory 51 changes. For this reason, the method of obtaining the interpolated data and the address for the interpolated data are changed, which is difficult to handle.

Further, a delay time is required from the time when the memory 51 is accessed until the convergence is corrected on the screen. This delay time varies. In the conventional digital convergence device, this delay time cannot be adjusted.

Therefore, an object of the present invention is to provide a digital correction signal generator capable of outputting data of extrapolation points without using complicated hardware.

Another object of the present invention is to provide a digital correction signal generator capable of obtaining interpolation data without significantly changing hardware even when the number of scanning lines changes.

Still another object of the present invention is to provide a digital correction signal generator capable of varying the phase of correction data.

[Means for solving problems]

The present invention relates to a memory 1 for storing correction data at each of the adjustment points divided into a matrix of a television effective screen, a first address generation circuit 4 for generating a lateral address of the memory 1, and a memory 1 And a second address generating circuit 7 for generating a vertical address of the memory, a first address generating circuit 4 and the memory 1 and / or a second address generating circuit 7 and the memory 1. An address conversion RO that stores an address conversion table for performing interpolation and extrapolation of correction data
A digital correction signal generator comprising M2 and M3.

[Action]

The correction data of the adjustment point is written in the memory 1.
The horizontal address is generated from PLL4 and the output of PLL4
It is converted by ROM2 and given to memory 1. The vertical address is generated from the counter 7, the output of the counter 7 is converted by the ROM 3 and given to the memory 1. The memory 1 outputs the correction data based on the outputs of the ROM2 and the ROM3. The ROM 9 outputs the difference between the correction data of the adjustment point and the correction data of the interpolation point for performing the interpolation.

〔Example〕

An embodiment in which the present invention is applied to a digital convergence correction device will be described below with reference to the drawings.

When performing the convergence adjustment, first, a crosshatch pattern as shown in FIG. 2 is displayed on the screen. This intersection point is used as an adjustment point, and the convergence correction amount of this adjustment point is obtained. Convergence adjustment is performed digitally using this correction data.

Since there are no adjustment points on all the lines, it is necessary to interpolate the correction data using the correction data of the two adjustment points arranged in the vertical direction and interpolate the interpolation data in a line having no adjustment points.

Further, it is necessary to use extrapolated data during the blanking interval in order to prevent the occurrence of ringing.

FIG. 1 shows an embodiment of the present invention. In this embodiment, as shown in FIG. 2, an intersection of a (6 × 4) crosshatch pattern is used as an adjustment point. Assuming that two correction data in the vertical direction and three correction data in the horizontal direction are added as the extrapolation correction data, in this case, the (9 × 6) two-dimensional address shown in FIG. 3 is assumed. .

In FIG. 3, the area surrounded by the broken line is the effective screen, the black circles indicate the adjustment points, and the white circles indicate the extrapolation points. The correction data (a to x) of the adjustment points indicated by black circles are written in the memory 1 in correspondence with the horizontal addresses m1 to m9 and the vertical addresses 1 to 16 in FIG.

The read address signal for the memory 1 is ROM2
And from ROM3. The address signal A2 output from ROM2 specifies horizontal addresses m1 to m9, and RO
Addresses A1 to L6 in the vertical direction are designated by the address signal A4 output from M3.

Address signal A1 for ROM2 is generated from PLL4. A horizontal synchronizing signal is supplied to the PLL 4 from the terminal 5.
The prescaler of PLL4 is counted from 1 to 9 for each horizontal synchronization, and the count output is used as the address signal A1.
Supplied to ROM2. The ROM2 converts the output address signal A1 of the PLL4 into the address signal A2 as shown in FIG. 4, and supplies the address signal A2 to the memories 1 and 6.

The address signal A3 for the ROM3 is generated from the counter 7. A horizontal synchronizing signal is supplied to the counter 7 from the terminal 5, and the counter 7 is up-counted by the horizontal synchronizing signal. This count output is the address signal
Supplied to ROM3 as A3. A vertical synchronizing signal is supplied to the terminal 8 and the counter 7 is cleared by this vertical synchronizing signal. As a result, the address signal A3 of, for example, 1 to 25 is output from the counter 7 every vertical synchronization. The address signal A3 output from the counter 7 is converted into address signals A4 and A5 in the ROM 3 as shown in FIG.
The address signal A4 is supplied to the memories 1 and 6, and the address signal A5 is supplied to the ROM 9.

The address of the memory 1 is designated by the address signal A4 and the address signal A2 output from the ROM 2, and the data at the designated address is read from the memory 1. The output of the memory 1 is supplied to the adder circuit 10.

In the memory 6, the data of the difference between the correction data of the adjustment points arranged in the vertical direction is written. Address signal A2 and
When the address is specified by A4, the data obtained by subtracting the correction data of the specified adjustment point from the correction data of the next adjustment point arranged in the vertical direction is output. The output of the memory 6 is supplied to the ROM 9 as the address signal A6.

The ROM 9 is provided with a conversion table for performing an operation [A6] · ([A5] −1) / 4 on the input address signals A5 and A6. The calculation based on the above equation is performed by the ROM9. This calculation output is RO
It is supplied from M9 to the adder circuit 10.

The output of the memory 1 is supplied to the adder circuit 10. The output of the memory 1 and the output of the ROM 9 are added by the adder circuit 10, which is supplied to the addition output D / A converter 11 and converted into an analog signal. The output of the D / A converter 11 is supplied to the deflection coil 13 via the drive amplifier 12, whereby the convergence is corrected.

The address signals A2 and A4 are used as read addresses for the memory 1. This address signal A2 and
A4 is an address signal output from PLL4 and counter 7.
A1 and A3 are addresses converted as shown in FIGS. 4 and 5. The address signal A2 repeats in horizontal synchronization. The address signal A4 repeats in vertical synchronization. Therefore, data is read from the memory 1 as shown in FIG.

That is, since the address signal A2 is advanced as shown in FIG. 4, the columns (m1 to m3) in FIG.
The same correction data as the correction data of the adjustment point on m3 is read. In the columns (m3 to m8), the correction data of the adjustment points written in the corresponding columns are read, and in the columns (m8 to m9), the columns
The same correction data as the adjustment point on m8 is read. For example, at the vertical address l2, as shown in FIG. 4, the data a is read out as the extrapolation point data at the horizontal addresses m1 and m2, and the data f is extrapolated at the horizontal address m9. Is read out as data.

The address signal A4 is advanced as shown in FIG.
Therefore, in the lines (1 to 12), the same correction data as the correction data of the adjustment points on the line 12 is read as extrapolation data. In the lines l2 to l5, the correction data of the adjustment points written in the corresponding lines are read. In the lines (l5 to l6), the same correction data as the correction data of the adjustment points on the line l5 is read as extrapolation data.

Since the address signals A2 and A4 are advanced as described above, the correction data are extrapolated to the extrapolation points of the columns m1, m2, m9 and the rows 1, 16 as shown in FIG.

To adjust the phase of the correction data, change the ROM2 table
This can be done by changing the step of the address signal A2 output from M2. For example, if the address signal A2 is
The phase is advanced by stepping as shown in the figure.

The output of memory 1 is added to the output of ROM 9. As a result, for example, correction data for four lines is interpolated between each of the addresses 1 to 16 in the vertical direction. For ROM9, the address signal A5 is incremented as shown in FIG.
And the address signal A6 output from the memory 6 is supplied. The same address signals A2 and A4 as the memory 1 are supplied to the memory 6. Data obtained by subtracting the correction data for the adjustment point at the address from the correction data for the next adjustment point arranged in the vertical direction is output from the memory 6 with respect to the adjustment point at the specified address. The output of the memory 6 is calculated by [A6]. ([A5] -1) / 4 with respect to the address signals A5 and A6 by the address signal A6. The output of the ROM 9 and the output of the memory 1 are added to obtain the interpolated data.

That is, as shown in FIG. 8, the data of two adjustment points X ₀ and X ₁ arranged in the vertical direction are Q ₀ and Q ₁ , and x ₁ and x between the adjustment points X _{0 to} X ₁ are
_{If the} data interpolated to ₂ , x ₃ is q ₁ , q ₂ , q ₃ , the interpolated data q ₁ , q ₂ , q ₃ is q ₁ = Q ₀ + (Q ₁ -Q ₀ ) / 4 q is obtained as _{2 = Q 0 +2 (Q 1} -Q 0) / 4 q 3 = Q 0 +3 (Q 1 -Q 0) / 4. Therefore, when interpolating the (N-1) line between the correction data Q ₀ and Q ₁ , the interpolation data of the nth line from the adjustment point X ₀ is corrected to n (Q ₁ -Q ₀ ) / N. Data Q
It is obtained by adding ₀ and.

The data of (Q ₁ -Q ₀ ) is output from the memory 6. The ROM 9, is provided with a table for multiplying the N / 4 to (Q ₁ -Q _0). n is advanced by the address signal A5, and n = [A5] -1. The address signal A5, as shown in FIG. Each horizontal section is stepped in the order of (1,2,3,3,4). Therefore, since the address signal A5 is 1 on the line where the adjustment point is provided, n = 0 and the output from the ROM 9 is 0. In the next line, the address signal A5 is 2 and n = 1,
From ROM9, ((Q ₀ -Q ₁ ) / 4) is output. After that, the address signal is advanced to (3,3,4), (2 (Q ₀ -Q ₁ ) / 4),
_{(2 (Q 0 -Q 1)} / 4), (3 (Q 0 -Q 1) / 4) is output sequentially. Since the output of the ROM 9 and the output of the memory 1 are added by the adder circuit 10, the adder circuit 10 outputs Q ₀ , (Q ₀ + (Q _0-
(Q ₁ ) / 4), (Q ₀ +2 (Q ₀ -Q ₁ ) / 4), (Q ₀ +2 (Q ₀ -Q ₁ ) /
4) and (Q ₀ +3 (Q ₀ -Q ₁ ) / 4) are output in sequence. In this way, the distance between lines with adjustment points
The correction data is interpolated on the line.

When the correction data for four lines is interpolated between the lines having the adjustment points, the data of the adjustment points arranged in the vertical direction Q ₀ , Q ₁
If the interpolation data is accurately obtained from the weighted average from
The Q _0, the _{n (Q 0 -Q 1) /} 5 is a value obtained by adding the interpolation data. However, in this embodiment, a value obtained by adding n (Q ₀ -Q ₁ ) / 4 and Q _0, which is obtained from the weighted average when the correction data for three lines between the lines with the adjustment points are interpolated Is used to interpolate correction data for four lines between lines. Thus, in order to interpolate the correction data using the value obtained by adding n (Q ₀ -Q ₁ ) / 4 and Q ₀ ,
The address signal A5 is stepped in the order of (1,2,3,3,4), and n =
The value at 2 is read continuously. Since the stepping of the address signal A5 is controlled in this way,
Correction data using a value obtained by adding n (Q ₀ -Q ₁ ) / 4 and Q ₀ can be used to interpolate four lines between adjustment points without any problem.

Further, as shown in FIG. 9, if the address signal A5 is controlled so as to step in the order of (1,1,2,3,3,4) within the effective screen, the line for 5 lines between the adjustment points is adjusted. Interpolation can be done.
As a result, it is possible to deal with the case where the number of lines on the projected screen is changed.

〔The invention's effect〕

According to the present invention, since the ROM 2 for address conversion is provided, the extrapolation point correction data can be obtained without using special hardware. Further, the phase of the correction data can be changed by changing the step of the ROM 2 for address conversion. Further, according to the present invention, the correction data of the interpolation point is obtained by adding the difference between the correction data of the interpolation point and the correction data of the adjustment point to the correction data of the adjustment point. If the address for the ROM 9 for obtaining the difference between the correction data of the interpolation point and the correction data of the adjustment point is controlled by changing the step of the ROM 3, the interpolation can be performed even if the number of lines to be interpolated changes. Therefore, according to the present invention, the hardware is not significantly changed for the method of different methods such as the method of 1025 scanning lines or the method of 1050 scanning lines, and the ROM3 You can do that simply by changing the table.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a schematic diagram of an example of an adjustment pattern in one embodiment of the present invention, and FIG. 3 is a schematic line used for explaining one embodiment of the present invention. FIG. 4, FIG. 5 and FIG. 5 are schematic diagrams of an example of the address conversion table in the embodiment of the present invention, and FIG. 6 is a schematic diagram used for explaining read data in the embodiment of the present invention. FIG. 8 is a schematic diagram of another example of the address conversion table in the embodiment of the present invention, FIG. 8 is a schematic diagram used for explaining the interpolation data, and FIG. 9 is an address conversion table in the embodiment of the present invention. 10 is a block diagram of an example of a conventional convergence correction device. Description of main symbols in the drawings 1,6: memory, 2,3,9: ROM, 5: horizontal sync signal input terminal, 7: counter, 8: vertical sync signal input terminal, 10: adder circuit.

Claims (1)

[Claims] 1. A first memory for storing correction data at each of the adjustment points divided into a matrix of a television effective screen and a difference data between the correction data for the adjustment points arranged in the vertical direction. A second memory, a first address generation circuit that inputs a horizontal synchronization signal to generate a first address signal, and a second address signal that inputs a horizontal synchronization signal and a vertical synchronization signal A second address generation circuit, and a first address for converting the first address signal output from the first address generation circuit into a third address signal for generating extrapolation data other than the valid screen. The conversion means and the second address signal output from the second address generation circuit are both converted to the fourth address signal for generating extrapolation data other than the valid screen and output. A second address converting means for outputting a coefficient for calculating the interpolated data; a calculating means for performing a predetermined operation using the data stored in the second memory and the coefficient; A digital correction signal generation device comprising: an addition unit that adds the correction data of the adjustment point including the extrapolation data read from the memory and the output of the calculation unit.