JPS60182893A - Digital convergence circuit - Google Patents

Abstract

PURPOSE:To obtain a digital convergence circuit without a multiplier by address- inputting the difference between the 1st line correction quantity and the 2nd line correction quantity and a position of scanning lines between data and by storing the correction quantity corresponding two quantities beforehand. CONSTITUTION:The correction quantity of a scanning line 1 and that of a scanning line 2 are added to a subtractor circuit 8, and difference data are added to a correction quantity ROM20. An output of a raster address generator circuit 4 is added to said ROM20 as an address input. Thus the same result as the multiplied one can be obtained from the correction quantity ROM20; therefore a multiplier circuit becomes unnecessary. Thus the correction quantity is calculated beforehand and stored in said ROM20. The correction quantity is added to that of the 2nd scanning line, held in D/A convertors 12-12''', and a current corresponding to these correction quantities passes in four types of convergence circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital convergence circuit for a display device using a color cathode ray tube, and more particularly to an interpolation circuit between vertical data.

[Technology background]

Color cathode ray tubes use the three primary colors of red, green, and blue to express color, and three electron guns are also used to focus the three electron beams that will be output on the same point on the fluorescent surface. is necessary. However, since the distance from the deflection point of the electron beam is different between the center and the periphery of the fluorescent surface, the three beams concentrate in front of the shadow mask at the periphery and do not pass through the same hole, causing color shift. . To correct this, as is well known, each electron gun is provided with a convergence circuit to correct the amount of deflection.

However, since correction in this convergence circuit has conventionally been performed in an analog manner, there is a limit to its adjustment.

Therefore, temperature characteristics and changes over time may occur.

Therefore, in recent years, it has been proposed to digitally process this convergence circuit, thereby making it possible to provide a convergence circuit that is less likely to change over time.

[Prior art and problems]

Conventional digital convergence circuit.

There are two types: a simple type that does not use a vertical interpolation circuit, and a type that uses a vertical interpolation circuit. Since this is a method for inputting data to a computer and requires a very large amount of memory, the circuit for the latter method will be explained with reference to FIGS. 1 and 2.

In this case, as shown in FIG.
An example of division into 56 blocks will be explained. Therefore, when the two display surfaces are addressed as shown in FIG. 2(b), h'-16, v'=16. In addition, as a correction amount, curves CV and C as shown in Figure 2 (cl + (di)
It is assumed that H data is necessary for the vertical circuit and horizontal circuit.

In FIG. 1, 1 is P L L (Phase Lo
ckedLoop) circuit, and 2 is a horizontal address generation circuit.

Each of these circuits 1.2 constitutes a frequency multiplier circuit. In this example, the horizontal clock To is 16 times the horizontal synchronization signal.
and horizontal address signals.

Of course, these correspond to the number of horizontal divisions.

Reference numeral 6 denotes a waveform shaping circuit for a vertical synchronizing signal, which serves as a clear input for a rask address generation circuit 4 and a vertical address generation circuit 5, which will be described later. Here, the rask address generation circuit 4 is
This is to set the number of scanning lines to perform data in the vertical direction.If the display screen has 512 scanning lines, and it is divided into 16 vertically, it is 512÷16-32, so 52 Set whether to do this for each book. For example, in Figure 2 (c
The vertical correction data VC1, VC2, etc. of l are 32
It will be set for each book. Vertical address generation circuit 5
is a counter incremented by one by the rask address generation circuit 4, and counts up to the number of vertical divisions.

Reference numeral 6 denotes a one-frame memory into which the outputs of the horizontal address generation circuit 2 and the vertical address generation circuit 5 are input as addresses, and the correction amount for one screen is stored.
(Reed 0nly Memory) or RAM (Random Access Memory)
ory ) or a combination of both.

Since this value is a representative value of 32 scanning line regions, that is, 16 vertically divided regions, it is necessary to determine the correction amount for each scanning line by interpolation.

That is, when scanning clocks 1 to 16 of FIG. ') is read out from the one frame memory 6.This data is horizontally read out from the second frame memory 6.
As shown in the figure (at), it is continuous. By the way, scanning line 2
The correction amount (21 to 2b') needs to be calculated based on the data of scanning line 1, which is the representative data. Therefore, the representative values of the 32 scanning lines constituting the previous block (in the case of block 1, the data of block 160, and in the case of block 20, the data of block 1 are separately read out and It is held in the register 7. At this time, if the difference between the two is calculated by the arithmetic circuit 8, the difference in vertical correction ff1 (VCl - VC2) is calculated as shown in Fig. 2 (cl). , scan line position (21
In the case of ~2h', the coefficient value according to the second value), that is, the correction amount according to the curve (slope of ■), that is, the weighting coefficient is read from the coefficient ROM 9, and this is
) is subtracted (or added) to the correction data (ie, the correction amount for scanning line 1) by an adder 11.

In this way, interpolation is performed by adding and subtracting the correction data in the second row. The digital convergence value corrected in this manner is converted into an analog value by the DA conversion circuit 12, smoothed by the low-pass filter 13, and amplified by the amplifier 14.

The signal is output to the convergence coil 15 and predetermined correction is performed.

The capacity of one frame memory 6 is in the horizontal direction.

When divided into 16 vertically, 16X16-256
word is required. As is well known, the adjustment points may be hXv corresponding to each other on the display screen, or several points may be selected from these points and the other points may be interpolated using a certain polynomial using a microcomputer or the like.

If V' is set to a very large value (same as the number of scanning lines or about a fraction of the number), a simple type of convergence circuit will be created, and the subsequent interpolation circuit will be unnecessary, but the capacity of one frame memory will be very large. It becomes something big. Therefore, the first
The one shown in the figure has a smaller amount of hardware.

In a delta gun type CRT, the digital convergence circuits shown in FIG. 1 are set in four circuits: blue radial, blue lateral, green radial, and red radial.

However, such a circuit requires an expensive multiplication circuit, and an I/O circuit consisting of an expensive shift register.
Since it requires an H register, it has to be expensive.

[Purpose of the invention]

An object of the present invention is to provide a digital convergence circuit that can perform interpolation without using such expensive multipliers.

[Structure of the invention]

In order to achieve this object, the digital convergence circuit of the present invention is a digital control convergence circuit for a display device using a color cathode ray tube.
The difference between the correction amount of the first row and the second row and the position of the scanning line between each data are input as addresses, and a correction amount storage section is provided in which correction values corresponding to these two amounts are written in advance. It is characterized by:

[Embodiments of the invention]

The present invention will be explained according to (1) omission of the multiplication circuit in the conventional circuit, (2) omission of the IH register in the conventional circuit, (3) common use of the interpolation circuit by time division multiplexing, etc.

(1) Circuit configuration without multiplier circuit In conventional digital convergence circuits.

As shown in FIG. 3, in the subtraction circuit 8, the value A of the previous block sent from the IH register and the value B of the block actually being scanned (for example, A is
, B is VC42) is transmitted, and this difference data A-B-Δ
is output. Then, weighted coefficients are outputted from the coefficient ROM 9 in accordance with the rask address value outputted from the rask address generation circuit 4, and these are multiplied by the multiplication circuit 10 to calculate the correction amount.

In the present invention, as shown in FIG. 4, the correction amount ROM2
Use 0. This correction amount ROM 20 stores in advance the rask address and the data after multiplication corresponding to the difference data Δ. Then, the output of the rask address generation circuit 4 and the output of the subtraction circuit 8 are directly transferred to the correction i1ROM 20.
Input the address of

As a result, from this correction amount ROM 20, the multiplication circuit 10
Since the same result as the multiplication result is obtained, the 9 multiplication circuit 10 can be omitted. It should be noted that the flip-flop 21 in FIG.

Here, the data in the correction amount ROM 20 is stored as follows. The rask address generation circuit counts up every scanning line and is reset to 0 after 9M lines. Now let m be the output of the rask address generation circuit, let the inputs of the subtracter be A and B, respectively, let the output Δ be Δ-A-B, and the carrier be C. The output of the rask address generation circuit is m (o≦m
<M.

When m=integer), the correction amount is (total △).

Since Δ has positive and negative values, carrier C is used as one of the addresses for determination. Here it is positive and C-r
Let o,,1 be negative and C-rIJ. In this manner, the correction amount may be calculated in advance and stored in the correction amount ROMK. An example of the correction amount ROM is shown in FIG. 4 (bl).

The circuit configuration shown in FIG. 5 with the +211H register omitted is
An example of the present invention in which the H register is omitted is shown. The feature of this circuit is that the IH register 7 in FIG. 1 is omitted, and the FF 22 for vertical address holding. Multiplexer 23 for vertical address switching and FFs 24 and 25 for data retention
is added.

Generally, an 8-bit x 16-word shift register is used as an IH register, but this is very expensive, and when peripheral circuits are included, it is usually more expensive than one frame memory.

As an input clock for the horizontal address generation circuit 2.

A signal T that is twice (or 20 times depending on the circuit configuration) the lowest address signal of the one frame memory 6. Use. This signal T, is twice or 20 times the horizontal synchronizing signal by PLL1.
This can be obtained by generating twice the signal. In addition, the output T1 of the rask address generation circuit 4 is set to 4 at the same time as the output of the vertical address generation circuit 5 is set to FF2 for vertical address holding.
It is also used as the second clock. As a result, the vertical address holding FF 22 always holds the previous output of the vertical address generation circuit 5.

Therefore, the previous vertical address held in the FF 22 and the new vertical address held in the vertical address generation circuit 5 are input to the multiplexer 25 to generate the signal To.
As shown in Figure 6, the vertical address of one frame memory is switched every 1'O7, and when +To=II+J, the previous vertical address is output to FF24 for holding old data. The stored data is retained and is equivalent to that used by the IH register of FIG. And T. -rHJ, the data output by the current vertical nutrace is held in the F25 for holding new data, and these can be subtracted by the subtraction circuit 8.

(3) Sharing of correction circuits by switching addresses in a time-division manner The conventional circuit shown in FIG. 1 relates to one deflection system. Therefore, 2. For example, when using a delta gun type color cathode ray tube.

A total of four circuits are required: blue radial (BR), back lateral (BL), red radial (RR), and green radial (GR). Therefore, in the present invention, as shown in FIG. 7 (al), a quaternary color switching counter 26 is provided in the horizontal address generation circuit 2 outside the horizontal address counter 27, and the color switching counter 26 outputs an address for one frame memory. 2 bits are added to the color switching counter 26.
Co and CI are generated by counting To output from LL1. Further, a decoder 2B is provided, and this C01C
1 outputs each signal of BR, BL, GR, and RR.

As shown in FIG. 7(b), this BR-RR signal is set to the output of the adder 11 and is subjected to D-A conversion.
4 digital-to-analog conversion circuits 12 for R to RR
~12'''' and becomes the write timing clock for that FF portion.

Each of these operations is shown in FIG. In other words, Fig. 8 (
As shown in bl, while the lowest horizontal address HO is output as 1 bit, the output CD of the one color switching counter 26 is output as 4 bits as shown in (al). In response to the output C02C1Vc, the decoder 28 outputs the write timing signals RR to GR of the digital fist analog conversion circuits 12 to 12# as shown in FIG. 8(e). As a result, as shown in FIG. The correction amounts output from the adder circuit 11 corresponding to each horizontal address are held in these digital-to-analog conversion circuits 12 to 12″', and the four types of convergence circuits are supplied with currents corresponding to these correction amounts. flows.

If the output C1 of the color switching counter 26 is the highest address of one frame memory, and CO is the next address, the data in the one frame memory will be arranged as shown in FIG. 7 (cl). .

Thus 1 For example, C0=rLJ, CI=rLJ
At this time, positive radial (BR) data is read from one frame memory, and the calculation result based on the data is written to the FF portion of the digital-to-analog conversion circuit 12 using the BR clock (generated from the decoder 28) K. Similarly, CO-“H
”, when C1=“L”, blue lateral (BL), Co-
rLJ, CI -rHJ (D when green maggot flu ('OR
)', CO=rHJ, C1-[If the red radial (RR) is read out in January and K is added, the correction circuit can be used as one circuit.

FIG. 9 shows an example of the digital convergence circuit of the present invention that combines the above (1) to (3). A time chart for explaining the operation is shown in FIG. Each of these figures is merely a synthesis of what has been described above, so a detailed explanation will be omitted.

Still another embodiment of the invention will be described with reference to FIGS. 11 and 12.

In FIG. 11, the plurality of arithmetic circuits used in each of the embodiments described above is replaced with only an addition/subtraction circuit 8'.

The addition/subtraction circuit 8' is initially controlled by the addition/subtraction switching circuit 32 to perform subtraction. The multiplexer 30 is controlled so that the old data from the FF 24 is output. Therefore, in the addition/subtraction circuit 8', it is not FF.
Subtraction is performed between the old data held in FF 24 and the new data held in FF 25, and this subtraction result is held in FF 51 for holding the subtraction result, and this subtraction result is stored in the correction iROM.
This is data for one of the 20 addresses. The correction amount ROM outputs the correction amount based on this subtraction result and the rask signal from the raster address generation circuit 4. At this time, the multiplexer 30 is controlled to send out the output of this correction -[i1ROM 20, and the addition/subtraction circuit 8' is controlled by the addition/subtraction switching circuit 32 to perform addition.
The addition/subtraction circuit 8' adds the new data sent from the FF 25 and the correction amount sent from the multiplexer 30, and outputs the corrected data. This is selectively stored in the FFs 12 to 12'' according to the data at that time. By doing so, the expensive arithmetic element can be reduced to one.

〔Effect of the invention〕

According to the present invention, in a digital convergence circuit, not only can expensive multipliers and I and N registers be eliminated, but also the number of components can be significantly reduced, and a circuit with high implementation efficiency can be created.

[Brief explanation of drawings]

Figure 1 is a conventional digimir convergence circuit, Figure 2 is an explanation of its operation RFT, Figure 5m3 is an illustration of a conventional multiplication, Figure 4 is a partial diagram of the present invention with the multiplication circuit omitted, and Figure 5 is an In register. 6 is a time chart of FIG. 5, FIG. 7 is a time division control state explanatory diagram, and FIG. 8 is a time chart of FIG. 7. FIG. 9 shows an example of a digital km convergence circuit using the present invention. FIG. 10 is a time chart thereof, FIG. 11 is another example of a digital fist convergence circuit using the present invention, and FIG. 12 is a time chart thereof. In the figure, 1#'i is a PLL circuit, 2 is a horizontal address generation circuit, 3 is a pulse shaping circuit, 4 is a raster address generation circuit, 5 is a vertical address generation circuit, 6 is a 1 frame memory,
7 is an I n register, and 8 is a subtraction circuit. 9 is a coefficient ROM, 10 is a multiplication circuit, 11 is an addition circuit, 1
2 is a digital/analog conversion circuit with FF. 15 is a low-pass filter, 14 is an amplifier, 15 is a convergence coil, and 2o is a correction iR. M, 22 is an FF for holding vertical addresses, 23 is a multiplexer, and 28 is a decoder. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Akira Yamatani Sakae No. 3 Closing/1 (b) I Minister I L Go 1 Procedural Amendment (Voluntary) September 26, 1980 3, with the case of the person making the amendment Related Patent Applicant Address 1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture Name (522) Fujitsu Limited Representative Takuma Yamamoto 4, Agent Address 1-19-8-6 Kanda Awaji-cho, Chiyoda-ku, Tokyo
, Subject of amendment Column 7 of Detailed Description of the Invention in the Specification, Contents of Amendment Contents of Amendment (1) Lines 4 to 5 of page 3 of the specification are amended as follows. ``There is a limit to the number of convergence circuits, and because analog circuits are connected in multiple stages, they may be affected by temperature characteristics or change over time.'' ” Addendum 1E. (3) "To clarify." in the second line of page 4 is amended as follows. "To clarify. (Including blanking time)" (4) Same No. 7
Delete "Therefore, it becomes -1----smaller." from line 15 to line 16 of the page. that's all

Claims (1)

[Claims] (In a digital control convergence circuit for a display device using an 11-color cathode ray tube, the difference between the correction amount of the first line and the second line and the position of the scanning line between each data are used as address inputs. A digital convergence circuit characterized in that a correction amount storage section is provided in which correction amounts corresponding to these two ftKs are written in advance. (2) Digital convergence circuit of a display device using a color cathode ray tube.
In the 611 convergence circuit based on the 611 convergence circuit, the difference between the correction amount of the first line and the correction amount of the second line and the position H of the scanning line between each data
1 as an address input, and a correction amount storage section in which correction amounts corresponding to these two amounts are written in advance, a vertical address holding means that holds the vertical address of the data of the previous row in advance, and 2 time-division vertical A digital convergence circuit comprising switching output means for switching addresses and data holding means for temporarily holding data.