JPS61293089A - Digital convergence correcting device - Google Patents

Abstract

PURPOSE:To execute the correction of B (blue shift), BL (lateral shift) independently from that of R (red shift) and G (green shift) by changing the amount of correction of R and G in accordance with the magnitude of the correction amount of B and BL. CONSTITUTION:The correction of R and G is the same as the conventional practice, however, in case the correction amount of B or BL is changed, the outputs from one-field memory 6B and 6BL are supplied to multipliers 16 and 17 so that a certain coefficient is multiplied. The outputs from the multipliers 16 and 17 are respectively added by adders 18 and 19 with the correction data of R and G which are the output from write data generating circuits 5R and 5G, and are stored in one-field memories of R and G; 6R and 6G. By selecting proper coefficients to be multiplied by the multipliers 16 and 17, the influence of the correction amount of B and BL on R and G is made nearly none. Therefore, the correction of B and BL can be executed almost independently from R and G.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital convergence correction device for a color television receiver.

[Prior Art] FIG. 2 is a block diagram schematically showing a digital convergence correction device conventionally used in color television receivers. In the figure, one test pattern generation circuit (1), one control panel (2), and one write address generation circuit (3) are provided.
Other components are R (red shift)), G (green shift), B (
A total of four systems are provided corresponding to the convergence coils of blue shift) and BL (lateral shift).

Data write key (2b) on control panel (2)
The letters R, G, B, and BL shown in the figure mean keys corresponding to each of these systems.

Next, the operation of the digital convergence correction device shown in FIG. 2 will be explained. The operation of this device is to store digital convergence correction data in one field memory (6).
and the operation of reading data from the 1-field memory (6) and actually performing digital convergence correction.

In the write operation, the test pattern generation circuit (1)
Projects a grid-like image on the screen. Then, the user operates the cursor key (2a) on the control panel (2) to move the cursor key (2a) to the grid point to be adjusted. The output of the write address generation circuit (3) changes depending on the output signal of the cursor key (2a) at this time. The output of the multiplexer (4) is applied to one field memory (6), and this signal specifies the address corresponding to the grid point. Next, select the data write key (
2b), the output of the write data generation circuit (5) changes. At this time, the l field memory (6) is in write mode by the read/write control circuit (8), and the output data from the write data generation circuit (5) is in the l field specified by the cursor key (2a). It is written to the address in memory (6).

By the way, in the double writing operation, the writing mode is activated only at the moment when the scanning line passes through the point on the screen selected by the cursor key (2a) and the data writing key (2b) is being operated; , the 1 field memory (8) is set to read mode by the read/write control circuit (8), and the multiplexer (4
) gives the output of the read address generation circuit (7) to the 1-field memory (6).

On the other hand, in read mode, one field memory (
All of the data corresponding to each grid point of the screen stored in 6) is read out in accordance with the scanning speed of the receiver. In order to interpolate between each scanning line from the data corresponding to these grid points, data for one tree of horizontal lines of the grid is temporarily stored in one line memory (9), and data for one tree of next horizontal lines is stored in one field. Data is read from the memory (6), and in parallel, data stored in the 1-line memory (8) is read and applied to the vertical interpolation circuit (10). Direct interpolation circuit (10
) calculates digital convergence correction data on each scanning line between 1i12 horizontal trees of data by linear interpolation. The interpolated correction data is converted into analog data by the digital/analog conversion circuit (11), smoothed by the low-pass filter (12), and then sent to the output amplifier (11).
3) and is amplified by the convergence coil (1) of the receiver.
4) as a correction current.

Convergence coils (14) are provided for each of R, G, B, and BL, but they influence each other in a π-like manner due to the ring 1m field. Among them, the magnetic fields generated by the B and BL coils are particularly strong, and have a large influence on R and G.

[Problems to be Solved by the Invention] Since the conventional digital convergence correction device is configured as shown below, each correction amount of R, G, B, and BL is applied to each of the R, G, and H beams. For example, if you change the amount of correction for B, the R9G and H beams move at the same time, so there is a problem that it takes a lot of time and experience to converge each beam. .

This invention has been made to solve the problems mentioned in (1) above, and it is an object of the present invention to provide a digital convergence correction device that can perform convergence correction very simply and with high precision.

[Means for solving the problems] The digital convergence correction device according to the present invention has the following features:
The amount of correction for R and G is changed according to the amount of correction for B and BL.

[Operation] In this invention, the R and G correction amounts are changed according to the B and BL correction amounts, so that even if the B and BL correction amounts are changed, the R and G beams do not move. As a result, B and BL can be corrected almost independently of R and G.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a digital convergence correction device of the present invention. Of these, parts that are the same as or equivalent to those of the apparatus shown in FIG. 2 will be denoted by the same reference numerals, and a redundant explanation thereof will be omitted, and only the parts indicated by 4 and 1 in FIG. 1 will be described.

In FIG. 1, the write data generation circuit (5R), (
5G), (5B), (5BL), l field memory (13R), (EiG), (8B)
, (flBL) , output circuit (t5R) , (1
5G), (15B), and (+5BL) are provided with the same ones for each of the four systems R, G, B, and BL. Note that the output circuit (15R) is a vertical interpolation circuit (lO)
, D/A conversion circuit (11), 1-line memory (9), and LPF (12), other output circuits (15G), (15B), (15
Since the configuration of BL) is also exactly the same, one illustration is omitted. (1B) and (1?) are multipliers that multiply the outputs of the 1-field memory (flB) and (6BL) of B and BL by a constant, respectively, and output the result (+8) and (
19) is the write data generation circuit (5R), (5G)
This is an adder that adds the output of the multiplier (16) and the output of the multiplier (17).

Next, the operation will be explained. R and G corrections are the same as before, but when increasing or decreasing the B or BL correction amount, 1 field memory (eB), (8B
The output of L) enters a multiplier (18), (1?), where it is multiplied by a certain coefficient. This multiplier (18).

The output of (17) is sent to write data generation circuits (5R) and (5R) in adders (18) and (19), respectively.
5G) is added to the correction data of R and G, which is the output of R.
, G are stored in one field memory (f(R), (ec). Here, the multipliers (16) and (17) multiply B, BL by appropriately selecting the coefficients to be combined.
The effect of the correction amount on R and G is almost eliminated, and B
, BL can be corrected almost independently for R and G.

[Effects of the Invention] As described below, according to the present invention, corrections for B and BL, which have a large influence on the movement of R and G beams, can be performed almost independently, so that the convergence of each beam can be improved. This has the effect of providing a digital convergence correction device that can perform adjustment very quickly and accurately.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital convergence correction device of the present invention, and FIG. 2 is a block diagram showing a conventional digital convergence correction device. (5R), (5G), (5B), (5BL
)...Write data generation circuit, (OR), (GG
), (8B), (flBL)...l field memory, (ill), (+7)...multiplier, (
18), (19)...Adder. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Write digital convergence correction data to one field memory, read the above correction data from this memory, and perform each convergence of R (red shift), G (green shift), B (blue shift), and BL (horizontal shift). A digital convergence correction device that performs convergence correction by supplying a correction current to each coil, characterized in that the correction amounts of R and G are changed according to the magnitude of the correction amounts of B and BL. Device.