JPH0440791A - Digital convergence device - Google Patents

Abstract

PURPOSE:To quickly and accurately execute convergence adjustment without needing readjustment by comparing a correcting value to be supplied to a convergence yoke and the correcting value of the output signal of a storing means, detecting that they are coincident and correcting a convergence correcting quantity. CONSTITUTION:A means 12 to select a convergence adjusting point, a means to read the correcting quantity of a 1 frame memory 5 with a clock signal, a correcting means 120 and so on are provided. Then, data except the adjusting point selected by the 1 frame memory 5 with the correcting means 120 are corrected so that the convergence deviation of the peripheral adjusting point generated by the data change of the selected adjusting point may be a same correcting value with comparing the output of a storing means 100 to store the correcting value to be supplied to a convergence yoke 13 of the adjusting points except the selected adjusting point and the correcting value except the selected adjusting point to be supplied to the convergence yoke 13 and with detecting whether they are coincident or not. Thus, readjustment is not needed and convergence adjustment is executed quickly and accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a convergence circuit for a color television receiver, and more particularly to a digital convergence device that can be adjusted accurately and easily.

2. Description of the Related Art As a conventional digital convergence device, for example, an invention as shown in Japanese Patent Application Laid-open No. 144688/1988 is known. , write the correction data of the convergence correction amount for each point and each intersection into the day V and N Kl frame memory, read out the data and perform D/A conversion,
This is to perform convergence correction.

This will be explained in detail below with reference to FIGS. 2 and 3. 2, and 13 vertical lines as shown in FIG.

A pattern corresponding to the convergence adjustment points in nine rows in the horizontal direction is displayed by the pattern generation circuit 15, and the intersection point of the dot and crosshatch corresponding to the adjustment point to be adjusted is selected using the cursor keys 2 of the control panel I. The address Fi of the adjustment point selected with the cursor key 2 is stored in the cursor counter 12.

Next, if the color you want to correct is red, for example, specify red using the red data write key 3 of the control spring/I/l, set a desired piece of data in the data reversible counter 4, and The output of the reversible counter 4 is written to the 9th address specified by the cursor counter 12 of the one frame memory 5. Here, the contents of the l-frame memory 5 selected by the cursor counter 12 are read out to the data reversible counter 4, and when it is desired to increase the convergence correction amount at that adjustment point, the data reversible counter 4
Write correction is performed by increasing the amount of correction and writing the desired correction amount into a predetermined address of the one-frame memory 50 by decreasing it when desired. Thereafter, all adjustment points on the screen are adjusted in the same manner.

Next, we will explain how to read out the convergence correction amount written in the l-frame memory 5. The reading address counter 14, which is a reading means, reads the contents of the l-frame memory 5 using a clock synchronized with the horizontal and vertical deflections. At this time, the l frame memory 5 only stores the correction amount at the location corresponding to the intersection of each dot and crosshatch, so the correction amount for each scanning line between the adjustment points in the vertical direction is read out. Interpolation needs to be done. Therefore, for example, after reading the correction amount for the first column from the one-frame memory 5 and setting it in the register 6,
The correction amount in the second column is read from the frame memory 5. Using the correction amounts of the first and second columns read in this way,
The amount of correction for the scanning line between the first column and the second column is determined by interpolation. That is, the difference between the correction amount in the first column set in the V star 6 and the correction amount in the second column read from the one-frame memory 5 is calculated by the subtraction circuit 7, and a total of 1 kl[ M
A multiplication circuit 8 multiplies weight coefficients for each scanning line written in advance in , and an addition circuit 9 adds the result and the correction amount of the second column to perform interpolation.
The output signal is converted into an analog signal by a D/A conversion circuit 10, smoothed and amplified by a low-pass filter (LPF), and then supplied to a convergence yoke 13.

Problems to be Solved by the Invention However, in the above configuration, the D/A conversion circuit l
Smooth the stepped signal converted to an analog signal with O.
Since smoothing is performed by the low-pass filter 11 so that Therefore, it is necessary to repeat the adjustment several times, and therefore there is a problem that the adjustment takes a very long time.

In view of this problem, it is an object of the present invention to provide a digital convergence device that can quickly and accurately adjust convergence without requiring readjustment.

Means for Solving the Problems In order to solve the above problems, the digital convergence device of the present invention includes means for selecting convergence adjustment points in N rows and y columns, and an l frame for storing convergence correction amounts for each convergence adjustment point. means for writing into the one-frame memory; means for reading out the correction amount in the one-frame memory using a clock signal synchronized with the horizontal deflection and vertical deflection; D/A conversion means for converting the analog value into a value, means for smoothing the analog value of the D/A conversion means with a low-pass filter, means for supplying an output signal of the low-pass filter to a convergence yoke, and the comparator. - a compensation means for storing a correction value of the output signal of the means for supplying the sense yoke, and a comparison between the correction value supplied to the convergence yoke and the correction value of the output signal of the storage means and detecting that they match; The apparatus includes a coincidence detection circuit and a correction means for correcting the convergence correction amount stored in the l-frame memory based on the detection result of the minus number composition means.

The storage means for storing the output signal of the means for supplying to the convergence yoke stores at least the correction values to be supplied to the convergence yokes at the adjustment points before and after the selected adjustment point.

Effect of the Invention With the above-described configuration, when adjusting the convergence correction of a selected adjustment point, the present invention corrects the convergence deviation of surrounding adjustment points caused by data changes of the selected adjustment point by adjusting the convergence correction of adjustment points other than the selected adjustment point. .

The output of the storage means for storing the correction value to be supplied to the parsense leak is compared with the correction values other than the selected adjustment point to be supplied to the convergence 8-reference. Since the data other than the selected adjustment point in one frame memory is corrected by the correction means, there is no need for readjustment.Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a digital convergence device according to an embodiment of the present invention. In FIG. 1, components that operate in the same manner as in the prior art are designated by the same numerals and their explanations will be omitted. In FIG. 1, 100 is a storage circuit configured to store a correction value to be supplied to a convergence yoke at an adjustment point, and during adjustment, a correction value to be supplied to a convergence yoke at an adjustment point other than the selected adjustment point. Remember the value. , 110 is a coincidence detection circuit that compares the output signal of the memory circuit 100 and the correction I[ supplied to the convergence yoke and detects whether they match;
Reference numeral 120 denotes a stop circuit that corrects the convergence correction data of adjustment points that do not match, so that they become the same correction value, based on the detection result detected by the coincidence detection circuit 110.

The operation of the digital convergence device of this embodiment configured as described above will be explained.

First, the operation when adjusting convergence correction will be explained.

Use the control springs A/l to select the desired adjustment point and move it using the cursor key 2 in the same manner as before. Correction data for the adjustment point selected by the cursor counter 12 is read from the one-frame memory 5 and set in the reversible counter 4. The storage circuit 100 supplies correction to the convergence yoke 13 at adjustment points other than the selected adjustment point. The correction values other than the points are compared with the correction values in the storage circuit 100 to detect whether they match. At this time, convergence correction has not yet been performed, so no peripheral convergence shift occurs due to the low-pass filter IIK.
No correction is made to the frame memory 50 frequency correction data by 20. Next, when adjusting the selected adjustment point, the correction data set in the reversible counter 4 is rewritten using the increase/decrease keys (not shown) on the control panel 1, written to the 17-frame memory 5, and then updated at the display processing speed. Readout, D/A conversion circuit lO1 low pass filter
It is supplied to the convergence yoke 13 via the convergence yoke 11.

Convergence correction data 71 of the adjustment point selected at this time
112) If a convergence shift occurs at a peripheral adjustment point other than the adjustment point due to a change, the -number output circuit 110 outputs a value other than the final point after the pre-adjustment oiiq adjustment point (the convergence point before convergence correction of the selected adjustment point - The correction value supplied to the convergence detection circuit 13 is used to detect convergence errors (data in the storage circuit 100) and the convergence error.
Based on the detection result of 0, the correction data in the 1 frame memory 5 is corrected, and 17 frames) are read out again from 1 to 5 and supplied to the convergence yoke 13.

As described above, according to this embodiment, when adjusting the convergence correction of nine selected adjustment points, the convergence deviation of the surrounding adjustment points caused by the data change of the selected adjustment points can be corrected by adjusting the convergence correction of the nine adjustment points other than the selected adjustment points. The coincidence detection circuit 110 compares the correction value supplied to the convergence yoke at the point t1 circuit ioo O output with the correction value supplied to the convergence yoke other than the selected adjustment point, and determines that they match.
By correcting data other than the adjustment points translated by the 5 ois in one frame memory using the correction circuit 120 so that the same correction value is obtained, convergence adjustment can be performed quickly and accurately without the need for readjustment. .

In this embodiment, the storage circuit 100 stores the correction value to be supplied to the convergence yoke for each adjustment point, but it may store only the correction values for one horizontal period or before and after the selected adjustment point.

It goes without saying that it is better to store the correction value supplied to the convergence yoke 13 in digital or analog format.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, when adjusting the convergence correction of a selected adjustment point, the convergence shift of surrounding adjustment points caused by data change of the selected adjustment point is corrected by adjusting the convergence shift of the surrounding adjustment points other than the selected adjustment point. The output of the storage means that stores the correction value supplied to the convergence yoke at the adjustment point is compared with the correction value supplied to the convergence yoke at a point other than the selected adjustment point, and it is detected whether or not they match. As shown in FIG.
Convergence can be adjusted quickly and accurately, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a digital convergence device in an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional digital convergence device,
FIG. 3 is a diagram for explaining the projected screen at the time of convergence adjustment. l...Control panel, 2...Cursor key 3
...Write key 4...Reversible counter, 5...
l frame memory, 6... register %7... subtraction circuit, 8... multiplication circuit, 9... addition circuit, lO...
D/A conversion circuit, 11...low-pass filter, 12.
... Cursor counter, 13... Convergence yoke, 14-... Read Ll counter, 15... Pattern generation circuit, 100... Memory circuit, 110...-
Laying and unloading circuit, 120-・Correction @1g. Agent Yoshihiro MorimotoFigure 8

Claims (1)

[Scope of Claims] 1. means for selecting convergence adjustment points in N rows and M columns; 1 frame memory means for storing a convergence correction amount for each convergence adjustment point; means for writing into the 1 frame memory; means for reading out the correction amount of the frame memory using a clock signal synchronized with horizontal and vertical deflection; D/A conversion means for converting the correction amount read from the one frame memory into an analog value;
means for smoothing the analog value of the A conversion means with a low-pass filter; means for supplying the output signal of the low-pass filter to a convergence yoke; and storing a correction value for the output signal of the means for supplying the convergence yoke. storage means; a coincidence detection means for comparing the correction value supplied to the convergence yoke with the correction value of the output signal of the storage means and detecting a match; A digital convergence device comprising a correction means for correcting a convergence correction amount stored in a memory. 2. The digital device according to claim 1, wherein the storage means for storing the output signal of the means for supplying to the convergence yoke stores at least correction values to be supplied to the convergence yoke at adjustment points before and after the selected adjustment point. Convergence device.