JPH0463086A - Digital convergence correcting circuit - Google Patents

Abstract

PURPOSE:To smoothly and accurately adjust correction data by providing a cursor display means which displays a cursor on a picture correspondingly to a correction point and a position adjusting means which adjusts the acting position of convergence correction in the horizontal direction. CONSTITUTION:A convergence correction signal DcL is delayed by a low pass filter 14 and is outputted; and when the position of a cursor CS and the actual acting position of convergence correction are shifted from each other, a phase adjustment signal Spc from a control circuit 7 is changed to adjust the digital value written in a phase adjustment register 44. Then, the phase of a reset signal HRT' outputted from a horizontal reset circuit 42H is adjusted. As the result, the reset timing of a horizontal address counter 43H is quickened, and the change timing of the horizontal address signal is quickened. Consequently, the position of the cursor CS and the actual acting position of convergence correction coincide with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a convergence correction circuit that digitally corrects the convergence of a color picture tube.

[Prior Art] FIG. 5 shows the configuration of a conventional digital convergence correction circuit.

In the figure, the PLL circuit 1 is supplied with a horizontal blanking signal P BLH (shown in FIG. 7A) and a vertical blanking signal P BLV. This PLL circuit 1 outputs a reference clock CLK (shown in C in the same figure) whose phase is synchronized with the blanking signals P8L)I and P8LV, and also outputs a phase lock signal PLH having the same period as the blanking signal PBLH. (shown in Figure B) is output.

The reference clock CLK from the PLL circuit 1 is supplied to the timing generation circuit 2. The timing generation circuit 2 supplies the crosshatch generation circuit 3 with a crosshatch clock CKI synchronized with the reference clock CLK.

A crosshatch signal 5CH (shown in FIG.
is supplied to the output terminal 6 via. When adjusting the convergence correction data (hereinafter referred to as "data adjustment"), the screen of the color picture tube (not shown) is divided into X equal parts in the horizontal direction by this crosshatch signal SCH.
A crosshatch pattern is displayed that is divided into Y equal parts in the vertical direction (X and Y are natural numbers).

The intersection of this crosshatch pattern becomes the convergence correction point. The coordinates of this correction point are indicated by (x, y) with the upper left correction point as a reference. For example, X=14, Y
= 10, the crosshatch pattern is
It is displayed as shown in the figure, and the coordinates (x, y) of the correction point are (
0,0) to (14°10).

Coordinates of cursor C5 and frame memory 10 to be described later
The address corresponds to the coordinates of this correction point.

Further, the timing generation circuit 2 is connected to the address generation port N4.
An address clock CK2 (shown in FIG. 7G) synchronized with the reference clock CLK is supplied. Furthermore, this address generation circuit 4 is supplied with a phase lock signal PLH having a horizontal period from a PLL circuit 1, and is also supplied with a vertical blanking signal P8LV.

At the time of data adjustment, the control circuit 7
A cursor designation signal SC that designates the coordinates of the cursor C5.
A is supplied, and the address generation circuit 4 outputs a cursor generation signal 5CG (shown in F of the figure) at the timing when the electron beam scans the specified coordinate position.

FIG. 6 shows a specific configuration of the address generation circuit 4. As shown in FIG.

In the figure, address clock CK2, vertical blanking signal PBLV, and phase lock signal PL■ are supplied to a cursor generation signal output section 41, and this signal output section 41 is further supplied with a cursor designation signal SCA.

The signal output section 41 includes a horizontal position down counter and a vertical position down counter, although not shown.

The vertical position down counter receives the cursor designation signal SC at the timing when the vertical blanking signal PBLv is supplied.
A count value indicating the vertical coordinate position designated by A is set and sequentially counted down by the phase lock signal PLH.

On the other hand, the horizontal position down counter receives the cursor designation signal SCA at the timing when the phase lock signal PL)l is supplied.
A count value indicating the horizontal coordinate position specified by is set and sequentially counted down by the address clock CK2.

Then, at the timing when the count values of both down counters reach 10, a cursor generation signal SCG 5 is output.

Returning to FIG. 5, the cursor generation signal 18 SCG output from the address generation circuit 4 is supplied to the cursor generation @ path 8, and the cursor generation circuit 8 outputs a cursor signal SC5. This cursor signal SC5 is combined into a crosshatch signal SCH by an adder 5 and output to an output terminal 6.

Therefore, as shown in Fig. 8, a crosshatch pattern is displayed on the screen, and the cursor
8 is displayed.

Additionally, a blanking signal P is output from the address generation circuit 4.
A synchronous address signal ADS is output in synchronization with BLV and PBLH, that is, in accordance with the scanning position of the electron beam.

In FIG. 6, the vertical blanking signal PBLV is supplied to the vertical reset circuit 42V, and at the timing of the supply, 11 is output as the reset signal V].

The vertical address counter 43V uses this reset signal V]
τ]1. This vertical address counter 43V is counted up by the phase lock signal PL, and a vertical address signal is output.

Further, the horizontal reset circuit 42H is supplied with the address clock CK2 and the phase lock signal PLH. From this horizontal reset circuit 42H, a reset signal Tff7 (seventh (shown in the figure) is output. The horizontal address counter 43H is reset by this reset signal .tau.11. This horizontal address counter 43H is controlled by the address clock CK.
2, and a horizontal address signal (only 4 bits HO to H3 are shown in H in the figure) is output.

The vertical address signal and horizontal address signal output from address counters 43V and 43H are output as a synchronous address signal ADS.

Returning to FIG. 5, the synchronous address signal ADS output from the address generation circuit 4 is supplied to the a-side fixed terminal of the address switching circuit 9.

The control circuit 7 described above is configured with, for example, a microprocessor, and includes keys (not shown) for adjusting data, keys for adjusting correction data, keys for moving a cursor C8, and the like. This control circuit 7 outputs a control address signal ADC, and this control address signal ADC is supplied to the b-side fixed terminal of the address switching circuit 9 and the nonvolatile memory 11. The address signal output from the address switching circuit 9 is then supplied to the frame memory IO.

The control address signal ADC output during data adjustment is
This corresponds to the coordinate position of the cursor C8.

On the other hand, the control that is output when the write switch 12 connected to the control circuit 7 is pressed and the correction data stored in the frame memory 10 is written to the nonvolatile memory 11 (hereinafter referred to as "data storage time") The address signal ADC is used to sequentially designate addresses of the frame memory 10 and nonvolatile memory 11.

Frame memory 0 is for storing the correction data at each correction point described above, and has a capacity to store correction data for one screen.

The nonvolatile memory 11 is for storing the correction data stored in the frame memory 10, and has a capacity that is, for example, 100N times that of the frame memory. A memory selection signal SMS for selecting a write area is supplied from the control circuit 7 to the nonvolatile memory 10.

Note that writing or reading of the frame memory 10 and the nonvolatile memory 11 is controlled by the control circuit 7.

The address switching circuit 9 is supplied with an address switching signal SAS from the control circuit 7 . And address switching circuit 9
is connected to bll during the vertical blanking period during data adjustment, and is connected to the a side during data adjustment except during the vertical blanking period. Further, the address switching circuit 9 is connected to b* during the vertical blanking period when saving data, and is connected to af during the vertical blanking period when saving data.
Connected to R. Further, the address switching circuit 9 is connected to the a side except when adjusting data and storing data.

Correction data DCC read from frame memory 10
is converted into an analog signal by the D/A converter W13, smoothed by the low-pass filter 14, and then supplied to the output terminal 15.

The signal outputted to the output terminal 15 is supplied as a convergence correction signal to a convergence correction coil (not shown), where convergence is corrected.

In the above configuration, during the vertical blanking period during data adjustment, the frame memory 10 is in the write state, the address switching circuit 9 is connected to the b side, and the frame memory 10 corresponds to the coordinate position of the cursor C5. A control address signal ADC is supplied. Therefore, the correction data that has been increased or decreased by the control circuit 7 is written into the address specified by the control address signal ADC of the frame memory 10 as the correction data of the correction point corresponding to the coordinate position of the cursor C5.

By moving the coordinate position of the cursor C5 using the control circuit 7, correction data for all correction points are adjusted in the same way.

Other than the vertical blanking period during data adjustment, the frame memory 10 is in a read state, the address switching circuit 9 is connected to the a side, and the frame memory 10 receives a synchronous address signal corresponding to the scanning position of the electron beam. A.D.
S is supplied. Therefore, correction data DCC is read out sequentially from the address designated by the synchronous address signal ADS of the frame memory 10, and convergence correction is performed in each part of the screen based on this correction data DCC.

That is, during this period, convergence correction is performed using the correction data written in the frame memory 10 during the vertical blanking period, so the degree of correction can be checked, and if the correction is not sufficient, the control circuit 7 The correction data will be further increased or decreased.

During the vertical blanking period when saving data, the frame memory 0 is in the read state, the nonvolatile memory 11 is in the write state, and the address switching circuit 9 is connected to the b side, and the frame memory 10 and the nonvolatile memory 11
A control address signal ADC for sequentially specifying addresses is supplied to the control address signal ADC.

Therefore, the correction data at each correction point ζ is sequentially read from the frame memory IO, and this correction data is supplied to the nonvolatile memory 1/11 via the data bus 16, written therein, and stored.

At times other than data adjustment and data storage, the frame memory 10 is in a read state, and the address switching circuit 9 is connected to the a side, and the frame memory 10 has a synchronous address corresponding to the scanning position of the electron beam. Signal ADS
is supplied. Therefore, the correction data DCII)<< is read out sequentially from the address specified by the synchronous address signal ADS of the frame memory 10, and convergence correction is performed in each part of the screen based on this correction data DCC. That is, during this period, a normal image on which convergence correction has been performed is displayed in each part of the screen.

Also, when turning the power off and then on again,
It works as follows.

First, the frame memory IO is put into a write state, and the nonvolatile memory 11 is put into a read state. The address switching circuit 9 is connected to the b side, and the frame memory 10 and nonvolatile memory 11 are supplied with a control address signal ADC that sequentially specifies addresses. Therefore, the correction data DCC at each correction point is sequentially read from the nonvolatile memory 11, and this correction data DCC is supplied to the frame memory 10 via the data bus 16 and written therein.

Next, the frame memory 10 is put into a read state, the address switching circuit 9 is connected to the a side, and the frame memory 10 is supplied with a synchronous address signal ADS corresponding to the scanning position of the electron beam. Therefore, the correction data DCC is sequentially read out from the address specified by the synchronous address signal ADS of the frame memory 10, and convergence correction is performed in each part of the screen based on this correction data DCC.

In order to simplify the explanation, in the example of FIG. 5, the circuit system from the frame memory 10 to the low-pass filter 14 is
Although only the systems are shown, there are actually three systems related to red, green, and blue, and convergence correction is performed by each system.

In this case, correction data for red, green, and plaster will be written in each frame memory 10 as described above.

[Problems to be Solved by the Invention] Incidentally, in the convergence correction circuit shown in the example in FIG. This becomes the convergence correction signal DCL (shown in J of the same figure).

Therefore, the delay time TO in the low-pass filter 14
For the position of cursor C8 (see cursor generation signal SCG shown in figure F), the convergence correction signal
CL is output with a delay.

However, the 9th TI! As shown in J, the actual convergence w1':'F
.

acts with a delay. Therefore,! At liJ alignment,
The position of the cursor C5 does not match the part where the convergence state changes due to the adjustment of the correction data, making it impossible to adjust the correction data smoothly and accurately.

Therefore, in the present invention, it is possible to match the position of the cursor with the position where convergence correction is applied.

[Means for Solving the Problems] The present invention uses the intersection points of a crosshatch pattern that equally divides the horizontal and vertical directions into predetermined numbers on the screen of a color picture tube as correction points, and calculates correction data at each correction point. It is equipped with a frame memory for storing and a non-volatile memory for storing correction data at each correction point stored in this frame memory, and after reading the correction data at each correction point from the frame memory in synchronization with the deflection timing. A digital convergence correction circuit that performs convergence correction by converting it into an analog signal, and a cursor display means that displays a cursor on a screen corresponding to a correction point;
A position adjusting means for horizontally adjusting the position where the convergence correction is applied is provided.

[Operation] In the above configuration, the position where the convergence correction acts can be adjusted in the horizontal direction by the position adjusting means. Therefore, it is possible to match the cursor position and the position where convergence correction is applied.

As a result, when making adjustments, the position of the cursor cs,
By adjusting the correction data, the parts where the convergence state changes are made to coincide with each other, and the correction data can be adjusted smoothly and accurately.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In this example, the address generation circuit 4 is supplied with a vertical blanking signal PBLV, a phase lock signal PLII from the PLL circuit, and an address clock CK2 from the timing generation circuit 2, as well as a reference clock CLK from the PLL circuit 1. At the same time, the control circuit 7 supplies the phase adjustment signal SPC. Note that the control circuit 7 is newly equipped with a key for changing the phase adjustment signal SPC.

FIG. 2 shows a specific configuration of the address generation circuit 4 in this example. In FIG. 2, parts corresponding to those in FIG. 6 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the figure, a phase adjustment signal SPC from a control circuit 7 is supplied to a phase adjustment register 44. Phase adjustment signal SP
The digital value written into register 44 by C is supplied to horizontal reset circuit 42H.

In the horizontal reset circuit 42H, as shown in the example in FIG. 6, the phase of the reset signal . It is adjusted accordingly.

In this case, the falling edge of the reset signal W is
Within a predetermined period To before and after the rising edge of the phase lock signal PLH, V with the resolution of the reference clock CLK.
& adjusted.

In addition, since the falling edge of the reset signal W may be shifted within the period To before the rising edge of the phase lock signal PLH, in this example, the phase lock signal PIJI and the at-shumic are shifted one horizontal period before the rising edge of the phase lock signal PLH. Reset signal formed based on CK2 ■]τ]1
is used.

In addition, 11 is supplied as a count clock to the vertical address counter 43V by the reset signal [1] from the horizontal reset circuit 42H.

The present example is constructed as described above, and the rest is constructed similarly to the example in FIG. 5 and the example in FIG. 6.

In this example, as shown in FIG. 7J, the convergence correction signal DCL is delayed by the low-pass filter 14 and output, and as shown in FIG. 9, the position of the cursor C8 and the position where the convergence correction actually acts are When there is a deviation, the phase adjustment signal sPc from the control circuit 7 is changed to adjust the appropriate digital value written to the register 44 of the address generation circuit 4, thereby adjusting the reset signal IT' output from the horizontal reset circuit 42H. Adjust the phase of the T-block as shown in the third diagram. Figure A to C,
E-GC,: indicates the same signals as in FIG. 7, A-C and E-G.

By adjusting the phase of the reset signal τ in this manner, the reset timing of the horizontal address counter 43H is advanced, and the change timing of the horizontal address signal is also advanced (as shown in FIG. 3H).

Therefore, the correction data DCC from the frame memory 1o
The read timing is advanced, and the output timing of the signal DCA from the D/A converter 13 and the convergence correction signal DCL from the low-pass filter 14 is also advanced (as shown in FIG. 3, 1.J).

This makes it possible to match the position of the cursor cs with the position where the convergence correction actually acts, as shown in FIG.

In this way, according to this example, the control circuit 7 changes the phase adjustment signal SPC and adjusts the phase of the reset signal can be matched. Therefore, during adjustment, the position of the cursor C5 coincides with the portion where the convergence state changes due to adjustment of the correction data, and the correction data can be adjusted smoothly and accurately.

Note that if you adjust the position of the cursor C5 so that it matches the position where the convergence correction is applied as described above with the cursor C8 pointing to a certain correction point, then move the cursor C3. Even if you specify other correction points, the position where convergence correction works will be
Since the position of the moved cursor C5 remains the same, it is sufficient to adjust the position where the convergence correction is applied by - degrees.

[Effects of the Invention] As explained above, according to the present invention, the position where the convergence correction acts can be adjusted in the horizontal direction by the position adjustment means, and the cursor position and the position where the convergence correction acts can be made to match. becomes possible.

Therefore, during adjustment, the position of the cursor coincides with the portion where the convergence state changes due to adjustment of the correction data, and the correction data can be adjusted smoothly and accurately.

[Brief explanation of the drawing]

No. 11ffl is a configuration diagram showing an embodiment of the present invention, No. 2
The figure is a specific configuration diagram of the address generation circuit, Figures 3 and 4 are diagrams for explaining the operation of the example in Figure 1, Figure 5 is a configuration diagram of an example of the digital convergence correction circuit, and Figure 6 is its configuration. Specific configuration diagram of address generation circuit, Figures 7 to 91
! I is a diagram for explaining the operation of the example in FIG. 1 ・ 2 ・ 3 ・ 6, l 5 fist 7 ・ 8 ・ 9 ・ 10 ・ 11 ・ 12 ・ 13 ・ 14 ・ 16 ・ 41 ・ 42V ・ 42H ・ 43V Φ 43H・ ・PLL circuit・Timing generation circuit・Crosshatch generation circuit・Address generation circuit ・Adder ・Output terminal ・Control circuit ・Cursor generation circuit ・Address switching circuit ・Frame memory ・Nonvolatile memory ・Write switch ・D/A converter ・A-pass filter ・Data bus ・Cursor generation signal Output section/Vertical reset circuit/Horizontal reset circuit/Vertical address counter/Horizontal address counter 44 ・ ・Phase adjustment register

Claims (1)

[Claims] (1) The intersection of a cross-hatch pattern that equally divides the horizontal and vertical directions into a predetermined number of parts on the screen of a color picture tube is set as a correction point, and a frame memory that stores correction data at each correction point and a frame memory that stores the correction data at each correction point are used. A digital device comprising a non-volatile memory for storing the stored correction data at each correction point, reads out the correction data at each correction point from the frame memory in synchronization with the deflection timing, converts it into an analog signal, and performs convergence correction. Digital convergence correction characterized in that the convergence correction circuit is provided with a cursor display means for displaying a cursor on the screen corresponding to the correction point, and a position adjustment means for horizontally adjusting the position where the convergence correction acts. circuit.