JPH0440793A - Digital convergence correcting circuit - Google Patents

Abstract

PURPOSE:To well correspond to plural video signals with different scanning line numbers by providing a phase adjusting means to adjust the phase of a vertical system. CONSTITUTION:A vertical blanking signal PBLV, a phase lock signal PLH from a PLL circuit 1, an address clock ACK from a timing generating circuit 2 and a phase adjusting signal SPC from a control circuit 7 adding to an address assigning signal SCA from the control circuit 7 are supplied to an address generating circuit 4. Besides, a key to make the phase adjusting signal SPC change at phase adjusting is provided in the control circuit 7. That is, a phase adjusting means to adjust the phase of a vertical system is provided. Thus, the center of a cross pattern is adjusted so as to be in the center of a screen not according to the number of scanning lines of a video signal and proper convergence correcting is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a convergence correction circuit that digitally corrects the convergence of a color picture tube.

[Prior Art] FIG. 4 shows the configuration of a conventional digital convergence correction circuit.

In the figure, a PLL circuit 1 is supplied with a horizontal blanking signal PBLH and a vertical blanking signal PBLV (shown in FIG. 6A). The PLL circuit 1 outputs a reference clock CLK that is phase-synchronized with the blanking signals P BLH and P BLV, and also outputs a phase lock signal PLH that has the same period as the blanking signal P BLH.
(shown in Figure B) is output.

A reference clock CLK from the PLL circuit 1 is supplied to a timing generation circuit 2. Further, the timing generation circuit 2 is supplied with a vertical blanking signal PBLV and a phase lock signal PLH.

A crosshatch pattern generation signal SHG is supplied from the timing generation circuit 2 to the crosshatch pattern generation circuit 3.

A crosshatch pattern signal 5C for displaying a crosshatch pattern is output from the crosshatch pattern generation circuit 3.
)I (shown in the sixth diagram) is output, and this crosshatch pattern signal SCH is supplied to the output terminal 6 via the adder 5. When adjusting the convergence correction data (hereinafter referred to as "data adjustment time"), this crosshatch pattern signal SCH divides the screen of the color picture tube (not shown) into X equal parts horizontally and vertically. A crosshatch pattern is displayed that is equally divided into Y directions (X and Y are natural numbers).

The intersection of this crosshatch pattern becomes the convergence correction point. The coordinates of this correction point are <x, y) with respect to the upper left correction point. For example, X = 14, Y
= 10, the crosshatch pattern is the seventh
The coordinates (X, y) of the correction point are displayed as shown in the figure.
is (0,0) to (14°10).

Coordinates of cursor C8 and frame memory 10 to be described later
The address corresponds to the coordinates of this correction point.

The address generation circuit 4 also includes a timing generation circuit 2.
An address clock ACK synchronized with the reference clock CLKt is supplied. Furthermore, this address generation circuit 4
, a horizontal period phase lock signal PL is generated from the PLL circuit l.
)l is supplied, and the vertical blanking signal P B
LV is supplied.

When adjusting data, the control circuit 7 sends the address to the address generation circuit 4.
cursor designation signal SC that designates the coordinates of cursor O5 in
A is supplied, and the address generation circuit 4 outputs a cursor generation signal SCG at the timing when the electron beam scans the specified coordinate position.

FIG. 5 shows a specific configuration of the address generation circuit 4. As shown in FIG.

In the figure, address clock ACK, vertical blanking signal PBLV, and phase lock signal PLH are supplied to a cursor generation signal output section 41, and this signal output section 41 is further supplied with a cursor designation signal SCA.

The signal output section 41 includes a horizontal position down counter and a vertical position down counter, although not shown.

The vertical position down counter receives the cursor designation signal SC at the timing when the vertical blanking signal P BLV is supplied.
A count value indicating the vertical coordinate position designated by A is set and sequentially counted down by the phase lock signal PL)I.

On the other hand, the horizontal position down counter receives the cursor designation signal SCA at the timing of supplying the phase opening/picking signal PLH.
A count value indicating the horizontal coordinate position specified by is set, and is sequentially counted down in response to the address clock ACK.

Then, at the timing when the count values of both down counters become 0, the cursor generation signal SCG is output.

Returning to FIG. 4, the cursor generation signal SCG output from the address generation circuit 4 is supplied to the cursor generation circuit 8, which outputs a cursor signal 5C5 (shown in FIG. 6E).

This cursor signal SC5 is combined into a crosshatch signal SCH by an adder 5 and output to an output terminal 6.

Therefore, as shown in FIG. 7, a crosshatch pattern and a curve C8 are displayed at the designated coordinate position on the screen.

Additionally, a blanking signal P is output from the address generation circuit 4.
A synchronous address signal ADS is output in synchronization with BLV and PBLH, that is, in accordance with the scanning position of the electron beam.

In FIG. 5, the vertical blanking signal P8LV is supplied to the vertical reset circuit 42V, and a reset signal V7Y (shown in FIG. 6C) is output at the timing of the supply. The vertical address counter 43V receives this reset signal V.
] is reset to 1. This vertical address counter 43V is counted up by the phase lock signal PLH, and a vertical address signal (only 4 bits VO to 3 are shown in FIG. 6G) is output.

Furthermore, the horizontal reset circuit 42H is supplied with an address clock ACK and a phase lock signal PLH. From this horizontal reset circuit 42H, a reset signal ■] is sent from the horizontal reset circuit 42H at the timing when the phase lock signal PL)I becomes high level "1" at the beginning of each horizontal period and the address clock ACK becomes low level "0" for the first time. ]1 is output. The horizontal address counter 43H is reset by this reset signal
It is reset with 1. This horizontal address counter 43H is counted up by the address clock ACK, and a horizontal address signal is output.

The vertical address signal and horizontal address signal output from address counters 43V and 43H are output as a synchronous address signal ADS.

Returning to FIG. 4, the synchronous address signal ADS output from the address generation circuit 4 is supplied to the a-side fixed terminal of the address switching circuit 9.

The control circuit 7 described above is configured with, for example, a microprocessor, and includes keys (not shown) for adjusting data, keys for adjusting correction data, keys for moving a cursor C8, and the like. This control circuit 7 outputs a control address signal ADC, and this control address signal ADC is supplied to the b-side fixed terminal of the address switching circuit 9 and the nonvolatile memory 11. The address signal output from the address switching circuit 9 is then supplied to the frame memory 10.

The control address signal ADC output during data adjustment is
This corresponds to the coordinate position of the cursor C8.

On the other hand, the control that is output when the write switch 12 connected to the control circuit 7 is pressed and the correction data stored in the frame memory 10 is written to the nonvolatile memory 11 (hereinafter referred to as "data storage time") The address signal ADC is used to sequentially specify addresses of the frame memory 10 and the nonvolatile memory 11.

The frame memory 10 is for storing correction data at each correction point described above, and has a capacity to store correction data for one screen.

The nonvolatile memory 11 is for storing the correction data stored in the frame memory 10, and has a capacity that is, for example, 100N times that of the frame memory. Control circuit 7
A memory selection signal SMS for selecting a write area is supplied to the nonvolatile memory 10.

Note that writing or reading of the frame memory 10 and the nonvolatile memory 11 is controlled by the control circuit 7.

The address switching circuit 9 is supplied with an address switching signal SAS from the control circuit 7 . And address switching circuit 9
is connected to b@ during the vertical blanking period during data adjustment, and is connected to the a side during data adjustment except during the vertical blanking period. Further, the address switching circuit 9 is connected to the b side during the vertical blanking period during data storage,
During data storage, it is connected to the a side except during the vertical blanking period. Further, the address switching circuit 9 is connected to all except during data adjustment and data storage.

Correction data DCC read from frame memory 10
is converted into an analog signal by the D/A converter W13, smoothed by the low-pass filter 14, and then supplied to the output terminal 15.

The signal outputted to the output terminal 15 is supplied as a convergence correction signal to a convergence correction coil (not shown), where convergence is corrected.

In the above configuration, during the vertical blanking period during data adjustment, the frame memory 10 is in the writing state, the address switching circuit 9 is connected to the b side, and the frame memory 10 corresponds to the coordinate position of the cursor C8. A control address signal ADC is supplied. Therefore, the correction data that has been increased or decreased by the control circuit 7 is written to the address specified by the control address signal ADC of the frame memory 1° as the correction data of the correction point corresponding to the coordinate position of the cursor C5.

By moving the coordinate position of the cursor C8 using the control circuit 7, correction data for all correction points are adjusted in the same way.

During periods other than the vertical blanking period during data adjustment, the frame memory 10 is in a read state, the address switching circuit 9 is connected to all, and the frame memory 10 receives a synchronous address signal A corresponding to the scanning position of the electron beam.
DS is supplied. Therefore, the correction data DCC is read out sequentially from the address specified by the synchronous address signal ADS of the frame memory 10, and the correction data DCC
Convergence correction is performed in each part of the screen based on this.

That is, during this period, convergence correction is performed using the correction data written in the frame memory 10 during the vertical blanking period, so the degree of correction can be checked, and if the correction is not sufficient, the control circuit 7 uses the correction data. will be further adjusted to increase or decrease.

During the vertical blanking period when saving data, the frame memory 10 is in a read state, the nonvolatile memory 11 is in a blind state, the address switching circuit 9 is connected to bIl, and the frame memory 10 and the nonvolatile memory 1 are in a blind state.
1 is a control address signal ADC that sequentially specifies addresses.
is supplied.

Therefore, the correction data at each correction point is sequentially read from the frame memory IO, and this correction data is supplied to the nonvolatile memory 11 via the data bus 16, written therein, and stored.

At times other than data adjustment and data storage, the frame memory 10 is in a read state, the address switching circuit 9 is connected to the a side, and the frame memory 10 receives a synchronous address signal ADS corresponding to the scanning position of the electron beam. is supplied. Therefore, the correction data DCC is sequentially read out from the address specified by the synchronous address signal ADS of the frame memory 10, and convergence correction is performed in each part of the screen based on this correction data DCC. That is, during this period, a normal image on which convergence correction has been performed is displayed in each part of the screen.

Also, when turning the power off and then on again,
It works as follows.

First, the frame memory 10 is placed in a write state, and the nonvolatile memory 11 is placed in a read state. Address switching circuit 9 is connected to bgg, and frame memory 10 and nonvolatile memory 11 are supplied with a control address signal ADC that sequentially specifies addresses. Therefore, the correction data DCC at each correction point is sequentially read out from the nonvolatile memory 11, and this correction data DCC is transferred to the data bus 16.
The signal is supplied to the frame memory 10 via the frame memory 10 and written therein.

Next, the frame memory 10 is put into a read state, the address switching circuit 9 is connected to the a side, and the frame memory 10 is supplied with a synchronous address signal ADS corresponding to the scanning position of the electron beam. Therefore, the correction data DCC is sequentially read out from the address specified by the synchronous address signal ADS of the frame memory 10, and convergence correction is performed in each part of the screen based on this correction data DCC.

In order to simplify the explanation, in the example of FIG. 4, the circuit system from the frame memory 10 to the low-pass filter 14 is
Although only the systems are shown, there are actually three systems related to red, green, and blue, and convergence correction is performed by each system.

In this case, red, green, and blue correction data will be written in each frame memory 10 as described above.

[Problem to be solved by the invention] By the way, number 41! ! In the convergence correction circuit shown in Example I, the vertical components of the crosshatch pattern signal SCH, cursor signal SC5, and synchronous address signal ADS are formed by counting the phase lock signal PLH, and are formed by counting the phase lock signal PLH. Since it depends on the number of scanning lines, it cannot support multiple video signals with different numbers of scanning lines.

Therefore, the present invention is designed to be able to respond well to a plurality of video signals having different numbers of scanning lines.

[! ! ! [Means for Solving the Problem] This invention uses the intersection points of a crosshatch pattern that equally divides the screen of a color picture tube in the horizontal and vertical directions into predetermined numbers as correction points, and stores correction data at each correction point. and a non-volatile memory that stores the correction data at each correction point stored in the frame memory. After reading the correction data at each correction point from the frame memory in synchronization with the deflection timing, the analog signal is This is a digital convergence correction circuit that performs convergence correction by converting the signal into a vertical signal, and is provided with a phase adjustment means for adjusting the phase of the vertical system.

[Function] In the above configuration, the position adjustment means, for example,
Cross pattern signal SCR, cross hatch pattern signal S
C8, cursor signal SC5 and synchronous address signal A
The phase of the vertical component of the DS can be adjusted.

This makes it possible to adjust the center of the cross pattern to be at the center of the screen, regardless of the number of scanning lines of the video signal, and to perform appropriate convergence correction.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In this example, a cross pattern generation signal SRG is supplied from the timing generation circuit 3 to the cross pattern generation circuit 17. The cross pattern generation circuit 17 outputs a cross pattern signal 5CR (shown in FIG. 6F) for displaying a cross pattern, and this cross pattern signal SCR is supplied to the output terminal 6 via the adder 5. . When adjusting the vertical system phase (hereinafter referred to as "phase adjustment"),
This cross pattern signal SCR causes a cross pattern to be displayed on the screen of a color picture tube (not shown).

The address generation circuit 4 also receives a vertical blanking signal PBLV, a phase lock signal PLH from the PLL circuit 1, and an address clock AC from the timing generation circuit 2.
K, in addition to the addressing signal SCA from the control circuit 7,
A phase adjustment signal SPC is supplied from the control circuit 7. Note that the control circuit 7 is equipped with a key (not shown) that changes the phase adjustment signal SPC during phase adjustment.

FIG. 2 shows a specific configuration of the address generation circuit 4 in this example. In this figure, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the figure, a phase adjustment signal SPC from a control circuit 7 is supplied to a phase adjustment register 44. Phase adjustment signal SP
The digital value written to register 44 by C is supplied to vertical reset circuit 42V.

In the vertical reset circuit 42V, as shown in the example in FIG.
The phase of the reset signal (1), which is generated based on the above, is adjusted in accordance with the digital value supplied from the register 44.

In this case, the reset signal V][tau]1 is adjusted with the resolution of the phase lock signal PLH within a predetermined period To before and after the rising edge of the vertical blanking signal PBLV. In FIG. 6, the reset signal ■TT is
This shows the case where the adjustment is made to a position shifted by PSV from the rising edge of BLV.

By adjusting the phase of the reset signal W in this manner, the phase of the vertical address of the synchronous address signal ADS is adjusted (see C and G11 in FIG. 6).

Further, the reset signal V] 11 outputted from the vertical reset circuit 42V is supplied to the cursor generation circuit 8, the crosshatch pattern generation circuit 3, and the cross pattern generation circuit 17 as shown in FIG.

Then, the cursor signal SC output from each of these circuits
5. The phase of the vertical components of the crosshatch pattern signal SCH and crosshatch pattern signal SCR is determined by the reset signal ■]τ
11 (see FIG. 6C-F).

This example is constructed as described above, and the rest is constructed in the same manner as the example in FIG. 4 and the example in FIG. 5.

Here, one vertical period is assumed to be V, and from a horizontal line of a cross pattern (displayed during phase adjustment as described above) that equally divides the upper and lower parts of the screen, the upper side is assumed to be VU, and the lower side is assumed to be VD.

First, it is assumed that when the number of scanning lines is N, VU=VD as shown in FIG. 3A.

Next, when the number of scanning lines is N-α (α is a natural number), the third
As shown in FIG. B, VU>VD, and the center of the cross pattern is shifted downward.

When there is a deviation in this way, the phase adjustment signal SPC from the control circuit 7 is changed to adjust the digital value written to the register 44 of the address generation circuit 4, thereby adjusting the reset signal output from the vertical reset circuit 42V. The phase of V]τ11 is adjusted so that the state shown in FIG. 3A is obtained. In this case, the cross pattern signal SCR
As the phase of the vertical component of the cursor signal SCS, crosshatch pattern signal SC)l, and synchronous address signal ADS is adjusted, the phases of the vertical components of the cursor signal SCS, crosshatch pattern signal SC)l, and synchronous address signal ADS are also adjusted.

Furthermore, when the number of scanning lines is N+α, contrary to FIG. 3B, VU<VD, and the center of the cross pattern is shifted upward. Even when there is a deviation in this way, the phase adjustment signal SPC from the control circuit 7 is changed so that the state shown in FIG. 3A is achieved.

As described above, according to this example, even if the number of scanning lines of the video signal changes, the center of the cross pattern can be adjusted to be at the center of the screen by changing the phase adjustment signal SPC. Therefore, appropriate convergence correction can be performed regardless of the number of scanning lines of the video signal.

In the above embodiment, the phase adjustment signal SPC is adjusted by manually changing it while referring to the position of the cross pattern. may be provided, and the phase adjustment signal SPC may be automatically changed based on the count result.

[Effects of the Invention] As explained above, according to the present invention, even if the number of scanning lines changes, the phase of the vertical system can be adjusted by the position adjustment means so that, for example, the center of the cross pattern is at the center of the screen. can be adjusted to perform appropriate convergence correction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a specific block diagram of the address generation circuit, FIG. 3 is a diagram for explaining the operation of the example shown in FIG. 1, and FIG. 4 is a diagram of digital convergence. FIG. 5 is a block diagram of an example of the correction circuit, FIG. 5 is a specific block diagram of the address generation circuit, and FIGS. 6 and 7 are diagrams for explaining the example shown in FIG.・PLL circuit ・Timing generation circuit ・Crosshatch pattern generation circuit ・Address generation circuit ・Adder ・Output terminal ・Control circuit ・Cursor generation circuit ・Address switching circuit 2V 2H 3V ... Frame memory ... Nonvolatile memory ...・Write switch...D/A converter--Φ low-pass filter...Data bus...Cross pattern generation circuit...Cursor generation signal output section...Vertical reset circuit...Horizontal reset circuit・Vertical address counter ・Horizontal address counter ・Phase adjustment register

Claims (1)

[Claims] (1) The intersection of a crosshatch pattern that equally divides the horizontal and vertical directions into a predetermined number of parts on the screen of a color picture tube is set as a correction point, and a frame memory that stores correction data at each correction point and a frame memory that stores correction data at each correction point are used. A digital device comprising a non-volatile memory for storing the stored correction data at each correction point, reads out the correction data at each correction point from the frame memory in synchronization with the deflection timing, converts it into an analog signal, and performs convergence correction. A digital convergence correction circuit characterized in that the convergence correction circuit is provided with phase adjustment means for adjusting the phase of a vertical system.