JP2930299B2 - Digital convergence correction circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital convergence correction circuit used in a television receiver. SUMMARY OF THE INVENTION According to the present invention, digital correction data previously written in a memory corresponding to each position on a screen is sequentially read and converted into an analog signal, and then supplied to convergence correction means for convergence correction. In the digital convergence correction circuit, the read address signal for the memory is changed in accordance with the change in the number of scanning lines, the image size, and the like. Without rewriting
This is to enable good convergence correction. [Prior Art] FIG. 4 shows an example of a digital convergence correction circuit. In the figure, (21) is a memory (e.g., random access memory) that the correction data S _CN convergence corresponding to the screen each position is written. Also, (2
2) is a counter for the horizontal address signal generator, the predetermined times in the counter (horizontal sync pulse P _H to the clock terminal CLK to be supplied to the terminal (23) of 22) PLL circuit (24),
For example it is a 32-fold is supplied with, at its reset terminal R is the horizontal synchronizing pulse P _H is supplied to the terminal (23) is supplied. The output signal of the counter (22) is supplied to the memory (21) as a horizontal address signal _ADH6 . Further, (25) is a counter for the vertical address signal generator, with the horizontal synchronizing pulse P _H is supplied to be supplied to the counter (25) pin (23) to a clock terminal CLK, its reset terminal R vertical synchronizing pulse P _V which is supplied to the terminal (26) is supplied to the. The output signal of the counter (25) is supplied to the memory (21) as a vertical address signal AD _V. Thus the memory (21) to the address signal AD _H, the AD _V is supplied, the address signal AD _H from the memory (21),
Correction data S _CN in response to changes in AD _V are sequentially read out, the correction data S _CN is supplied to the convergence correction means, such as a convergence yoke (not shown) via the D / A converter (27) . Such a circuit is described in, for example, JP-A-50-68012. [Problems to be Solved by the Invention] In such a circuit, the correction data _SCN is written in the memory (21) in correspondence with the predetermined number of scanning lines, the image size, and the like. Therefore, when the number of scanning lines, image size, and the like match the state in which the correction data _SCN is written,
The correction data S _CN corresponding to from screen position memory (21) is read, but it is possible to good convergence correction, whereas when they do not match, the correction data S _CN in response to than the screen position memory (21) It is no longer read and good convergence correction is no longer possible. Assuming that the correction data S _CN (C _{00 to} C _nm ) of the screen position as shown in FIG. 5A is written in the memory (21), the number of scanning lines, the image size, etc. are written in the correction data S _CN . When the state coincides with the corrected state, the correction data S _CN (C _{00 to} C _nm ) is read at the screen position as shown in FIG.
For example, when the number of scanning lines increases, the correction data S _CN (C _{00 to} C _nm ) is read at the screen position as shown in FIG. Correction data S _CN (C _{00 to} C _nm ) at the screen position as shown in FIG.
Is read. In FIG. 5, (100) indicates the entire screen. Therefore, in such a circuit, the number of scanning lines,
Correction data in memory (21) according to changes in image size, etc.
Rewriting the S _CN has a disadvantage needed. In view of the above, the present invention does not rewrite the correction data in the memory even if the number of scanning lines, the image size, and the like change.
It is an object of the present invention to enable good convergence correction. Digital convergence correction circuit according to the present invention [Means for Solving the problems], a screen memory (1) the correction data S _CN convergence corresponds is written to each location, of the input video signal synchronization Clock generating means (2) for generating a clock by changing a generating pattern according to the number or range of scanning lines of an image defined by a signal, and counting a clock signal _SCP inputted from the clock generating means (2) Address generation circuits (9), (1)
0) and the address generation circuits (9), (1) of the memory (1).
A D / A conversion circuit (11) for converting the correction data read from the address specified in (0) into an analog signal;
And convergence correction means for correcting convergence according to the output signal from the / A conversion circuit (11). [Operation] In the above configuration, according to the clock pattern data S _CP to be written into the first memory (2) counter (9) and (10) is counted, the counter (9),
Since the read address signals AD _H ′ and AD _V ′ supplied to the second memory (1) from (10) change, the clock pattern data _SCP is changed to be written to the second memory (1). Correction data S _{CN for} each screen position
Read timing is changed. Therefore, in the above configuration, the number of scanning lines, by changing the clock pattern data S _CP to be written into the first memory (2) in accordance with a change in such image size, the number of scanning lines, and change the picture size, etc. Also, the correction data _SCN corresponding to the screen position can be read from the second memory (1). Embodiment An embodiment of the present invention will be described below with reference to FIG. In the figure, (1) is a memory (e.g., random access memory) that the correction data S _CN convergence corresponding to the screen each position is written. in this case,
The correction data _SCN is written in a state where the number of scanning lines is 525 lines / frame and the image size is normal, for example, 32 regions in the horizontal direction and 256 lines in the vertical direction. The memory (1) stores correction data S by the CPU (20) based on a signal from a misconvergence detecting means (not shown).
_CN is sequentially supplied and written in advance. (2) is a memory (for example, a random access memory) in which the clock pattern data _SCP is written. In this case, 8-bit data is written into each address of the memory (2), and a high-level "1" bit of each 8-bit data is used as a clock signal as described later. In this case, the clock pattern data _SCP is supplied from the CPU (20) to the memory (2) according to the number of scanning lines, the image size, and the like, and is written in advance. Also, (3) is a counter for generating a horizontal address signal, and a clock terminal CLK of the counter (3) is provided with a horizontal blanking pulse P _BLK supplied to a terminal (4) by a PLL.
The circuit (5) supplies the signal at a predetermined multiple, for example, 32 times, and a reset terminal R thereof is supplied with a horizontal blanking pulse P _BLK supplied to the terminal (4). The output signal of the counter (3) is supplied to the memory (2) as a horizontal address signal AD _H. Reference numeral (6) denotes a counter for generating a vertical address signal. A horizontal blanking pulse P _BLK supplied to a terminal (4) is supplied to a clock terminal CLK of the counter (6), and a reset terminal R thereof is provided. vertical synchronizing pulse P _V which is supplied to the terminal (7) is supplied to the. The output signal of the counter (6) is supplied to the memory (2) as a vertical address signal AD _V. The memory (2) to the address signal AD _H, the AD _V is supplied, the address signal AD _H from the memory (2), AD
8-bit clock pattern data S _CP according to the change of _V
Are sequentially read. The clock pattern data S _CP read from the memory (2) is converted is supplied to a parallel / serial conversion circuit (8) into serial data. In this case, although not described above, for example, the number of scanning lines is 525.
When the line / frame and image size are normal,
The serial data output from the conversion circuit (8) is high level "1" every 8 bits in the effective screen (40) of each line.
The clock pattern data _SCP is written into the memory (2) so that the bit becomes the high level “1” by one bit corresponding to the horizontal blanking pulse P _BLK of each line. FIG. 2 shows a pattern of the serial data on the screen, and a black dot indicates a high-level "1" bit. For example, when the number of scanning lines is 625 lines / frame and the image size is in a normal state, the conversion circuit (8)
The output serial data becomes high level "1" for every 8 bits of each line in the effective screen (40),
The clock pattern data _SCP is written in the memory (2) so that the ratio of the horizontal blanking pulse P _BLK to 5 lines out of approximately 6 lines corresponds to the high level “1” by 1 bit. FIG. 3 shows a pattern of the serial data on the screen, and a black dot indicates a bit of a black level “1”. Reference numeral (9) denotes a counter for generating a horizontal address signal. Serial data output from the conversion circuit (8) is supplied to a clock terminal CLK of the counter (9).
The counter (9) performs a counter operation at a high-level "1" bit portion of the serial data. The reset terminal R of the counter (9) is supplied with a horizontal blanking pulse P _BLK supplied to the terminal (4). The output signal of this counter (9) is supplied to the memory (1) as a horizontal address signal AD _H '. Reference numeral (10) denotes a counter for generating a vertical address signal. Serial data output from the conversion circuit (8) is supplied to a clock terminal CLK of the counter (10) via a connection switch (12). . The connection switch (12) has a horizontal blanking pulse P _BLK supplied to the terminal (4).
Is supplied as a control signal, and the connection switch (12) is turned on only during the pulse period of the horizontal blanking pulse P _BLK ,
Other periods are off. Therefore, the counter (10) calculates the horizontal blanking pulse of the serial data.
Count operation is performed at the high-level “1” bit corresponding to _PBLK . The reset terminal R of this counter (10)
The vertical synchronizing signal P _V which is supplied to the terminal (7) is supplied to the. The output signal of the counter (10) is supplied to the memory (1) as a vertical address signal AD _V '. Further, the address signals AD _H 'and AD _V ' are output from the memory (1).
Correction data S _CN in response to the change is read out sequentially, the correction data S _CN is supplied to the convergence correction means (not shown) such as a convergence yoke through a D / A converter (11). This example is configured as described above. When the number of scanning lines is 525 lines / frame and the image size is in a normal state, the serial data output from the conversion circuit (8) is transmitted to the effective screen (40) of each line. Becomes a high level "1" bit for every 8 bits of the horizontal blanking pulse P for each line.
_{Since the} clock pattern data _SCP is written in the memory (2) so that the bit becomes a high level "1" by one bit corresponding to the _BLK , the counter (9) is horizontal in the effective screen (40) of each line. The count operation is performed 32 times in the direction, and the count operation is reset every line by a horizontal blanking pulse _PBLK . The counter (10) with is made to the counting operation for every line, and is reset for each one vertical period by the vertical synchronizing pulse P _V. Here, the memory (1) has correction data S for 32 areas in the horizontal direction and 256 lines in the vertical direction when the number of scanning lines is 525 lines / frame and the image size is normal.
_CN has been written, from the memory (1) address signal AD _H ', AD _V' different correction data S _CN in each line according to the change of the Desa viewed sequentially location. Then, the correction data S _CN is supplied to the convergence correction means, such as a convergence yoke through a D / A converter (11). Therefore, at this time, assuming that the screen position correction data S _CN (C _{00 to} C _nm ) as shown in FIG. 5A is written in the memory (1), the screen position as shown in FIG. When the correction data S _CN (C _{00 to} C _nm ) is read, excellent convergence correction can be performed. When the number of scanning lines is 625 lines / frame and the image size is in a normal state, the serial data output from the conversion circuit (8) becomes high level every 8 bits in the effective screen (40) of each line. 1 "bit, and the horizontal blanking pulse P at a rate of 5 out of 6 lines
_{Since the} clock pattern data _SCP is written in the memory (2) so that the bit becomes a high level "1" by one bit corresponding to the _BLK , the counter (9) is horizontal in the effective screen (40) of each line. The count operation is performed 32 times in the direction, and the count operation is reset every line by a horizontal blanking pulse _PBLK . The counter (10) with is adapted to count operation five lines of approximately 6 lines, the vertical synchronizing pulse P _V 1
Reset every vertical period. Here, the memory (1)
The 525 lines / frame number of scanning lines, the horizontal direction 32 region image size is in a normal state, the correction data S _CN in the vertical direction 256 lines have been written, substantially from the memory (1) 6 Different correction data _SCN are read out for every five lines among the lines, and the same correction data _SCN as the previous line is repeatedly read out for the remaining one line. Then, the correction data S _CN is supplied to the convergence correction means, such as a convergence yoke through a D / A converter (11). In this case, too, the correction data S _CN (C ₀₀ to C ₀₀ ) of the screen position as shown in FIG.
_Assuming that C _nm ) has been written, the correction data S _CN (C _{00 to} C _nm ) is read at the screen position as shown in FIG. B, and good convergence correction can be performed. According to the present embodiment, even if the number of scanning lines is changed, this is rewritten clock pattern data S _CP to be written into the memory (2) correspondingly, the memory correction data S _CN is written (1 ) For read address signal A
Since D _H ′ and AD _V ′ are changed, the correction data _SCN corresponding to the screen position is read, and good convergence correction can be performed. In the above-described embodiment, the example in which the number of scanning lines is changed from 525 lines / frame to 625 lines / frame has been described. Correction data written
Can be similarly configured as S _CN are read in the correct screen positions. In this case, when the number of scanning lines is changed to be larger than the number of scanning lines in the state in which the correction data _SCN is written, the counting operation of the counter (10) is not performed for each line as in the above-described embodiment, but appropriately. This can be realized by writing the clock pattern data _SCP into the memory (2) so as to thin it out. On the other hand, when the number of scanning lines is changed to a small value, the counting operation of the counter (10) is not performed once for each line. in may be realized by writing the clock pattern data S _CP to increase appropriately the memory (2). Further, in the above-described embodiment, an example in which the number of scanning lines is changed has been described. However, even when the image size is changed, the correction data written in the memory (1) may be changed.
As S _CN are read in the correct screen positions can be similarly configured. For example, when it is changed to the reduced screen, the counter (9), (10) also to rapidly counting until reduced screen position, so that the gently count operation in reduced screen clock pattern data S _CP Is written in the memory (2). Further, upon writing the correction data S _CN in memory (1), screen center rough in order to improve the convergence adjustment accuracy, surrounding even in those written finely Similarly clock pattern data S to be written into the memory (2)
_The configuration can be easily made by changing the _CP . [Effects of the Invention] According to the present invention described above, the clock pattern data is changed according to changes in the number of scanning lines, image size, and the like, and the read address signal for the memory is changed. Even if the image size or the like changes, excellent convergence correction can be performed without rewriting the correction data _SCN in the memory, and the image quality can be improved. Therefore, the present invention is suitable for application to a case where the misconvergence detection point is fixed to the screen coordinates of the cathode ray tube, such as autoconvergence, in which the number of scanning lines, image size, and the like change.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams for explaining the embodiment, and FIG. 4 is a block diagram of an example of a digital convergence correction circuit. FIG. 5 is a view for explaining this. (1) and (2) are memories, (3) (6) (9) and (10) are counters, (4) and (7) are terminals, and (5) is
PLL circuit, (8) parallel / serial conversion circuit, (1
1) is a D / A converter.

   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-60-33791 (JP, A)                 JP-A-61-12191 (JP, A)                 JP-A-60-130288 (JP, A)                 JP-A-62-11388 (JP, A)                 JP-A-61-152188 (JP, A)                 JP-A-61-72492 (JP, A)

Claims (1)

(57) [Claims] A memory in which convergence correction data is written corresponding to each position on the screen, clock generation means for generating a clock by changing a generation pattern in accordance with the number of image scanning lines or the image size of the input video signal, An address generation circuit that counts a clock signal input from the clock generation means to generate a read address of the memory; and an analog signal that outputs the correction data read from the address specified by the address generation circuit of the memory. A digital convergence correction circuit comprising: a D / A conversion circuit for converting the data into a digital signal;