GB2101459A

GB2101459A - Television display correction

Info

Publication number: GB2101459A
Application number: GB08121037A
Authority: GB
Inventors: Kenneth George Freeman; Alan George Knapp
Original assignee: Philips Electronic and Associated Industries Ltd
Current assignee: Philips Electronics UK Ltd
Priority date: 1981-07-08
Filing date: 1981-07-08
Publication date: 1983-01-12

Abstract

To correct vertical distortion on a CRT, with large angle or flat screen, a field frequency sawtooth from generator 1 is added to a correction waveform, the sum signals being converted 3 into deflection current through coil 4, producing a pre- distorted deflection field. The correction is derived from digital data in RAM's 5 and 12, converted to analogue 10, 13 and interpolated at line and field rate by an interpolator 14 feeding adder 2. Generator 7 receives field and line synch inputs from 6, 8 and generates addresses applied via multiplexer 9 to RAM 5 and via adder 11, which adds a binary '0' to the address code, to the RAM 12. The data read from RAM 5 relates to the field direction errors across the display row-by-row, while that read from RAM 12 relates to the row below that read from RAM 5. The error information is previously loaded into the RAM's 5 and 12 from data input 32 with the addresses being applied through input 31 to the multiplexer 9, the circuit having previously been set for load operation via control input 30. A similar circuit may be used for errors in the horizontal direction. <IMAGE>

Description

SPECIFICATION Television display correction The invention relates to a television deflection arrangement for producing a deflection magnetic field from a deflection unit for causing a beam to be deflected across a television display in one of its transverse directions so as to produce an image which when viewed is substantially geometrically distortion free, said arrangement comprising means for producing a main current component at the deflection frequency for application to said deflection unit and means for producing a correction current component from correction signals also for application to said deflection unit such that said deflection unit produces the deflection magnetic field required for the deflection of said beam to produce said substantially geometrically distortion free image.

Such an arrangement is described in our United Kingdom Patent Specification 1,124,306 where the deflection current at field frequency is applied to a winding of a transductor to another winding of which are applied pulses at line frequency. The line frequency pulses modulate the field frequency scan current such that pin cushion distortion at the top and bottom of the display (known as the N-S direction) is corrected. The correcting waveform generated by the transductor was of a shape such that only pincushion distortion (or its inverse, namely barrel distortion) could be corrected for and the arrangement was typically used with delta-gun colour cathode ray tubes having a maximum deflection angle of 900.The arrangement however, had the considerable advantage that it provided at the same time correction for pincushion distortion at the sides of the display (known as the E-W direction). With currently used colour cathode ray tubes with the electronguns arranged "in-line" and a maximum deflection angle up to 1100 it has been found possible to modify the magnetic field in the field direction by the shaping of the appropriate deflection coils and/or the addition of magnetic elements to the deflection unit.

For cathode ray tubes having a maximum deflection angle greater than 1100 and/or having flat screens the above measures cannot be used satisfactorily for the correction of pin-cushion distortion. Also with projection television pincushion distortion. Also with projection television pin-cushion or barrel and other geometric distortions such as non-linearity and keystone require correction to provide a rectangular display. Such non-linearity may also be present in direct viewed cathode ray tubes.

It is an object of the invention to provide an arrangement which is capable of providing corrections for such geometric distortions.

The invention provides an arrangement of the type described in the opening paragraph which is characterised in that said correction signals are stored in a store in digital form each stored signal representing the amount of geometric distortion in said one direction of discrete points or regions of an uncorrected display which would be produced in the absence of said correction current component, means for addressing the store for reading out therefrom a correction signal in digital code form at a time or times appropriate for said display, a digital to analogue converter for converting said digitally coded correction signals into analogue correction signals, and means for producing said correction current component from said analogue corrections signals.

With arrangements according to the invention the beam which is caused to be deflected by the deflection coil will be the electron beam in a direct view cathode ray display tube whilst when the arrangement is used in a projection television system the beam will be the beam of light from a projection tube resulting from the tube's magnetically deflected electron beam.

The correction signals may be subjected to interpolation in the line direction and this may be achieved by the integration of each analogue correction signal.

The correction signals may also be subjected to interpolation in the field direction. This may be achieved by the arrangement further comprising a second store for storing correction signals in digital form corresponding to those stored in the first mentioned store, means for addressing the second store for reading out therefrom correction signals digital code form corresponding to points or blocks spaced adjacent in the field direction to those read out from the first store, and means for interpolating between the correction signals being concurrently read out from the first and second stores.Alternatively, the store may be addressed such that correction signals for points or regions adjacently positioned in the field direction are sequentially read-out from the store and loaded in the given sequence in the first and second latch circuits with means for interpolating between the corrections signals present in these latch circuits. A second digital to analogue converter may be provided for converting the digitally coded correction signals from the second store or the second latch circuit into second analogue correction signals, the first mentioned and the second analogue correction signals being subjected to interpolation in the field direction.The output of the first mentioned and the second digital-to-analogue converter may be connected to a first summing circuit for producing the difference between the first and second analogue correction signals corresponding at any one time to adjacent points in the field direction which points are spaced by a given number of lines per field, means for applying the resulting difference signal from the first summing circuit to an analogue multiplier for producing an incremental portion of the difference signal the magnitude of which is dependent upon the position of a line being displayed relative to the said given number of lines, means for applying the incremental output from the analogue multiplier circuit to a second summing circuit and means for applying one of the analogue correction signals also to the second summing circuit, to produce a correction signal interpolated in the field direction. Interpolation in the line direction of the correction signals will preferably take place after the correction signals have been subjected to interpolation in the field direction.

An arrangement according to the invention may further comprise a generator for producing a sawtooth deflection waveform at the deflection frequency, means for summing the sawtooth waveform and the analogue corrections signals, means for applying the summed signals to a voltage to current converter and means for applying the output of the converter which comprises the main current component and the correction component to the deflection unit.

The main current component and the correction current component may instead be added to each other prior application to the deflection unit.

Alternatively, the deflection unit may comprise first and second magnetically coupled deflection coils, the deflection current being applied to the first deflection coil whilst the correction current is applied to the second deflection coil.

The invention also provides television display apparatus comprising a direct view cathode ray tube and an arrangement as above disclosed.

The invention further provides television projection apparatus comprising a plurality of projection cathode ray tubes and a corresponding number of arrangements as above described.

With such apparatus common address means may be employed for all the arrangements.

The above and other features of the invention will be hereinafter described, by way of example, with reference to the accompanying drawings in which: Figure 1 is a block diagram of an arrangement according to the invention, Figure 2 is a diagrammatic representation of a television display for explaining the operation of Figure 1, Figure 3 is a block diagram of an address generator for use with the arrangement of Figure 1, Figure 4 is a block diagram of a field interpolator for use with the arrangement of Figure 1, and Figure 5 is a block diagram of a modification of part of Figure 1.

In Figure 1 the reference 1 indicates a field ramp generator which generates a sawtooth waveform having a deflection portion and a flyback portion, the frequency of the sawtooth being that of the field frequency of the television apparatus in which the arrangement is to be used.

The sawtooth output of the generator 1 is applied to a first input of a summing circuit 2 whose other input will receive a correction signal as hereinafter explained. The summed signals from the summing circuit 2 are applied to the input of a voltage to current converter 3 which may be in the form of class A amplifier or some other suitable form of converter. The output of converter 3 is applied to the field deflection coils 4 of the apparatus for deflecting an electron beam in the field direction of the display. If the display was a direct viewed cathode ray display tube then the beam or beams falling on the display screen might exhibit a number of geometric distortions should the sawtooth waveform alone from the generator 1 be used to provide the deflection current for the field deflection coils 4.For one scan direction a typical geometric distortion would be pin-cushion distortion in the northsouth direction i.e. at the top and bottom of the display when viewed in the normal manner.

Should however the display be that of a television projection system the beam of light falling on the viewing screen due to the movement of an electron beam across the screen of a projection tube or tubes can produce a number of other geometric distortions in addition to the northsouth pin-cushion distortion. Such other distortions can be keystone or trapezium distortion due to the positioning of the projection tube(s) relative to the viewing screen, tilt or possibly non-linearity. For the above reasons, it is necessary to add a correction signal to the sawtooth waveform in order to provide a magnetic deflection field from the field deflection coils which will overcome the above errors at the display.

The manner of obtaining the correction signal will be further explained with reference to Figure 2 which diagrammatically shows such a display.

From this Figure it will be seen that the display has been divided into rows of blocks with 1 6 blocks per row in the line direction, i.e. across the drawing with 1 6 rows in blocks in the field direction i.e. in the direction transverse to the line direction. Thus, the display is divided into 256 separate blocks.

If for a point in each block the amount of geometric distortion in the field direction is measured when only a sawtooth waveform is used for deflection of the beam across the display the measured amount of distortion for each such point or preferably a correction quantity required to give a distortion corrected display at such point can be stored as a digital quantity in some form of digital store. At appropriate times during the generation of the raster on the display these digital quantities may be read-out sequentially from the store, converted into the appropriate analogue quantity and the resulting correction signal added to the sawtooth waveform to produce a corrected deflection current through the field deflection coils which in turn will produce the required undistorted display. Each block in the 1 6x 1 6 matrix over the display is assigned an address as shown in Figure 2 which is in Hexadecimal form producing an 8-bit binary number for each block the first four bits defining the block position in the field direction whilst the last four bits define the block position in the line direction.

Returning now to the description of Figure 1, the magnitude of the correction required for each point of the display is stored as an 8-bit code for the 256 blocks in a first digital store 5 which in this described embodiment is a random access memory (RAM). At an input terminal 6 field synchronising pulses are received for application to the field ramp generator 1 for synchronising the operation of that generator in normal manner.

These field synchronising pulses are also applied to an address generator 7 the details of which will be described hereinafter. The address generator 7 also receives line synchronising pulses from an input terminal 8 and from these two synchronising pulse inputs the address generator 7 produces sequentially the discrete 8-bit address code for each block of the display row by row as described with reference to Figure 2, the resulting train of 8-bit address codes being applied to a multiplexer 9 set to apply these address codes to the address input of the digital store 5 causing the required 8-bit digital correction signals to be readout sequentially and row by row from the store for the appropriate blocks on the display.Each digital correction signal is applied to a digital-toanalogue converter 10 where it is converted into an analogue correction signal of an amplitude such as to provide the required modification of the current through the field deflection coils 4.

The train of address codes at the output of the multiplexer 9 is also applied to an adder circuit 11 where a binary 1 is added to the field address portion of the address code. The modified address code from the adder 11 is applied to a second digital store 12 also in the form of a RAM in which information is stored which corresponds to that present in the first digital store 5. This results in the address code applied to the second digital store 12 at any one time relating to the corresponding block in a row below that for which an address code is applied at that time to the first digital store 5. The digital correction signals being read from the second digital store 12 therefore relate to a row below the digital correction signals being simultaneously read-out from the first digital store 5.The resulting 8-bit digital correction signal from the digital store 1 2 are applied to a second digital-to-analogue converter 1 3 to produce analogue correction signals which relate to one row below those being produced by the digital-to-analogue converter 10. The analogue correction signals from the converters 10 and 13 are applied to an interpolator 14 for providing interpolation in the line and field directions of the correction signals. The resulting interpolated correction signals are then fed to the second input of the summing circuit 2 to provide the required correction as previously described.

Figure 3 shows in greater detail the address generator 7, digital stores 5 and 12 and the adder circuit 11 of Figure 1 , the multiplexer 9 having been omitted from this Figure as here it is assumed that the signals are applied straight through the multiplexer 9. In Figure 3, the line frequency synchronising pulses are applied from the input terminal 8 to a clock generator 1 5 which generates a pulse train of 1 6 pulses in response to each line sync. pulse. The output of generator 1 5 is applied to a 4-bit counter 1 6 which produces 1 6 unique 4-bit binary address codes per line period sequentially representing the 1 6 difference block positions in the line direction across the display.The counter 1 6 has a reset input R which also receives line synchronising pulses from terminal 6 to reset this counter when it has counted to its maximum count per line. The line frequency pulses at terminal 8 are also applied to a divide by 20 stage 1 7 which produces a single pulse output for every 20 line frequency pulses received. The output of divider 1 7 is applied to a second 4-bit binary address counter which also produces 16 unique binary 4bit codes per field period sequentially representing the 1 6 different block positions (i.e.

the rows) in the field direction down the display.

Counter 1 8 has a reset input R which receives field synchronising pulses from terminal 6 which resets this counter when it has counted to its maximum count per field. The 4-bit address codes from counter 1 6 are applied as the last 4-bits of the 8-bit address codes to the digital stores 5 and 12 whilst the 4-bit address codes from the counter 1 8 are applied as the first 4-bits of the 8bit codes to the digital store 5.The output of the counter 1 8 is also applied to the first inputs of the 4-bit binary adder circuit 11 to second inputs of which a binary 1(0001) is applied and which is added to the first inputs to produce 4-bit address codes which are one higher than those produced by the counter 16, the address codes from counter 1 8 being applied as the first 4-bits of the 8-bit address codes for the digital store 12. The address codes for the digital store 1 2 always relate to one row below the address codes for the digital store 5. With the above address generator the respective sequence of unique address codes applied to the respective digital store 5 or 12 is repeated for each of the twenty lines which is the height of each row in the field direction.

Figure 4 is a block diagram of the field interpolating portion of the interpolator 14 in which the terminal 1 9 receives the analogue correction signals (sun) from the output of the digital-to-analogue converter 10 which signal is applied to the non-inverting input of an amplifier 20 the non-inverting input of which is connected to an input 21 which receives the analogue correction signals (sun+1) from the output of the digital-to-analogue converter 13. The amplifier 20 has unity gain and produces at its output a signal which is the difference between the analogue signalstat the input 19 and 21, this output -(Sn+1Sn) being applied to the first input of an analogue multiplier circuit 22. A terminal 23 receives line synchronising pulses which are applied to a digital counter 24 and which produces a binary coded output counting from 0 to 20, the counter being reset when it has reached a binary count of 20 by a pulse which is applied to its reset terminal R from a terminal 25 which is derived from the output of the divide by 20 stage 1 7 shown in Figure 3. The binary output from the counter 24 is applied to digital-toanalogue converter 26 to produce as shown at 27 a staircase waveform over a 20 line period with 20 equal incremental steps successive steps each having a step magnitude of V, the voltage level at any time having a value of V(m-1) where m is the line number in each block and hence the step in the staircase waveform.The staircase waveform 27 is applied to the second input of the analogue multiplier circuit 22 which sequentially produces at its output a portion of the difference signal from amplifier 20 incrementally changing from 1/20 to the whole of the difference signal over the 20 line periods of each block. This output which is -V(m-1) (Sn+iSn) where a is the multiplier gain is applied to the non-inverting input of a second amplifier 28, the inverting input of which receives the analogue correction signal Sn present at the terminal 1 9.

These inputs are summed in the amplifier which has unity gain and thus for each of the 20 lines present in a row correction signals interpolated in the field direction are produced at the output 29 resulting from correction signals for adjacent blocks in the field direction. The output from the amplifier 28 is -[S+aV(m-1) (Sn+iSn)1 and if a and V are chosen such that .V=1/20 the output for line 1 will be Sn and each line will be incremented by an amount (SnSn+,)/20 until the last line in each row when the output has a value of

For the examples given the values Sn and Sn+1 are of opposite polarity to the required correction signals, the signal after interpolation being of the correct polarity.

After such field interpolation the resulting signals are interpolated between adjacent interpolated values (16 per line) in the line direction this being achieved by means of an integrator having a suitable time constant.

The description in relation to Figure 1 has been concerned with the reading out of the digital correction signals rom the two digital stores 5 and 12. At such times these digital stores are in the READ mode and are set for operation in this mode by a control signal present at an input terminal 30 which is applied to the control inputs C of the two digital stores. The control signal is also applied to the control input C of the multiplexer 9 to allow the address codes from the address generator 7 to pass to its output and to the control input C of the adder circuit 11 to cause it to add a binary 1 to the field portion of the address codes as previously described.When data relating to the correction quantity is to be loaded into the digital stores 5 and 12 at their terminals D the control signal at terminal 30 is changed such that the two stores are set to their WRITE mode, the multiplexer 9 is set to prevent address codes from the address generator 7 being applied to the stores 5 and 12 but to allow address codes applied to its second input from an address input terminal 31 to be applied to these stores, and the adder circuit 11 is prevented from adding a binary 1 to the field portion of the address codes as the data to be loaded into the digital store 1 2 is the same as that to be loaded into the digital store 5. The data relating to the amount of geometric distortion is applied through a data input terminal 32 to the data inputs D of the digital stores 5 and 12.Together with the corresponding address applied to the address input 31 , the data being loaded by briefly switching the stores into their WRITE mode Thus data will come from an external source which may comprise a set of switches or a computer, the values required at each point having been calculated from measurements made on the distorted display. Alternatively, the values may be generated and loaded automatically by the use of a television camera observing the display, the viewed display shape being analysed using a computer to produce the required values.

With the arrangement as so far described use is made of two digital stores from which digital correction signals relating to adjacent blocks in the field direction are read-out simultaneously.

Figure 5 shows a modification and extension of Figure 3 which can be used in a modified Figure 1 arrangement, and in which like reference numerals used in the previous Figures 1 and 3 indicate like components. The block diagram in Figure 5 shows the use of only one digital store 5 and this is addressed in a similar manner to that described with reference to Figure 5, the line address being supplied by the 4 binary bits from the 4-bit binary counter circuit 1 6 whilst the field address is supplied from; the 4-bit binary counter circuit 1 8 via the adder circuit 11.At the start of a block the second input of the adder circuit 11 receives a binary 0 (0000) and thus the field portion of the address code applied to the digital store 5 is as produced by the counter 1 8. The digital correction signal read-out from the digital store 5 is simultaneously applied to the data input of a first (30) and a second (31) 8-bit latch circuit.

At the start of a block a pulse having a length which is short compared with the length of a block is applied via a terminal 32 to the ENABLE input E of the latch circuit 30 and the correction signals from the digital store 5 are loaded into that latch circuit. At that time no pulse is applied to the ENABLE input E of the latch circuit 31 and so that latch circuit is not loaded with the correction signals present at its data input. Immediately following or on the termination of the above mentioned short pulse applied to terminal 32 a correspondingly short pulse is applied to a terminal 33 connected to the ENABLE input of latch circuit 31 and to the second input of the adder circuit 11 to provide a binary 1 (0001) at that input.The adder circuit 11 consequently adds the binary 1 to the field portion of the address code such that digital correction signal read-out from the digital store 5 relates to the adjacent block in the field direction to that previously read out. With no pulse now present at the terminal 32 the changed output from digital store 5 cannot be loaded into the latch circuit 30 which retains the previous signal. However, the pulse at terminal 33 and hence at the ENABLE input E of latch circuit 31 causes the changed correction signal to be loaded in that latch circuit.

Thus close to the start of a block correction signals are loaded into the two latch circuits for that and an adjacent block in the field direction.

The loaded information is then operated on in the same way as in Figure 1 with the information first being applied to the first and second digital-toanalogue converter circuits 10 and 1 3.

In a modification of Figure 5 the digital information for the adjacent blocks in the field direction could be loaded into the latch circuits 30 and 31 immediately prior to the display of the relevant block rather than at the start of this block. This would then require the addition of a further pair of latch circuits each of which follows the present latch circuits 30 and 31. These further latch circuits could be incorpora.ted into the digital-to-analogue converter circuits 10 and 1 3 or could be separate circuits. The further latch circuits would be simultaneously enabled at the start of each block in the line direction.

In the above description of Figures 1 and 4 interpolation in the field direction is provided. If a large digital store were to be provided it would be possible to use blocks or rows which in the field direction were only 2 or 3 lines deep which would provide 1 56 or 104 blocks in this direction. In such a case interpolation in the field direction would not be required and the adder circuit 11, second digital store 1 2 and the second digital-toanalogue circuit 13 as well as the field interpolator 14 could be omitted.

With Figure 1 the correction signal is added to the sawtooth signal prior to converting these voltage signals into the deflection current. It is alternatively possible for the sawtooth signal to be converted to a current and the correction signal to be separately converted to a correction current with the two currents being summed at the field deflection coil. In one such arrangement the field deflection coil could be formed of two windings preferably magnetically coupled with the sawtooth current being applied to one winding and the correction current being applied to the other winding.

So far arrangements have been described relating to the correction of errors in the field direction only but similar arrangements can be used for the correction of such errors in the line direction. With Figure 1 the only changes that would need to be made would be to replace the field ramp generator 1 with a line ramp generator and the field deflection coils 4 by line deflection coils with the appropriate correction data stored in the stores 5 and 12. When the correction current is added to the sawtooth current a conventional pulsed line generator circuit could be employed and in such a case the ramp generator 1 would not be required. If correction in both the line and field directions were to be provided then a common generation of the address codes could be used for both directions.

With the arrangements and modifications described above the interpolation in the two deflection directions takes place on the analogue correction signals. The action of interpolation could however be carried out on the digital correction signals in which case only one digitalto-analogue converter would be required following the interpolator rather than the two digital-to-analogue converters which precede it in the arrangement described in reiation to Figure 1.

Claims

1. A television deflection arrangement for producing a deflection magnetic field from a deflection unit for causing a beam to be deflected across a television display in one of its transverse directions so as to produce an image which when viewed is substantially geometrically distortion free, said arrangement comprising means for producing a main current component at the deflection frequency for application to said deflection unit and means for producing a correction current component from correction signals also for application to said deflection unit such that said deflection unit produces the deflection magnetic field required for the deflection of said beam to produce said substantially geometrically distortion free image, characterised in that said correction signals are stored in a store in digital form each stored signal representing the amount of geometric distortion in said one direction of discrete points or regions of an uncorrected display which would be produced in the absence of said correction current component, means for addressing the store for reading out therefrom a correction signal in digital code form at a time or times appropriate for said display, a digital to analogue converter for converting said digitally coded correction signals into analogue correction signals, and means for producing said correction current component from said analogue correction signals.

2. An arrangement as claimed in Claim 1, characterised in that said correction signals are subjected to interpolation in the line direction.

3. An arrangement as claimed in Claim 2, characterised in that said line direction interpolation is achieved by the integration of said analogue correction signal.

4. An arrangement as claimed in Claim 1, or 2, characterised in that said correction signals are subjected to interpolation in said field direction.

5. An arrangement as claimed in Claim 4, characterised in that said arrangement further comprises a second store for storing correction signals in digital form corresponding to those stored in said first mentioned store, means for addressing said second store for reading out therefrom correction signals in digital code form corresponding to points or regions spaced adjacent in the field direction those read out from said first store, and means for interpolating between the correction signals being concurrently read out from said first and second stores.

6. An arrangement as claimed in Claim 4, characterised in that said store is addressed such that correction signals for points or regions adjacently positioned in the field direction are sequentially read-out from said store and loaded in the given sequence in first and second latch circuits, and means for interpolating between the correction signals present in said latch circuits.

7. An arrangement as claimed in Claim 5, characterised in that said arrangement further comprises a second digital-to-analogue converter for converting the digitally coded correction signals from said second store or said second latch circuit into second analogue correction signals, the first mentioned and said second analogue correction signals being subjected to said interpolation in said field direction.

8. An arrangement as claimed in Claim 7, characterised in that the output of the first mentioned and the second digital-to-analogue converter is connected to a first summing circuit for producing the difference between the first and second analogue correction signals corresponding at any one time to adjacent points in the field direction which points are spaced by a given number of lines per field, means for applying the resulting difference signal from said first summing circuit to an analogue multiplier for producing an incremental portion of said difference signal the magnitude of which is dependent upon the position of a line being displayed relative to said given number of lines, means for applying the incremental output from said analogue multiplier circuit to a second summing circuit and means for applying one of said analogue correction signals also to said second summing circuit, to produce a correction signal interpolated in the field direction.

9. An arrangement as claimed in Claims 4, 5, 6, 7 or 8, characterised in that interpolation in the line direction of said correction signals takes place after said correction signals have been subjected to interpolation in the field direction.

10. An arrangement as claimed in any of the preceding claims characterised in that said arrangement further comprises a generator for producing a sawtooth deflection waveform at the deflection frequency, means for summing said sawtooth waveform and said analogue correction signals, means for applying said summed signals to a voltage to current converter and means for applying the output of the converter which comprises the main current component and the correction component to said deflection unit.

11. An arrangement as claimed in any of the preceding Claims 1 to 9, characterised in that said main current component and said correction current component are added to each other prior to application to said deflection unit.

12. An arrangement as claimed in any of the preceding Claims 1 to 9, characterised in that said deflection unit comprises first and second deflection coils, said main current component being applied to said first deflection coil whilst said correction current component is applied to said second deflection coil.

13. A television deflection arrangement substantially as herein described with reference to the accompanying drawings.

1 4. Television display apparatus comprising a direct view cathode ray display tube and an arrangement as claimed, in any one of the preceding claims.

1 5. Television projection apparatus comprising a plurality of projection cathode ray tubes and a corresponding number of arrangements as claimed in any of the preceding Claims 1 to 13.

1 6. Television projection apparatus as claimed in Claim 15, characterised in that common address means are employed for the said arrangements.