JPH03250876A - Video signal display device - Google Patents

Abstract

PURPOSE:To display 1st and 2nd video images without a blank automatically corresponding to the 1st video image written in an optional range by storing the end of write of the 1st video signal by a latch circuit and allowing a comparator decoder circuit to discriminate the readout over the write and selecting the display of the 2nd video signal. CONSTITUTION:A control signal output of a comparator decoder circuit 16 resulting from a write address and a readout address latched by a latch circuit 15 is used for changeover control of a video signal switching circuit 12. The latch circuit 15 latches and stores an address just before the write address is reset and the comparator decoder circuit 16 compares the quantity between the readout address and the latched address and outputs a switching control signal when the readout address is larger than the latched address. Thus, the 1st and 2nd video signals are switched and displayed without a blank corresponding to the 1st video signal written in an optional range.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal display device that displays two video signals on one screen.

2. Description of the Related Art In recent years, digital technology has become widely used for displaying images. Conventionally, when a plurality of images were simultaneously displayed on a television receiver, they were displayed in a predetermined size, and signal processing was performed with the time relationship between horizontal and vertical synchronizations also kept almost constant.

An example of a conventional technique will be described below with reference to the drawings.

FIG. 3 is a block diagram of a conventional video signal display device.

As shown in the figure, a conventional video signal display device has an input terminal 1 for a first video signal, an input terminal 2 for a second video signal, and a synchronization signal separation circuit that separates the synchronization signal of the first video signal. 3, a reset signal generation circuit 14 that generates a seven-segment signal from the synchronization signal, a synchronization signal separation circuit 4 that separates the synchronization signal of the second video signal, and a synchronization signal of the first video signal. A write address generation circuit 6 to be reset, a reading ratio address generation circuit 6 generated based on the synchronization signal of the second video signal, and an address switching circuit 7 for switching between a write address and a read address, and two signals are generated. A decoder 8 that generates a switching pulse from the read address, an AD converter 9 that converts the first video signal into digital data, a memory 10 that stores the digital data according to the write address, and a memory 1o. It is composed of a DA converter 11 that converts read digital data into an analog signal, and a video signal switching circuit 12 that switches between the analog signal and the second video signal and outputs it to an output terminal 13.

The operation of the video signal display device configured as described above will be described below. The first input from input terminal 1
The video signal is converted into digital data by an AD converter 9. A reset signal is generated by the reset signal generation circuit 14 from the synchronization signal separated from the first video signal to reset the write address. The write address is generated by the write address generation circuit 6, and the address switching circuit 7
It is switched and sent to memory 1o. Memory 1o
Then, the digital data that has been AD converted is stored in accordance with the hot address.

Data is read from the memory 10 according to a read address, which is generated by the read address generation circuit 6 as a read address based on the synchronization signal of the second video signal. The address switching circuit 7 switches the write address and the read address and supplies them to the memory 10, and writing and reading are performed according to the addresses. The read digital data is converted into an analog signal by the DA converter 11. The analog signal converted by the AD converter 11 and the second video signal from the input terminal 2 are connected to the video signal switching circuit 1.
2 to output from the output terminal 13. The control signal for switching the video signal is switched by the decoder 8 from the first signal to the second video signal at a predetermined fixed position.

Problems to be Solved by the Invention In such conventional video signal display devices, the display range of the first video signal and the display range of the second video signal are determined in advance, and the screen switching is performed in accordance with the display range of the first video signal and the second video signal. There is. Therefore, when the amount of data written in the first video signal decreases, the unwritten portion of the memory is read and then switched to the second video signal, resulting in a blank area being displayed on the screen. It had

The present invention solves the above problems, and even if a first video signal is written in an arbitrary size, a video signal display device automatically displays the first and second videos without any blank areas in response to the first video signal. The purpose is to provide

Means for Solving the Problems In order to solve the above problems, the present invention provides an AD converter that converts a first video signal into digital data;
A memory that stores the digital data, and a DA that restores the read data into an analog video signal.
a converter; a first synchronization signal separation circuit that separates a synchronization signal from the first video signal to obtain a first synchronization signal; a write address generation circuit that is reset by the first synchronization signal; a second synchronization signal separation circuit that separates a synchronization signal from the second video signal to obtain a second synchronization signal; and a reading height address generation circuit based on the second synchronization signal;
an address switching circuit that switches between the write address and the read address and supplies the memory to the memory;
a circuit that latches the write address immediately before being reset by the first synchronization signal; and an output terminal that switches between the analog video signal from the DA converter and the second video signal in response to a control signal. and a comparison/decoder circuit that compares the latched address and the read address to generate the control signal, and the control signal is determined when the read address is the write address. The video signal display device is configured such that the second video signal is output when the second video signal is equal to or exceeds .

According to the above-described configuration, the latch circuit stores the write end point of the first video signal, and the comparison/decoder circuit determines that the reading is more than the input and displays the second video signal. Switch to

Embodiment A video signal display device according to an embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing its configuration. In contrast to the conventional configuration shown in FIG. The embodiment shown in FIG. 1 is characterized in that the write address latched by the latch circuit 15 and the read address are compared and the comparison/decoder circuit 16 outputs a control signal. The latch circuit 15 latches and stores the address immediately before the write address is set, and the comparison/decoder circuit 16 compares the read address with the latch address and switches when the read address becomes larger than the latching address. It outputs a control signal.

The operation of the above configuration will be explained.

FIG. 2 shows the timing of each signal output in the above operation, and the symbols corresponding to the signals correspond to the symbols in FIG. 1. A first video signal input from input terminal 1 is input to a first synchronization signal separation circuit to obtain a first synchronization signal.

A reset signal generator 14 generates a reset signal from the first synchronization signal. By resetting the write address generated by the write address generation circuit 5 with the reset signal, a write address synchronized with the first video signal is obtained. Further, the first video signal is sent to an AD converter 9.
The data is input to the computer, converted into digital data, and stored according to the write address.

On the other hand, the second video signal input from input terminal 2 is
The second synchronizing signal is input to the synchronizing signal separation circuit of FIG. The read address generation circuit e is reset by the second synchronization signal to generate a read address, and obtains a read address synchronized with the second video signal. The write address and the read address are simultaneously supplied to the memory 10 while being switched by the address switching circuit A.
At 0, the digital data of the first video signal is written and read at the same time. The read digital data is converted into an analog video signal by a DA converter 11, and is outputted to an output terminal 13 via a video signal switching circuit 12.

At this time, the latch circuit 15 latches and stores the write address immediately before the write address is reset by the reset signal using the reset signal. The comparison/decoder circuit 1e constantly compares the read address with an address stored in a latch.

In the process of writing and reading ratio of memo 1J10,
When the read address matches or exceeds the latched write address, the comparison/decoder circuit 1
8 outputs a control signal to the video signal switching circuit 12.

Using the control signal, the video signal switching circuit 12 switches the analog video signal to the second video signal and outputs it to the output terminal 1.
Output to 3.

As described above, according to the video signal display device of the embodiment of the present invention, the latch circuit 15 is provided to latch and store the write AT/N immediately before reset, and compare the read comparison address with the latch address. By switching the video signal when the readout address exceeds the write address, switching to the second video is possible without displaying the readout image that exceeds the write range of the first video signal. The first and second video signals can be switched and displayed without any blank spaces in response to the first video signal written in an arbitrary range.

Note that when the waveform of the video signal is disturbed, the synchronization signal is also greatly disturbed, and the reset of the write address fluctuates. To deal with this, stable video signal switching can be achieved by averaging the latch addresses for comparison a predetermined number of times and comparing the addresses with the average value.

Effects of the Invention As described above, according to the present invention, a first video signal is digitally converted, and is written to a memory at a write address synchronized with the video signal, while being read out at a read address synchronized with a second video signal. , in a video signal display device that switches and outputs an analog video signal obtained by DA converting the read digital data and the second video signal, means for latching and storing a write address immediately before reset; The means for comparing the read address with its latch address and switching to the second video signal when the read address is equal to or higher than the write address automatically outputs the first video signal corresponding to the first video signal written in an arbitrary range. The first and second images can be displayed without any blank space.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a video signal display device according to an embodiment of the present invention, FIG. 2 is a timing waveform diagram of signal power of the video signal display device according to an embodiment of the present invention, and FIG. FIG. 1 is a block diagram showing the configuration of a conventional display device. DESCRIPTION OF SYMBOLS 1...First video signal input terminal, 2...Second video signal input terminal, 3...First synchronization signal separation circuit, 4...First 2 synchronous signal separation circuit, 6.
...Write address generation circuit, 6...
Read address generation circuit, 7... Address switching circuit, 9... AD converter, 1o...
...Memory, 11...DA converter, 12...
...Video signal switching circuit, 13...Output terminal, 14...Reset signal generation circuit, 15...
... Latch circuit, 16 ... Comparison/decoder circuit.

Claims (2)

[Claims] (1) A converting the first video signal into digital data
A D converter, a memory that stores the digital data, and a DA that restores the data read from the memory into an analog video signal.
a converter; a first synchronization signal separation circuit that separates a synchronization signal from the first video signal to obtain a first synchronization signal; a write address generation circuit that is reset by the first synchronization signal; a second synchronization signal separation circuit that separates a synchronization signal from a second video signal to obtain a second synchronization signal; a read address generation circuit that uses the second synchronization signal as a reference; an address switching circuit that switches the address and supplies the address to the memory; a circuit that latches the write address immediately before being reset by the first synchronization signal; and an analog video signal from the DA converter and the second video signal. a video signal switching circuit that switches the signal in response to a control signal and outputs the signal to an output terminal, and a comparison/decoder circuit that compares the latched address and the read address to generate the control signal, A video signal display device, wherein the control signal outputs the second video signal when the read address is equal to or exceeds the write address. (2) The video signal display device according to claim 1, wherein an average value is obtained from a plurality of address values of the latched read addresses, and the average value read address is supplied to a comparison/decoding circuit.