JP2564002B2 - Digital convergence correction device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital convergence correction device for a color television receiver.

2. Description of the Related Art FIG. 4 is a block diagram of a conventional digital convergence correction device.

In FIG. 4, (22) is a synchronizing signal input terminal,
The synchronization signal guided to the input terminal (22) is guided to a phase locked loop (hereinafter referred to as “PLL”) (16), and the PLL
The reference clock is output from (16). This reference clock is guided to the timing generation circuit (17) at the next stage,
For the crosshatch generation circuit (18), the x row and y column signals (x,
y is a natural number) and an address clock signal is output to the address generation circuit (8).

The crosshatch generation circuit (18) is arranged horizontally on the screen in the case of a direct-view tube color television receiver, or on the screen in the case of a projection type color television receiver, for example on the screen as shown in FIG. 9 in the direction and 7 in the vertical direction (9
Project the crosshatch (row 7 column). In this case, the convergence adjustment point is the cross hatch intersection.

The address generation circuit (8) generates a memory address signal for the one-frame memory (13), and the contents of the one-frame memory (13) are sequentially read out in synchronization with the synchronization signal, and D /
The analog signal is converted into an analog signal by the A conversion circuit (14), but since this analog signal waveform is stepwise, it is smoothed by a low pass filter (hereinafter referred to as "LPF") (15). After smoothing, although not shown, it is amplified by the drive stage and supplied to the convergence yoke.

The memory address signal is also input to the address matching circuit (7) and is compared with the adjustment point address signal output from the controller (1). The address matching circuit (7) writes the memory address signal when both address signals match. Output a write signal to 12).

Next, the convergence correction method will be described by exemplifying the case of a projection type color television receiver.

Convergence adjustment for matching the red, green, and blue electron beams in a color television receiver is divided into two types: a case where green is fixed and red is matched, and a case where green is matched with blue. First, select either green-red or green-blue combination with the color switch button (5) of the controller (1). For example, suppose you chose the green-red combination first, you would see a crosshatch of only green and red on the screen. Then, the mode switch button (4) is used to select either the cursor movement mode or the convergence adjustment mode for the cursor car (2). The cursor movement mode is a mode in which the cursor moves up, down, left, and right by the cursor key (2), and the convergence adjustment mode is a mode in which the convergence is corrected up, down, left, and right at the position where the cursor is, that is, the adjustment point. That is. Select the cursor movement mode with the mode switching button (4) and move the cursor to the point to be corrected with the cursor key (2).

After selecting the adjustment point in this way, the convergence adjustment mode is selected by the mode switching button (4) and the correction is performed. Depending on the level of the correction amount required,
In other words, when a large amount of correction is required, the correction amount ± A step (A> 1) circuit (9) is selected to roughly increase or decrease the correction amount by A (A> 1) to reduce the convergence deviation. When this happens, select the correction amount ± 1 step circuit (10) and finely adjust the correction amount by one.

These changes are made by the correction amount changeover switch (23) selecting the correction amount ± A step circuit (9) or the correction amount ± 1 step circuit (10) by the correction amount changeover button (23). The convergence correction amount is output to the writing circuit (12) when the adjustment point address signal derived from the controller (1) in the address matching circuit (7) and the memory address signal generated from the address generating circuit (8) match. The data is written in the 1-frame memory (13) at the timing of the write signal. The convergence correction information written in the 1-frame memory (13) is sequentially read out in synchronization with the sync signal, and is passed through the D / A conversion circuit (14) and LPF (15), which is not shown in the figure, but is driven. After being amplified in stages, it is supplied to a convergence yoke to perform a predetermined convergence correction.

In the same manner, correct the convergence for all adjustment points on the screen, then select another color (here, a combination of green and blue) with the color selection button (5) and similarly correct for all adjustment points on the screen. To do.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In the above-described conventional digital convergence correction apparatus, since the crosshatch has only a rough pattern as shown in FIG. 2, in order to adjust the convergence of the peripheral portion of the screen or the portion outside the screen, There was a problem that the information on the convergence deviation was insufficient and the information could not be adjusted accurately.

It is an object of the present invention to provide a digital convergence correction device that solves such a problem.

Means for Solving the Problems In order to achieve the above object, the present invention stores an arbitrary convergence correction amount in a digital memory, derives a convergence correction waveform based on the information stored in the digital memory, and performs the correction. A first pattern for displaying a coarse convergence correction pattern of x rows and y columns (x, y is a natural number) on a display screen in a digital convergence correction device that supplies a waveform to a convergence yoke and corrects the convergence. Generating means, x × m
Second pattern generating means for displaying dense convergence correction patterns in rows and y × n columns (m and n are both larger than 1 and xxm and y × n are natural numbers); And the second
The first digital switching means for selectively switching the pattern generating means, the second switching means for switching the convergence correction amount, and the interlocking switching control circuit for interlockingly switching the first and second switching means. The convergence correction amount stored in the memory is automatically A step (A> 1) when the first pattern generating means is selected.
Incrementing or decrementing each step, and automatically increasing or decreasing by the minimum step when the second pattern generating means is selected.

Therefore, when the coarse convergence correction pattern is selected by the interlocking switching control circuit, the level of the correction amount is increased to roughly correct the convergence deviation. When a large amount of information is required, such as when performing fine adjustments or adjustments outside the screen, selecting a dense convergence correction pattern by the switching means minimizes the level of the correction amount, resulting in highly accurate convergence deviation. Correction is performed.

Embodiment 1 FIG. 1 is a block diagram of an embodiment of the present invention, and portions corresponding to the conventional apparatus shown in FIG.

In FIG. 1, (22) is a synchronizing signal input terminal, and the synchronizing signal guided to the input terminal (22) is a PLL (16).
The reference clock is output from the PLL (16). This reference clock is input to the timing generation circuit (17) of the next stage, and an x row y column signal (x, y is a natural number) is supplied to the crosshatch generation circuit (31) and an address generation circuit (8). And outputs an address clock signal.
The crosshatch generation circuit (31) has a crosshatch coarse pattern generation circuit (32) and a crosshatch dense pattern generation circuit (33) inside. The timing generation circuit (17)
The x-row y-column signal output from the cross-hatch coarse pattern generation circuit (32) is directly input to the x-row y-column crosshatch, and the x-row y-column signal is cross-hatch dense pattern generation circuit (33). ), A crosshatch of x × m rows and y × n columns (m and n are both greater than 1 and x × m and y × n are natural numbers) is used for a direct-view tube color television receiver. Is displayed on the screen, and in the case of a projection color television receiver, is displayed on the screen. However, only one of them is displayed, and the switching is performed by the crosshatch switching button (3) of the controller (30) through the crosshatch / step interlocking switching control circuit (6) in conjunction with the switching of the correction to be described later. It is performed by the hatch changeover switch (34). For example, as a cross hatch rough pattern, 9 rows and 7 columns (x = 9, y = 7) in the screen as shown in FIG.
There is a cross hatch pattern of, and as a cross hatch dense pattern, in the screen as shown in FIG. 3 with m = n = 3.
There is a cross-hatch dense pattern with 27 rows and 21 columns. The convergence adjustment point is the intersection of the rough cross hatch patterns without changing the number of adjustment points in both the coarse cross hatch pattern of FIG. 2 and the fine cross hatch pattern of FIG. The address generation circuit (8) generates a memory address signal to the 1-frame memory (13) and outputs the 1-frame memory (1
The contents of 3) are sequentially read in synchronization with the synchronization signal and converted into an analog signal by the D / A conversion circuit (14). This analog signal waveform is a stepped LPF (low pass filter) ( Smoothed by 15). After smoothing, although not shown, it is amplified by the drive stage and supplied to the convergence yoke.

The memory address signal is also input to the address matching circuit (7) and is compared with the adjustment point address signal output from the controller (30). The address matching circuit (7) writes the memory address signal when both address signals match. Output a write signal to 12).

Next, the convergence correction method will be described by exemplifying the case of a projection type color television receiver.

Convergence adjustment for matching the colors of red, green and blue in a color television receiver can be divided into two ways, one for fixing red to green and the other for matching blue to green. First, select a combination of green-red or green-blue with the color switch button (5) of the controller (30).

If you choose the green-red combination first, only green is red and a crosshatch is projected on the screen. Then, the mode switch button (4) is used to select either the cursor movement mode (2) for the cursor key (2) or the convergence adjustment mode. The cursor movement mode is a mode in which the cursor moves up / down / left / right by the cursor key (2), and the convergence adjustment mode is a mode in which the convergence correction is performed up / down / left / right at the position where the cursor is, that is, at the adjustment point. That is.

Select the cursor movement mode with the mode switching button (4) and move the cursor to the point to be corrected with the cursor key (2).

After selecting the adjustment point in this way, the convergence adjustment mode is selected by the mode switching button (4) and the convergence is corrected. Here, either the rough pattern of FIG. 2 or the dense pattern of FIG. 3 is displayed as the crosshatch pattern, but when the correction amount of the adjustment point is large, the rough pattern is changed to the crosshatch switch button (3). Choose by. The signal from the crosshatch changeover button (3) is guided to the crosshatch / step interlocking changeover control circuit (6), and the control circuit (6) causes the crosshatch changeover switch (34).
Operates to select the crosshatch rough pattern from the crosshatch rough pattern generation circuit (32). In conjunction with this, the correction amount changeover switch (35) selects the correction amount ± A step circuit (9). When the crosshatch dense pattern is selected with the crosshatch switching button (3), the crosshatch dense pattern from the crosshatch dense pattern generation circuit (33) is selected with the crosshatch dense switch (34), and correction is performed in conjunction with this. The correction amount ± 1 step circuit (10) is selected by the amount selector switch (35). That is, the crosshatch / step interlocking switching control circuit (6) switches the ac of the crosshatch switching switch (34) and a'-c 'of the correction amount switching switch (35) by the signal of the crosshatch switching button (3). Select in conjunction with each other, or select bc of the cross hatch selector switch (34) and b'-c 'of the correction amount selector switch (35) in conjunction.

When the convergence adjustment mode is selected with the mode switching button (4), the crosshatch coarse pattern is first selected with the crosshatch switching button (3) as described above, and when the cursor key (2) is operated, the cursor key ( 2) A correction amount correction signal is output from the correction amount ± A step circuit (9) through the correction amount changeover switch (35), and the writing circuit (1
A correction signal of ± A step is introduced in 2). This correction signal is written when the adjustment point address signal derived from the cursor key (2) and the memory address signal from the address generation circuit (8) are detected to match in the address matching circuit (7). The signal is written in the 1-frame memory (13) through the write circuit (12) at the timing when the both address signals match.
Then, the contents of the 1-frame memory (13) are supplied to the convergence yoke (not shown) via the D / A conversion circuit (14) and the LPF (15) as described above, and red is converted to green in units of A steps. Convergence correction is performed.

In this way, after correcting the convergence of red and green at a predetermined adjustment point of the crosshatch rough pattern in coarse units of A step, the mode switch button (4) and cursor key (2) are pressed in the above-mentioned case. Perform the same operation as above for all the adjustment points of the cross-hatch coarse pattern to complete the convergence correction.

The crosshatch dense pattern is adjusted by selecting the crosshatch dense pattern with the crosshatch switching button (3). When a dense pattern is selected with the changeover button (3), the crosshatch interlocking changeover control circuit (6) switches the crosshatch changeover switch (34) and the correction amount changeover switch (35), and the crosshatch dense pattern generation circuit (33). A cross hatch dense pattern is derived and displayed on a display device (not shown), and a writing circuit (1
The correction signal of the minimum unit of the ± 1 step circuit (10) is guided to the 2) from the correction amount ± 1 step circuit (10) through the correction amount changeover switch (35), and each fine adjustment of 1 step unit is performed. The point is performed in the same manner as in the case of the cross hatch rough pattern described above.

As described above, the entire screen is roughly matched with the coarse pattern, and then the dense pattern is finely adjusted. Further, when the peripheral portion of the screen and the outside of the screen are matched, the coarse and dense crosshatch patterns are alternately used to easily and accurately adjust the convergence deviation.

If the convergence adjustment to match red with green is completed on the entire screen as described above, then operate the color switch button (5) to select the combination of green and blue. In the same manner as above, correction is performed so that blue is matched with green at all adjustment points of both the crosshatch coarse and dense patterns, and the entire convergence correction is completed.

Although the above-described embodiments have been described by exemplifying the projection type color television receiver, the same applies to the case of a direct-view tube color television receiver, and the embodiment is one in which convergence is adjusted by a cross hatch. However, it can be similarly implemented by using a dot pattern.

EFFECTS OF THE INVENTION According to the present invention, the interlocking switching control circuit automatically performs control so as to increase the correction amount in the coarse convergence correction pattern and minimize the correction amount in the dense convergence correction pattern. , If the amount of information needed to adjust the convergence is not so large, the amount of information needed to adjust the convergence is not large, and the amount of correction is set to a large value with a coarse convergence correction pattern to roughly adjust the convergence, and the amount of convergence is small. If you need a large amount of information to adjust the time or adjustment, you can adjust the convergence in a short time because the convergence amount can be adjusted finely with a dense convergence correction pattern. Moreover, the adjustment of the peripheral portion can be easily and accurately performed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 and FIG.
FIG. 4 is an operation explanatory diagram of the present invention, and FIG. 4 is a block diagram of a conventional example. (6) …… Cross hatch interlock switching control circuit, (9) …… Correction amount ± A step circuit, (10) …… Correction amount ± 1 step circuit, (13) …… 1 frame memory, (32) …… Crosshatch coarse pattern generator, (33) …… Crosshatch dense pattern generator.

Claims (1)

(57) [Claims] 1. An arbitrary convergence correction amount is stored in a digital memory, a convergence correction waveform is derived based on the information stored in the digital memory, and the correction waveform is supplied to a convergence yoke to perform convergence correction. In a digital convergence correction device, first pattern generating means for displaying a rough convergence correction pattern of x rows and y columns (x and y are natural numbers) on a display screen, and x × m rows and y × n columns Second pattern generating means for displaying dense convergence correction patterns (where m and n are both greater than 1 and x × m and y × n are both natural numbers); and the first and second pattern generation described above. First switching means for selectively switching the means, second switching means for switching the convergence correction amount, and interlocking switching for interlocking switching control of the first and second switching means. A control circuit, and automatically increases or decreases the convergence correction amount stored in the digital memory by A step (A> 1) in a state where the first pattern generating means is selected,
A digital convergence correction device characterized in that it automatically increases or decreases by the minimum step when the pattern generating means is selected.