JPS58101586A - Convergence correction circuit - Google Patents

Abstract

PURPOSE:To perform vertical interporation between splits easily, by splinting a screen into a plurality, to store an amount of correction in a memory, to obtain the amount of adjustment for other split from data of a representing adjusting point through calculation, in a convergence correction circuit for a color TV receiver. CONSTITUTION:A video signal is applied to a picture tube 7 via a switch 5, a horizontal and vertical synchronizing signal from a synchronizing separation circuit 8 is applied to a deflection coil 11 and a synchronizing signal from a synchronizing oscillator 12 is applied to a cursor generating circuit 15 and corresponding cross part is emphasized with a desired address from a microprocessor 16. In switching a switch 5 to the synthesis circuit 14, cross hatch picture dividing the screen into 16 equally is displayed, and one of the cross part out of 25 parts is selected as a representing adjusting point through the operation of a keyboard 23 to form the convergence correction mode, the data of correction is stored in a memory 24, the amount of correction of other cross parts is obtained through calculation from the data, a vertical difference is sequentially stored in the memory 24 to execute the vertical interpolation with addition.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a convergence correction circuit for a color television receiver, and particularly to a convergence correction circuit that uses a digital method 49 to perform highly accurate convergence correction over the entire screen, is easy to adjust, and has a simple configuration. It provides a circuit.

For example, in the case of a large TV receiver called a high-definition TV, the impurity accuracy is 0.1% relative to the screen size.
It is necessary to match within

However, in the case of a large-sized receiver such as the one described above, it is difficult, for example, to wind the deflection coil uniformly, and the magnetic field distribution is not symmetrical on the left, right, top, and bottom of the iii plane, but varies.

Therefore, even if convergence correction using conventional horizontal period, -direct period parabola, and sawtooth waveforms is performed, 11
It is not possible to match the weight of the entire 1w.

Therefore, the screen is divided into multiple parts, and in each division:
It has been proposed that the amount of convergence correction is stored in a memory, read out from the memory in response to electron beam scanning, and supplied to a convergence correction means to perform convergence correction for the entire screen.

However, in this case, in order to increase the accuracy of convergence, it is better to have a large number of divisions. However, when the number of divisions is increased, the :1y parsenne of each division is adjusted [the number of adjustments for memorization is reduced]. For example, many adjustment steps in the production line are required, which is undesirable.

On the other hand, [set a predetermined substitute adjustment point smaller than the division, adjust the damper at this point, calculate the adjustment amount for other divisions from this adjustment data, and store the memory in row 5. However, in conventional devices of this kind, the circuit for calculation is complicated, and the pre-adjustment is performed by calculation, so that accurate correction is not necessarily performed.

In view of the above five points, the present invention has a simple configuration, allows for easy and accurate storage of comperance correction amounts, and
Furthermore, vertical interpolation between divisions can be easily performed. An embodiment of the present invention will be described below with reference to the drawings.

At the 11th O, the signal from the antenna (1) is chased (2), is supplied to the video detection signal link (4)K through the video intermediate frequency circuit (3), and the detected video signal is sent to the switch (
5). A signal from this switch (5) is supplied to a picture tube (7) through a video output circuit (6).

In addition, the signal from the switch (5) is transmitted to the synchronous separation circuit (8) K.
The supplied and separated horizontal and vertical synchronizing signals are supplied to the deflection coil Qυ through the output circuit (9) and aQ, respectively.

Further, a signal from a synchronous oscillator n that forms a horizontal-vertical synchronizing signal is supplied to a crosshatch video signal forming circuit 0, thereby forming a crosshatch video signal of, for example, ls in the vertical and horizontal directions. This video signal is supplied to the switch (5) through the synthesis circuit I.

Also, the synchronization signal from the oscillator a is supplied to the cursor generation circuit (c), and! The desired address from the output circuit αe is the generation circuit α! 19. This generation circuit a! The signal from 9 is applied to a synthesis circuit a4 to modify and emphasize the desired cross section 1, as shown in FIG. 2, for example.

Furthermore, any data signals from the Pousetsner ae are supplied to the multiplexer a8 via the register IA7). Further, a signal corresponding to the above-mentioned scanning period of the desired cross portion from the cursor generation path 4 is supplied to the multiplexer, and the signal from the register aη is taken out at this point 11I. 20gI4# is supplied to the pumperence correction signal Ik(2) through the DA conversion circuit 14-pass filter (2) and the amplifier QD.

Furthermore, the signal from the keyboard (2) is
The data signal supplied to IIK and supplied to the above-mentioned register storage η is modified. This adjusts the convergence correction amount and measures the correct humperance correction amount.

Furthermore, the data signal of processor t-aQ is memorized (2)
The address supplied to the data input terminal of
When supplied to the write address terminal of K.

A write/read control signal from the Proryu Tuna-aS is supplied to the control terminal of the memo V (c).

In addition, horizontal and vertical synchronization signals from the synchronization separation circuit (8) are supplied to an address forming circuit (c) K to form addresses corresponding to horizontal and vertical scanning positions. The second address is applied to the read address terminal of the memory (2).

Then, the data signal read from the memory (2) is supplied to the multiplexer ring through the direct supplementary link (to).

In this device, the switch (5) is connected to the synthetic circuit a shown in the figure.
When switching to 4-Confucian mode, the screen of the joy tube (7) displays, for example, a crosshatch image that divides the screen into 16 groups vertically and horizontally as shown in FIG.

Further, the key ``-'' is configured as shown in FIG. 4, for example.

If the automatic (AUTO) operation button 6M) is pressed here,
The 2i cross portions surrounded by broken lines in FIG. 3 are selected as representative adjustment points, and the cross portion surrounded by broken lines in the upper left corner is displayed first as shown in FIG.

In this state, when the R/B operation button (2) or the R/G operation button (To) is pressed, the red and blue or red and edge color are respectively set as the red and blue or red and edged intensity correction screens. Further, by pressing the upper and lower operation buttons W or the left and right operation buttons -1 (B), the red and blue or red and green =/parsence correction amount is increased or decreased by a predetermined amount. When the end (END) operation button is pressed at the time when the L''c:1 invergence correction is completed, the data of the y-space correction amount is stored as a memo in the converter.

Further, by operating the operation button (To), the address of the next representative adjustment point is output. In this way, representative 1 of 2s places
111I The convergence at one point is corrected, and the data of the amount of correction at each point is stored in the memory.

The correction amounts for the remaining 231 cross portions are calculated from these stored data. Here, as a method of calculation, for example, as shown in No. 511, a quadratic or quartic interpolation formula that becomes 11'' at any representative adjustment point and 0' K at the adjacent 1IIIl adjustment point becomes 111-. It is set in the Tsusa Kan, and the numerical value according to this interpolation formula is added to the 2 in between.
A point correction amount is calculated.

This calculation is performed horizontally and vertically to calculate the correction amounts for the remaining 231 cross sections. In addition, Fig. 3 00.1, 1
The data in the 59th row and column are calculated from the data in the 2.3rd or 13.14th row and column, respectively, by linear approximation or the like.

These data are stored in the mail.

Furthermore, these data I are read out from the memory and the compliance is corrected. And in this state 2
Manual adjustment is performed for cross portions with poor intensity correction. In other words, in the irises 4 figure [Manual (M
When the operating button υ of ANUAL) is pressed, the device is put into manual mode. When the upper and lower operation buttons, 1 or 1 (c) are pressed, the address output from the above-mentioned pusher is increased or decreased by 1 in the vertical and horizontal directions. As a result, the adjusted E1 section is moved up and down, left and right, and the convergence correction is performed using the operation buttons 0 and 1 for the desired E1 section.

A correction amount of 1 percent is made at a desired portion below this k.

Furthermore, the memory that can be placed in the middle of the day is the oiIth (the best)
The numeric value of the measured point is stored in the row, and the vertical difference value is stored in each of the following rows. By performing such storage, the vertical interpolation circuit (to) is configured as follows.

In l1euvA, addresses in the vertical direction (ri) and horizontal direction (h) are supplied to the memory 94, and the above-mentioned stored data is sequentially read out.The data signal from this memory is sent to the divider circuit. - and is divided by the number of horizontal scans between adjacent cross sections.If this number of horizontal scan lines is, for example, 16, then the division is performed by shifting the data down 4 bits. Furthermore, the shifted data signal is supplied through the adder circuit to a register that stores data for the horizontal period CH1, and the register is driven by the above-mentioned horizontal address input tie selection. The supplied data signals are sequentially transferred. The signals taken out from this register are sequentially latched by a latch circuit. This latched signal is supplied to the multiplexer shaft and also to the adder circuit.

[In this circuit], in contrast to the 5 straight shift circuit as shown in Figure 7, the division (shift) circuit has a rear signal as shown in Figure 7B and a division as shown in the 7th WAC. (shift) abort signal is provided. That is, the division circuit 6 is cleared outside the effective screen in the latter half of the vertical period, and the data (true numerical value) of the row of one predetermined horizontal period KOII in which the shift within the planning period is stopped is taken out. Here, the data signal is composed of, for example, 8 bits, and the division circuit 6υ is composed of 4 bits below the decimal point and 8 bits above the decimal point, a total of 12 bits.

Therefore, during the shift stop period, the K signal (8 bits above the decimal point) is output, and the 4 bits below the decimal point are all set to 0, and during the shift period, the 4 bits below the decimal point and the /JS
A signal is output to the 4 bits below a few points, and a positive or negative sign is output to the upper 4 bits.

Furthermore, the addition H road wheel is composed of 4 bits below the decimal point and 8 bits above the decimal point, a total of 12 bits.

Here, the signal from the above-mentioned divider circuit 61) and the signal delayed by one horizontal period in relation to the register are added. Therefore, in the 0th line, for example, if data of AO is supplied,
The division circuit f1υ outputs A. Then, when (At-AO) is supplied in the first row, the A1-A division circuit 61) outputs 16, and the addition circuit - The output of is A1-A・””16. When this addition is performed 16 times, the output of adder circuit 3 becomes AtK, and the data of each horizontal scanning line is sequentially extracted by linear interpolation. Furthermore, in the horizontal scanning lines from 1s11th onwards, extrapolation by linear approximation is automatically performed by continuing to add 8 of the tsIIth data.

Then, by supplying the rear signal as shown in the 7th WADK to the latch circuit (b), the latch circuit - to -1
For example, a signal as shown in FIG. 7E is output. In step 5, superposition interpolation is performed.

Note that horizontal interpolation is performed by a low-pass filter (2).

This is how the convergence correction force is performed.According to the present invention, it is only necessary to adjust the 25 substitute IIIM1 points and further adjust only the defective points, making the adjustment extremely easy and Since it is possible to individually adjust defective points, extremely accurate adjustments can be made to all points.

Further, as described above, by using the difference data in the vertical direction stored in the memory, the vertical interpolation circuit can be constructed from an adding circuit, which greatly simplifies the circuit construction.

Note that normal convergence correction is performed only in the circuit on the right side of the memory (2). Therefore, oscillator 04 ~ register a
1 and the circuit surrounded by the broken line of the keyboard (c) may be separated via an arbitrary boat, and these circuits may be inserted into the boat only at the time of adjustment to perform adjustment.

Further, the number of screen divisions and the number of representative adjustment points described above are not limited to the above numerical values. However, calculations and the like can be more advantageously performed if the number of representative adjustment points is odd in both the horizontal and vertical directions and arranged symmetrically with respect to the center line.

Further, the number of horizontal scanning lines between the cross sections is not limited to 16 as described above, but in this case as well, the number of scanning lines is 2°KL? By setting K to 3°, division can be performed by shifting n bits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of the present invention, FIG. 5 is a diagram for explaining the same, FIG. It is a figure for explanation. ae is microprocessor - 1 (2) is memory, (to)
is a vertical interpolator.

Claims (1)

[Claims] A convergence correction means that divides the display surface of the picture tube into a plurality of parts, stores the amount of intensification correction in each division in a memory, and calculates the above-mentioned image in accordance with the scanning of the electron beam. In the 5K Zumperins correction tunnel that supplies convergence correction for one screen mass, set fewer representative adjustment points than the number of divisions above, adjust the convergence of these points, and calculate based on these adjustment data. (a means for calculating data on the number of divisions and storing it in the memory; and a means for correcting the memory of the memory by further adjusting the divisions for which correction has not been completed using these calculated data); In addition, the memory contents of the above-mentioned message 49 are such that the above-mentioned data is directly stored in the top row;
A convergence correction circuit that stores difference data between rows in each of the following rows and performs vertical correction.