JPH0434629Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a convergence correction pattern generation circuit that is displayed on a CRT display screen during digital convergence adjustment.

[Technical background of the invention]

Receivers with high resolution, such as high-definition monitors and high-definition VTs, often use convergence devices to reduce color shift on the screen.

As shown in FIG. 1, the convergence device includes a correction waveform generation circuit 1 that generates a correction waveform 2 necessary for correction, and an output circuit 3 that supplies a current 4 having substantially the same shape as the correction waveform 2 to a convergence yoke 5. As shown in FIG. 2, the correction waveform generation circuit 1 stores in a memory the correction amounts necessary for convergence correction at several tens to hundreds of correction points 7 provided inside and outside the screen 6, and calculates and processes the correction amounts using a low-pass filter. Perform interpolation and other processing to create the necessary correction waveform.

In other words, the convergence correction is performed by changing the correction amount so as to eliminate the convergence error at the correction point 7 described above, thereby almost eliminating color shift at the correction point 7 in the CRT screen 6. At this time, convergence correction in areas other than correction point 7 is automatically performed based on the correction amount at correction point 7 by linear interpolation in the vertical direction and by interpolation in the horizontal direction by a low-pass filter. Thus, convergence correction over the entire screen 6 is accomplished. Note that the correction point 7 can be set as a dot pattern as shown in FIG.
As shown in the figure, the points are displayed on the screen 6 as intersection points of the crosshatch pattern 8.

Next, a circuit for generating a correction pattern indicating the above-mentioned correction point 7 will be explained. As an example, a generating circuit for the crosshatch pattern 8 shown in FIG. 4 is shown in FIG. For the explanation, the frequency of clock 10 used for digital convergence is 384H.
(H; horizontal scanning frequency), and the number of correction points in the horizontal direction is 16 points. Therefore, the interval between correction points 7 is 24
Every clock. In addition, correction point 7 is added in the vertical direction.
It shall be provided every 48 lines.

A synchronization separation circuit 11 to which the television synchronization signal 12 is supplied outputs a V synchronization pulse 14 and an H synchronization pulse 16 synchronized with the vertical V and horizontal H synchronization pulses, respectively. The V synchronization pulse 14 is supplied to a vertical frequency division counter 13 and a vertical address counter 15. Further, the H synchronization pulse 16 is supplied to the vertical frequency division counter 13, PLL 17, horizontal frequency division counter 19, and horizontal address counter 21, respectively.

The PLL 17 generates the clock 10 and supplies it to the horizontal frequency division counter 19. The frequency division counter 19 is a 24-digit counter prepared according to the above-mentioned conditions, and the counter output 18 is the pattern generator 5
The divided output (frequency 16H) 20 is guided to the horizontal address counter 21. The counter output 18
indicates the scanning location between correction points in the horizontal direction. Further, the horizontal address counter 21 outputs a horizontal correction point address 22 indicating the number of the correction point corresponding to the scanning position in the horizontal direction.

On the other hand, the vertical frequency division counter 13 is a 48 frequency division counter, its count output 24 is led to the second NOR gate 25 in the pattern generation section 50, and the frequency division output 26 is led to the vertical address counter 15. be guided. The vertical correction point address 26 output from the vertical address counter 15 indicates the number of the correction point in the vertical direction.

Now, NOR gate 2 in the pattern generation section 50
The outputs of 3 and 25 are led to an OR gate 27.
The NOR gates 23 and 25 become "1" only when each bit of the count outputs 18 and 24 input to both are "0". Therefore, the output 28 of the NOR gate 23 corresponds to the vertical line of the crosshatch pattern 8 shown in FIG.
corresponds to a horizontal line. Therefore, the output signal of the OR gate 27 converts the cross hatch pattern into the CRT3.
This is a pattern signal 32 for displaying on the screen 5. The video signal switching circuit 33 to which this pattern signal 32 is supplied has, for example, each RGB color signal 3.
4, change the pattern output signal 36 to CRT35
The crosshatch pattern 8 is displayed on the display screen of the CRT 35.

[Problems with background technology]

According to the conventional method described above, convergence correction can be performed relatively easily, but the correction waveform created by linear interpolation calculation or interpolation using a low-pass filter will have some errors from the correct correction waveform. That is, R,G
Taking the two colors as an example, if the R and G crosshatch patterns are shown by solid lines and broken lines, respectively, color shift occurs in the direction of the arrow outside the correction point as shown in FIG.

Further, since the pattern cannot be seen at the correction points outside the screen 6, the color shift cannot be directly adjusted. For this reason, even if the correction amount is calculated from the correction amount at the correction point within the screen 6, an error occurs between the correction amount and the actually required correction amount, and it is not possible to obtain convergence accuracy at the periphery of the screen.

[Purpose of invention]

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a convergence correction pattern generation circuit that is used when performing convergence adjustment and can improve convergence correction accuracy.

[Summary of the idea]

The pattern generation circuit according to the present invention is capable of projecting not only the basic crosshatch pattern that connects correction points, but also the crosshatch patterns that are interposed vertically and horizontally between correction points. The correction amount for off-screen correction points can be given so as to disperse the convergence error between the images and to reduce the convergence error in the periphery of the screen.

[Example of idea]

Hereinafter, a pattern generation circuit according to the present invention will be explained using the drawings. According to the pattern generation circuit according to the present invention, it is possible not only to connect the correction points 7 but also to display a crosshatch pattern interposed between corrections. In the description, a case will be exemplified in which a crosshatch pattern is displayed in which five lines are added between each correction point in the horizontal and vertical directions.

To satisfy the above conditions, with the same settings as before, horizontally every 4 (=2 ² ) clocks,
Further, in the vertical direction, a pattern may be provided every 8 (=2 ³ ) lines. A pattern generating section 60 that realizes this is shown in FIG.

The pattern generating section 60 corresponds to the conventional pattern generating section 50 shown in FIG. The pattern generating section 60 is composed of NOR gates 61 to 64, OR gates 65 to 66, inverters 67 and 68, and a switch 69.

The NOR gate 61 receives the lower two bits 184 of the count output 18 supplied from the horizontal frequency division counter 19,
185 is input, and the other upper bits 181 to 183 are input to the NOR gate 62 together with the output of the NOR gate 61 inverted by the inverter 67. In addition, the lower 3 bits 244 to 246 of the count output 24 supplied by the vertical frequency division counter 13
is sent to NOR gate 63, and other upper bits 241~
243 connects the output of the NOR gate 63 to the inverter 6
It is input to the NOR gate 64 along with the inverted version by 8. Furthermore, the NOR gate 61,
The output of 63 is sent to OR gate 65, and NOR gate 6
The outputs of 2 and 64 are led to an OR gate 66, and the outputs of both OR gates 65 and 66 are led to a switch 6.
9 and output as a pattern signal 32.

According to the above configuration, the output of the NOR gate 61 becomes "1" when the count output value of the horizontal frequency division counter 19 is divisible by 4, and the output of the NOR gate 61 becomes "1".
The output becomes "1" when the count output value of the vertical frequency division counter 13 is divisible by 8. Then,
Since the interval between the correction points of the basic crosshatch pattern 8 shown in FIG. 4 is 24 clocks in the horizontal direction and 48 lines in the vertical direction, the pattern signal 32a output from the OR gate 65 is The pattern signal is a crosshatch pattern with five lines added in each of the horizontal and vertical directions.

In the embodiment, since the pattern signal 32b output from the OR gate 66 is a pattern signal that displays the conventional basic crosshatch pattern 8, the switch 69 displays the basic pattern 8 and the crosshatch pattern according to the present invention. It is possible to select according to the following.

Next, convergence correction performed using the crosshatch pattern generated by the convergence correction pattern generation circuit according to the present invention will be explained.

FIG. 8 corresponds to the above-mentioned FIG. 7, and shows the projected state of the crosshatch pattern 9 according to the present invention when convergence correction is performed so that there is no color shift at the correction point 7. As can be seen at a glance in FIG. 8, according to pattern 9 according to the present invention, it is possible to grasp the R and G color deviations on the entire screen outside the correction point 7. Therefore, by adjusting the convergence in the correction point 7 to shift as shown in FIG. 9, it is possible to disperse the convergence shift between the correction points and reduce the maximum error in convergence.

Furthermore, in the peripheral area of the screen, there is no need for convergence to match at off-screen correction points. Therefore, by using the pattern according to the present invention, when the correction amount of the correction point 10 outside the screen is changed as shown in FIG. It can be adjusted to minimize the convergence error at the periphery of the screen.

Note that the number of patterns interposed vertically and horizontally between correction points is five in the above-described embodiment, but even if this number is increased or decreased somewhat, the effect on convergence adjustment is hardly impaired. However, if only one pattern is added in both the horizontal and vertical directions between the correction points, the added pattern may become invisible at the periphery of the screen during overscanning or during the adjustment stage, and in effect, the pattern added at the periphery of the screen may become invisible. , the effect of adding the pattern may be lost. Further, convergence correction between correction points in the horizontal direction is usually performed by interpolation using a low-pass filter, but in this case, the change in the correction waveform is larger near the correction points than between the correction points. Therefore, in order to fully grasp the state in which the convergence error between correction points is minimized, at least two additional patterns are required between correction points in the horizontal direction. Therefore, in order to obtain a sufficient effect, it is desirable that two or more patterns be interposed vertically and horizontally between the correction points. Note that the pattern intervals between correction points do not need to be equal intervals.

[Effect of idea]

As explained above, by using the pattern projected by the convergence correction pattern generation circuit according to this invention, it is possible to sufficiently grasp the convergence deviation outside the correction point, and by dispersing it. Correction that reduces the maximum convergence error becomes possible. As a result, appropriate convergence correction can be performed and a good image with little color shift can be obtained.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the convergence circuit. Figure 2 is a schematic diagram showing the positions of correction points inside and outside the screen. Figure 3 is a dot pattern diagram showing the correction points within the screen. Figure 4 is a diagram showing the correction points within the screen. 5 is a block diagram showing a conventional crosshatch pattern generation circuit, FIG. 6 is a block diagram of a pattern generation section according to the present invention, and FIGS. 7 to 10 explain convergence correction. It is a crosshatch pattern diagram for. 6...screen, 7,10...correction point, 9...crosshatch pattern, 60...pattern generation section.

Claims (1)

[Claims for Utility Model Registration] When performing convergence correction through correction of convergence deviation at a plurality of correction points set in the horizontal and vertical directions inside and outside the screen of a television receiver, a screen is used to clearly indicate the position of the correction point. In the convergence correction pattern generation circuit that generates the pattern projected above, selectively generates a crosshatch pattern in which at least two or more lines are interposed in the horizontal and vertical directions between the correction points and a pattern indicating the correction points. A pattern generation circuit for convergence correction, characterized in that a pattern generation circuit generates convergence.