KR0186148B1 - Digital convergence compensation apparatus - Google Patents

Abstract

The present invention relates to a digital convergence correction device, comprising: a microcomputer for generating address data and convergence correction data according to a convergence correction input signal generated by an input signal generator, and the above-mentioned generated by the microcomputer. An address generator for generating a memory address and a control signal according to the control data VRST and RD of the address data and the synchronization unit, a phase detector and a voltage adjusting oscillator for generating an internal reference clock and a horizontal synchronization signal, and a synchronization signal (DVS) A synchronization unit for generating (DHS) (RD), a pattern generation unit for generating a convergence adjustment grid pattern signal according to the synchronization signal (DVS) (DHS), a grid pattern signal for this pattern generation unit, and an external video signal An adder for synthesizing the video signal for adjustment, and receiving the convergence correction data from the memory and the synchronization signal of the synchronization unit, and outputting the convergence correction data. A digital / analog for converting the convergence correction data of the convergence correction data path section, the data path control section, and the convergence correction data path section into an analog signal and outputting a correction current of the convergence adjustment yoke. It is composed of a transducer and is suitable to be configured as a custom semiconductor.

Description

Digital Convergence Compensator

1 is a block diagram of a digital convergence correction device of the present invention.

2 is a grid pattern display diagram of an actual screen area in the present invention.

3 is an X-Y graph for explaining linear interpolation in the present invention.

* Explanation of symbols for main parts of the drawings

10: input signal generator 20: microcomputer

30: RAM 40: address generator

50: data path control unit 60: convergence correction data path unit

70: digital / analog converter 80: yoke for convergence adjustment

90: synchronization unit 100: phase detector

110: voltage controlled oscillator 120: pattern generator

130: an adder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a convergence correction device of a large high definition display device of a raster scan type, and more particularly, to a digital convergence correction device suitable for forming a custom semiconductor.

Recently, preference for display devices such as TVs with large screens has increased. The requirements for such a display device are brightness, large viewing angel, fine image quality, and low geometrical distortion.

The reason for the deformation of the shape is because the geometric positions of the electron guns of the red, green, and blue electron guns of the display apparatus are different from each other.

In order to solve such shape deformation, convergence correction is generally performed, and in conventional analogue convergence correction, many parameters are manually adjusted by experience, and the time required for this adjustment during mass production is long. There is a lot of cost, and not only can not be uniformly adjusted over the entire screen, there was a problem that is not suitable for large screen.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and an object of the present invention is to provide a digital convergence correction device suitable for forming a custom semiconductor.

The digital convergence correction device according to the above object includes an input signal generator for generating a convergence correction input signal and an address corresponding to each correction position according to the convergence correction input signal generated by the input signal generator. A microcomputer for generating data and convergence correction data at the correction position thereof, a memory for storing the convergence correction data generated at the microcomputer, the address data generated at the microcomputer, and a synchronization unit; An address generator for generating a RAM address and a control signal according to the control signals VRST and RD, a phase detector and a voltage adjusting oscillator for generating an internal reference clock and an internal horizontal synchronization signal from a horizontal synchronization signal in an external video signal, Generates a synchronization signal DVS (DHS) (RD) according to an internal reference clock and an internal horizontal synchronization signal and a vertical synchronization signal among the external video signals. And a pattern generator for synchronizing the grid pattern signal for adjusting convergence with the external video signal according to the synchronization signal DVS (DHS) of the synchronization unit, and for displaying the grid pattern on the screen. An adder for synthesizing the grid pattern signal of the pattern generator with an external video signal to generate an adjustment video signal, and a display time of a corresponding adjustment point by receiving the convergence correction data from the memory and the synchronization signal RD of the synchronizer; A convergence correction data path section for outputting convergence correction data for the horizontal and vertical directions of the ALG ratio signal in synchronism with the control unit, and the convergence correction data path section and memory or data between the memory and the microcomputer. A data path control unit for controlling the transfer direction and the convergence correction data of the convergence correction data path unit as analog signals; It is composed of a digital / analogue converter which converts and outputs a correction current of the yoke for convergence adjustment.

The address generator, data path control unit, synchronizer, phase detector, convergence correction data path unit, and pattern generator are composed of one chip.

In the digital convergence correction device of the present invention, as shown in FIG. 2 in the adjustment mode, 1) an adjustment point display grid pattern B consisting of vertical and horizontal lines is formed on an actual screen area A of the display device. By dividing the actual screen area A into several small blocks (24 small blocks in FIG. 2), (2), convergence correction is independently performed on each of these small blocks.

In particular, in the convergence correction, the edge of each small block (the intersection of the horizontal line and the vertical line) is used as a basic correction point, and the correction between two adjacent correction points is performed through linear interpolation.

An example of this linear interpolation (linear interpolation in the vertical direction) is as follows.

At two adjustment points (X, YO) and (X, Yn) as shown in the XY graph in Fig. 3, Yn should be corrected to Y'n directly below, and YO should be corrected to Y'O directly below, respectively. In this case, subtract YO from Y'O to find a, subtract Yn from Y'n to find b, and then obtain Yi as shown in Equation (1) below to perform linear interpolation.

I = 0,1,2, ..., n

Then, ③ calibrate independently for each color component (R, G, B), and repeat convergence correction by repeating ① and ② above.

Now, the configuration of the present invention digital convergence correction apparatus of FIG. 1 will be described in detail.

In this way, the grid pattern is generated and the grid pattern is displayed on the actual screen area. Then, convergence correction current is generated and input to the convergence correction yoke as follows.

Such a digital convergence correction device of the present invention has a high convergence adjustment speed, which can reduce production cost and is suitable for construction of an on-demand semiconductor (ASIC).

1 illustrates an embodiment of the present invention digital convergence correction device.

In order to generate the convergence correction data, the input signal generator of reference numeral '10', which is constituted by a remote controller or a key panel, is used for the convergence correction input signal at each adjustment point (see FIG. 2 above). IN) and input it to the microcomputer 20.

The microcomputer 20 outputs the address data uA corresponding to each correction position and the convergence correction data uD at the correction position in accordance with the received convergence correction input signal IN. The address data uA is input to the address generator 40.

The address generator 40 generates a RAM address (MA: Memory Address) and a write control signal according to the received RAM address data uA.

In this embodiment, the memory is a RAM 30, and the convergence correction data output from the microcomputer 20 is stored in the address MA of the RAM 30 where the address generator 40 is generated. do. The data transfer direction between the RAM 30 and the microcomputer 20 is controlled by the data path controller 50.

This completes the creation of the convergence correction data.

On the other hand, in order to display the grid pattern B, which is a horizontal line and a vertical line, as shown in FIG. 2 on the actual screen area A of the display device, the phase detector 100 is a voltage controlled oscillator (VCO). The oscillator 110 is controlled to generate an internal reference clock VCLK and an internal horizontal synchronizer signal IHS from the horizontal sync signal HS in the external image signal, and input the same to the synchronizer 90.

In this synchronization unit 90, two synchronization signals DVS (DHS) which are control signals according to the received internal reference clock VCLK, the internal horizontal synchronization signal IHS, and the vertical synchronization signal VS among the external video signals. ) Is generated and input to the pattern generator 120, generates a vertical reset signal (VRST: Vertical ReSeT) and inputs to the address generator 40, and generates a synchronization signal (RD) to generate a convergence correction data path. Input to the unit 60.

The pattern generator 120 is generated by synchronizing the grid pattern signal GP for convergence to the external image signal according to the two synchronization signals DVS (DHS) received from the synchronization unit 90, and adding the same to the external image signal. 130).

The adder 130 synthesizes the input grid pattern signal GP and the external video signal VIN to generate a video signal VOUT for adjustment, and inputs the same to the video signal amplifier (not shown). A grid pattern B consisting of vertical lines and horizontal lines is displayed on the actual screen area A. FIG.

Finally, in order to perform the convergence correction, the digital convergence correction apparatus of the present invention should generate a correction current of the convergence correction yoke CY as indicated by reference numeral '80' in FIG. To this end, the address generator 40 first generates an address MA while increasing from zero according to the vertical reset signal VRST received from the synchronizer 90.

In the data path controller 50, the convergence correction data DI is used as the correction data (MD: Memory Data) in the address MA of the RAM 30 generated by the address generator 40. Input to the correction data path unit 60.

The convergence correction data path unit 60 corresponds to the convergence correction data DI received from the data path control unit 50 and the synchronization signal RD previously inputted from the synchronization unit 90. By synchronizing the display time of the control points, the convergence correction data (CDbv, CDbh, CDgv, CDgh, CDrv, CDrh) (digital data) of the algi ratio (R, G, B) signals of each control point are generated simultaneously. To the analog converter (DAC) 70.

Here, the convergence correction data CDrh is a horizontal convergence correction data for red (R), and the convergence correction data CDrv is a vertical convergence correction data for red (R). The convergence correction data CDgh is the horizontal convergence correction data for green (G), and the convergence correction data (CDgv) is the vertical convergence correction data for green (G). The convergence correction data CDbh is a horizontal convergence correction data for blue (B), and the convergence correction data CDbv is a vertical convergence correction data for blue (B).

The digital / analog converter 70 converts the received digital data into an analog signal to generate a correction current of the convergence adjusting yoke 80 and inputs it to the convergence adjusting yoke 80, thereby converting it. Correction is performed.

As described in detail above, the digital convergence correction device of the present invention is preferably applicable for the convergence correction of a large-scale high-definition display device, and the microcomputer can generate the RAM at any time by the address generator and the data path controller. The data can be read and written, so the convergence adjustment speed is high, which reduces the production cost, and has the effect of being suitable for custom semiconductors.

Claims (1)

An input signal generator which generates an input signal for convergence correction, and address data corresponding to each correction position and convergence correction data at the correction position according to the convergence correction input signal generated by the input signal generator. A memory for storing the convergence correction data generated by the microcomputer, the address data generated by the microcomputer, and a control signal (VRST, RD) of the synchronizer. And an address generator for generating a control signal, a phase detector and a voltage adjusting oscillator for generating an internal reference clock and an internal horizontal synchronizing signal from a horizontal synchronizing signal in an external image signal, the internal reference clock and an internal horizontal synchronizing signal, and the external image. A synchronization unit for generating a synchronization signal DVS (DHS) RD in accordance with the vertical synchronization signal in the signal; and a synchronization signal DVS (DH) for this synchronization unit. According to S), the pattern generation unit generated by synchronizing the convergence adjustment grid pattern signal with the external video signal, and the grid pattern signal and the external video signal of the pattern generation unit for displaying the grid pattern on the screen are synthesized. An adder for generating a video signal for adjustment, a convergence correction data from the memory and a synchronization signal RD of the synchronization unit, and synchronizing with the display time of the corresponding adjustment point in synchronization with the horizontal and vertical directions of the A convergence correction data path section for outputting convergence correction data, a data path control section for controlling a data transfer direction between the convergence correction data path section and a memory or the memory and the microcomputer, and the convergence Correction of convergence adjustment yoke by converting the convergence correction data of the correction data path portion into an analog signal Since digital cone's correction device, characterized in that consisting of a digital / analog converter to obtain an output stream.