JPH11252577A - Convergence correcting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep the waveform of a convergence correcting current to be constant by simple constitution even in a case when the scanning frequency of a video signal is switched by detecting the horizontal synchronizing signal of an input signal so as to control the amplitude of voltage to apply to a convergence correcting coil according to the frequency. SOLUTION: The horizontal synchronizing signal of the input signal is detected so as to control the amplitude of voltage to apply to the convergence correcting coil according to the frequency. In this device, a frequency detecting circuit 6 detects the frequency of the horizontal synchronizing signal 14 and converts it to voltage to output. A voltage amplifying circuit 7 amplifies a stepwise analog voltage according to a voltage outputted from the circuit 6 and outputs a stepwise analog corrected voltage. An output circuit 8 converts the stepwise analog corrected voltage to a current to output to the convergence correcting coil 9, which corrects the convergence of a video signal to display on a screen by the corrected current outputted from the circuit 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a convergence correction device used for an image display device such as a color television receiver or a display terminal using a CRT (cathode ray tube). The present invention relates to a convergence correction device suitable for a multi-scan image display device that can be handled by the same device even when the frequency is switched.

[0002]

2. Description of the Related Art Conventional CRT color display devices include a direct-view tube type display device and a three-tube video projector. In the former, three primary colors of light are combined on the surface of a cathode ray tube to create a color image. In the latter,
Light from three cathode ray tubes is combined on a screen through color filters to create an image. In any case, in order to obtain a high-precision image, it is necessary to accurately overlap the three primary colors. To this end, an auxiliary deflection coil that independently and finely adjusts the deflection of the red, blue, and green electron beams is provided behind the cathode ray tube, and a correction waveform current synchronized with the deflection cycle is supplied to this auxiliary coil to correct color misregistration. A convergence device is required. Although the correction current can be generated by using an analog signal, a digitally generated correction waveform current is often used in recent years in order to perform correction with higher accuracy. This correction method is called digital convergence correction.

A conventional convergence correction apparatus takes a horizontal synchronizing signal of a video signal into a PLL circuit as shown in FIG. 5, generates a reference clock synchronized with the horizontal synchronizing signal, and generates various timing signals using this clock. ing.

The generated timing signal may be a signal supplied as an address clock to an address generation circuit for generating a read address for a memory in which the convergence correction data is written, or an X line supplied to a cross hatch generation circuit. There is a Y column signal and the like.

The convergence correction data read from the correction data memory circuit in accordance with the output address of the address generation circuit is converted into an analog voltage by a D / A converter and output. The analog signal is smoothed by a low pass filter (LPF), converted into a current by a feedback type output circuit, and input to a convergence correction yoke.

[0006]

However, the conventional configuration has a problem that in the case of a multi-scan display device in which the scanning frequency is switched to another frequency, the convergence correction current waveform varies depending on the frequency.

In the conventional convergence correction device, when the scanning frequency of the video signal is switched, the number of addresses in one horizontal cycle is fixed by the PLL circuit, and the output interval of the correction data becomes equal on the screen. However, since the scanning frequency is changed, the temporal output interval changes depending on the horizontal frequency.

FIG. 6 is an explanatory diagram showing the operation of the LPF in the digital convergence correction circuit. FIG. 1A shows one horizontal period of a staircase voltage waveform which is the output of the D / A converter, and FIGS. 3B, 3C and 3D.
Shows an integrated waveform obtained after passing this through the LPF. Here, (b), (c) and (d) show signals in order from a signal having a lower scanning frequency to a signal having a higher scanning frequency.

That is, as a first point, in the conventional convergence correction device, since the cutoff frequency of the LPF is constant, when the time interval of the correction data changes (when the frequency of the horizontal synchronization signal changes), FIG. (B) (c)
As shown in (d), there is a problem that the waveform of the convergence correction current cannot be kept constant.

Second, in order to keep the waveform of the convergence correction current constant, it is necessary to change the characteristics of the LPF in accordance with the time interval of the correction data, resulting in a complicated hardware structure. There was a point.

Therefore, an object of the present invention is to overcome the problems of the prior art, and it is not necessary to change the characteristics of the LPF accordingly even when the scanning frequency of the video signal to be displayed is switched to another frequency. It is another object of the present invention to provide a convergence correction device having a simple hardware configuration.

[0012]

In order to solve the above-mentioned problems, a convergence correction apparatus according to a first aspect of the present invention comprises a CRT.
And a PLL circuit for outputting a clock obtained by multiplying the horizontal synchronizing signal of the video signal displayed on the CRT by N times, receiving the clock and the vertical synchronizing signal, and outputting a memory address synchronized with the screen scanning of the CRT. An address generation circuit, a correction data memory circuit for storing data for correcting a convergence deviation on the screen of the CRT, and reading in accordance with an output address of the address generation circuit; and a CPU for rewriting data stored for adjustment A D / A converter for converting digital data, which is a read output of the correction data memory circuit, into an analog voltage, a frequency detection circuit for detecting a horizontal synchronization signal, converting the signal into a voltage, and outputting the voltage, A voltage amplifying circuit for amplifying a correction voltage from the D / A converter in accordance with the output voltage; By providing an output circuit for converting an output voltage from the circuit into a current, and a convergence correction coil for correcting convergence of the video signal with a correction current output from the output circuit, Instead, the convergence correction current waveform is always constant.

A convergence correction device according to a second aspect of the present invention has
RT, a PLL circuit for outputting a clock obtained by multiplying the horizontal synchronizing signal of the video signal displayed on the CRT by N times, and receiving the clock and the vertical synchronizing signal, outputting a memory address synchronized with the screen scanning of the CRT And a correction data memory circuit which stores data for correcting a convergence deviation on the screen of the CRT and reads the data in accordance with an output address of the address generation circuit, and rewrites data stored for adjustment. A CPU, a D / A converter for converting digital data, which is a read output of the correction data memory circuit, into an analog voltage, and detecting and converting a horizontal synchronization signal to a voltage to control a reference voltage of the D / A converter. A frequency detection circuit for outputting a voltage, an output circuit for converting an output voltage from the D / A converter to a current, A convergence correction coil that corrects the convergence of the video signal with a correction current output from the circuit, whereby the convergence correction current waveform is always constant regardless of the scanning frequency of the video signal. .

A convergence correction device according to a third aspect of the present invention provides
RT, a PLL circuit for outputting a clock obtained by multiplying the horizontal synchronizing signal of the video signal displayed on the CRT by N times, and receiving the clock and the vertical synchronizing signal, outputting a memory address synchronized with the screen scanning of the CRT And a correction data memory circuit which stores data for correcting a convergence deviation on the screen of the CRT and reads the data in accordance with an output address of the address generation circuit, and rewrites data stored for adjustment. A CPU, a frequency detection circuit for detecting a horizontal synchronization signal, converting the data into digital data, and outputting the digital data; a convergence correction data read from the correction data memory circuit multiplied by digital data output from the frequency detection circuit to generate correction data; A multiplying circuit for outputting, and a D / A converter for converting the correction data into an analog voltage And an output circuit for converting an output voltage from the D / A converter into a current, and a convergence correction coil for correcting convergence of the video signal with a correction current output from the output circuit. Irrespective of the scanning frequency, the convergence correction current waveform is always constant.

[0015]

Next, a convergence correction device according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a convergence correction device according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram of electric signals in each block of the convergence correction device according to the first embodiment of the present invention.

As shown in FIG. 1, the convergence correction device according to the first embodiment of the present invention receives a horizontal synchronizing signal 14, and outputs a clock obtained by multiplying this signal by N times.
An L circuit 1, an address generation circuit 2 that receives the clock and the vertical synchronization signal 15 and outputs a memory address synchronized with screen scanning, and stores data for correcting a convergence deviation on the screen, , A CPU 4 for rewriting data stored for adjustment, and a D / D converter for converting digital data, which is a read output from the correction data memory circuit 3, into an analog voltage. A converter 5
A frequency detection circuit 6 that detects the horizontal synchronization signal 14 and converts it to a voltage, and outputs the voltage; a voltage amplification circuit 7 that amplifies the output voltage of the D / A converter 5 according to the voltage; An output circuit 8 converts a voltage into a current, and a convergence correction coil 9 that corrects convergence of a video signal displayed on a screen by a correction current output from the output circuit 8.

Next, the operation of the convergence correction device according to the first embodiment of the present invention will be described with reference to the drawings.

The operation of the convergence correction apparatus according to the first embodiment of the present invention is described below. First, as shown in FIGS. 1 and 2, the PLL circuit 1 operates when the frequency of the horizontal synchronizing signal 14 is switched. However, in order to equalize the output interval of the correction data on the screen, a clock obtained by multiplying the horizontal synchronizing signal by N times is generated and output to the address generating circuit 2. The address generation circuit 2 receives the clock and the vertical synchronization signal 15 and outputs a memory address synchronized with screen scanning. The correction data memory circuit 3 outputs convergence correction data according to the memory address. D / A converter 5
Converts the convergence correction data into a step-like analog correction voltage shown in FIG.

Second, the frequency detection circuit 6 detects the frequency of the horizontal synchronizing signal 14, converts it into a voltage, and outputs it. The voltage amplifying circuit 7 amplifies the staircase analog voltage shown in FIG. 2A according to the voltage output from the frequency detection circuit 6, and outputs the staircase analog correction voltage shown in FIG. I do. The output circuit converts the step-like analog correction voltage shown in FIG. 2B into a current and outputs the current to the convergence correction coil. At this time, the current flowing through the correction coil has an integral waveform shown in FIG. 2C due to the inductance of the convergence correction coil 9. Assuming that the inductance of the convergence correction coil 9 is L, the applied voltage is E, and the time is t, the correction current I is represented by I = (E / L) t.

Third, when the frequency of the horizontal synchronizing signal is switched (when the time t is switched), the frequency of the horizontal synchronizing signal is detected by the frequency detecting circuit 6, and the applied voltage E is detected by the voltage amplifying circuit 7. To keep the value of the correction current I constant. At this time, the relationship between the applied voltage E and the time t is inversely proportional.

Therefore, according to the present embodiment, even when the scanning frequency of the video signal to be displayed is switched, the waveform of the horizontal period correction current flowing through the convergence correction coil 9 is kept constant, so that good convergence correction can be performed. There is.

Next, a convergence correction device according to a second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a block diagram of a convergence correction device according to a second embodiment of the present invention.

As shown in FIG. 3, the convergence correction device according to the second embodiment of the present invention receives a horizontal synchronizing signal 14, and outputs a clock obtained by multiplying this signal by N times.
An L circuit 1, an address generation circuit 2 that receives the clock and the vertical synchronization signal 15 and outputs a memory address synchronized with screen scanning, and stores data for correcting a convergence deviation on the screen, , A CPU 4 for rewriting data stored for adjustment, and a D / D converter for converting digital data, which is a read output from the correction data memory circuit 3, into an analog voltage. A converter 5
A frequency detection circuit 6 that detects the horizontal synchronization signal 14 and converts it into a voltage to output a voltage for controlling the reference voltage of the D / A converter 5, and an output that converts the output voltage from the D / A converter 5 into a current The circuit 8 includes a circuit 8 and a convergence correction coil 9 for correcting convergence of a video signal displayed on a screen by a correction current output from the output circuit 8.

Next, the operation of the convergence correction device according to the second embodiment of the present invention will be described with reference to the drawings.

The operation of the convergence correction device according to the second embodiment of the present invention is as follows, as shown in FIG.
In addition, the PLL circuit 1 generates a clock obtained by multiplying the horizontal synchronizing signal by N times in order to equalize the output interval of the correction data on the screen even when the frequency of the horizontal synchronizing signal 14 is switched, and generates an address generating circuit 2 Output to The address generation circuit 2 receives the clock and the vertical synchronization signal 15 and outputs a memory address synchronized with screen scanning. The correction data memory circuit 3 outputs convergence correction data according to the memory address. The D / A converter 5 converts the convergence correction data into a staircase analog correction voltage and outputs it.

Second, the frequency detecting circuit 6 converts the horizontal synchronizing signal 14 into a voltage and outputs a voltage for controlling a reference voltage of the D / A converter 5. This control voltage controls the amplification factor of the analog correction voltage. The operations of the output circuit 7 and the correction coil 9 are the same as in the first embodiment shown in FIG.

Third, when the frequency of the horizontal synchronizing signal 14 is switched (when the time t is switched), the frequency of the horizontal synchronizing signal 14 is detected by the frequency detection circuit 6 and the D / D
The value of the correction current I is kept constant by controlling the reference voltage of the A converter 5 and controlling the voltage E applied to the correction coil. At this time, the relationship between the applied voltage E and the time t is inversely proportional.

Therefore, according to the present embodiment, even when the scanning frequency of the video signal to be displayed is switched, the waveform of the horizontal period correction current flowing through the convergence correction coil is kept constant, and the effect of performing good convergence correction is obtained. is there.

Next, a convergence correction device according to a third embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a block diagram of a convergence correction device according to a third embodiment of the present invention.

As shown in FIG. 4, the convergence correcting device according to the third embodiment of the present invention receives a horizontal synchronizing signal 14, and outputs a clock obtained by multiplying this signal by N times.
An L circuit 1, an address generation circuit 2 that receives the clock and the vertical synchronization signal 15 and outputs a memory address synchronized with screen scanning, and stores data for correcting a convergence deviation on the screen, A correction data memory circuit 3 for reading in accordance with the output address of the CPU, a CPU 4 for rewriting data stored for adjustment, a frequency detection circuit 6 for detecting a horizontal synchronization signal, converting the signal into digital data and outputting the digital data, A multiplication circuit 17 for multiplying the convergence correction data read from the memory circuit 3 by the digital data output from the frequency detection circuit and outputting correction data; a D / A converter 5 for converting the correction data into an analog voltage; An output circuit 8 for converting an output voltage from the D / A converter 5 into a current; The correction current, and a convergence correction coil 9 for correcting the convergence of the video signal to be displayed on the screen.

Next, the operation of the convergence correction device according to the third embodiment of the present invention will be described with reference to the drawings.

The operation of the convergence correction device according to the third embodiment of the present invention is as follows, as shown in FIG.
In addition, even if the frequency of the horizontal synchronizing signal is switched, the PLL circuit 1 generates a clock obtained by multiplying the horizontal synchronizing signal 14 by N times in order to equalize the output interval of the correction data on the screen, and generates an address generating circuit. Output to 2. The address generation circuit 2 receives the clock and the vertical synchronization signal 15 and outputs a memory address synchronized with screen scanning. The correction data memory circuit 3 outputs convergence correction data according to the output address from the address generation circuit 2.

Second, the frequency detecting circuit converts the horizontal synchronizing signal into digital data and outputs the digital data to the multiplying circuit 16. The multiplication circuit multiplies the convergence correction data by the digital data output from the frequency detection circuit 6 and outputs correction data. The D / A converter 5 receives the correction data and outputs a step-like analog correction voltage shown in FIG. The operations of the output circuit 8 and the correction coil 9 are the same as those of the first embodiment shown in FIG.

Third, when the frequency of the horizontal synchronizing signal 14 switches (when the time t between the correction points changes), the frequency of the horizontal synchronizing signal 14 is detected by the frequency detection circuit 6 and the correction coil is detected. To maintain the value of the correction current I constant. The applied voltage E and time at this time
The relationship of t is inversely proportional.

Therefore, according to the present embodiment, even when the scanning frequency of the video signal to be displayed is switched, the waveform of the horizontal period correction current flowing through the convergence correction coil is kept constant, and good convergence correction can be performed.

[0040]

As described above, according to the convergence correction apparatus of the present invention, the horizontal synchronization signal of the input signal is detected, and the amplitude of the voltage applied to the convergence correction coil is controlled in accordance with the frequency. Even when the time interval of the correction data changes (when the frequency of the horizontal synchronizing signal changes), the correction current can be maintained at a constant waveform, and there is an effect that good convergence can be realized.

Further, unlike the conventional convergence correction device, a smooth convergence correction current can be generated without using an LPF for the output of the D / A converter, so that the convergence correction can be realized with an inexpensive circuit configuration. .

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a convergence correction device according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram of an electric signal in each block of the convergence correction device according to the first embodiment of the present invention.

FIG. 3 is a block circuit diagram of a convergence correction device according to a second embodiment of the present invention.

FIG. 4 is a block circuit diagram of a convergence correction device according to a second embodiment of the present invention.

FIG. 5 is a block circuit diagram of a conventional convergence correction device.

FIG. 6 is a waveform diagram of an electric signal in each block of the conventional convergence correction device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 PLL circuit 2 Address generation circuit 3 Correction data memory circuit 4 CPU 5 D / A converter 6 Frequency detection circuit 7 Voltage amplification circuit 8 Output circuit 9 Convergence correction coil 10 Deflection yoke 11 CRT 12 Horizontal deflection circuit 13 Vertical deflection circuit 14 Horizontal synchronization Signal 15 Vertical synchronization signal 16 Video signal 17 Multiplication circuit 18 Low-pass filter 19 Feedback output circuit

Claims (3)

[Claims] 1. A CRT and a P which outputs a clock obtained by multiplying a horizontal synchronizing signal of a video signal displayed on the CRT by N times
An LL circuit, an address generating circuit that receives the clock and the vertical synchronizing signal and outputs a memory address synchronized with the screen scanning of the CRT, and stores data for correcting a convergence deviation on the screen of the CRT; A correction data memory circuit that reads the data in accordance with the output address of the generation circuit, a CPU that rewrites the stored data for adjustment, and an analog voltage that outputs digital data that is a read output of the correction data memory circuit. A D / A converter for detecting the horizontal synchronizing signal, converting the voltage into a voltage, and outputting the voltage; and amplifying the voltage waveform from the D / A converter according to the voltage output from the frequency detecting circuit. A voltage amplifying circuit, an output circuit for converting an output voltage from the voltage amplifying circuit into a current, A convergence correction coil for correcting the convergence of the video signal by the output correction current, whereby the convergence correction current waveform is always constant regardless of the scanning frequency of the video signal. . 2. A CRT and a P which outputs a clock obtained by multiplying a horizontal synchronizing signal of a video signal displayed on the CRT by N times
An LL circuit, an address generating circuit that receives the clock and the vertical synchronizing signal and outputs a memory address synchronized with the screen scanning of the CRT, and stores data for correcting a convergence deviation on the screen of the CRT; A correction data memory circuit that reads the data in accordance with the output address of the generation circuit, a CPU that rewrites the stored data for adjustment, and an analog voltage that outputs digital data that is a read output of the correction data memory circuit. A D / A converter, a frequency detection circuit for detecting a horizontal synchronizing signal and converting it to a voltage, and outputting a voltage for controlling a reference voltage of the D / A converter, and an output voltage from the D / A converter An output circuit that converts
A convergence correction coil for correcting the convergence of the video signal by a correction current output from the output circuit;
The convergence correction current waveform is always constant irrespective of the scanning frequency of the video signal. 3. A CRT and a P which outputs a clock obtained by multiplying a horizontal synchronizing signal of a video signal displayed on the CRT by N times
An LL circuit, an address generating circuit that receives the clock and the vertical synchronizing signal and outputs a memory address synchronized with the screen scanning of the CRT, and stores data for correcting a convergence deviation on the screen of the CRT; A correction data memory circuit for reading the data in accordance with the output address of the generation circuit, a CPU for rewriting the stored data for adjustment, and a frequency detection for detecting a horizontal synchronization signal, converting the signal into digital data and outputting the digital data A multiplication circuit that multiplies the convergence correction data read from the correction data memory circuit by the digital data output from the frequency detection circuit and outputs correction data,
A D / A converter for converting the correction data into an analog voltage, an output circuit for converting an output voltage from the D / A converter into a current, and a correction current output from the output circuit, for correcting convergence of a video signal. And a convergence correction coil, wherein the convergence correction current waveform is always constant regardless of the scanning frequency of the video signal.