JP3509357B2 - Digital convergence device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for correcting the convergence of a color television receiver, and a digital convergence device capable of performing highly accurate correction in which mutual interference of correction data between inside and outside of an effective screen is reduced. Patent classification H04N 9/28).

[0002]

2. Description of the Related Art Generally, in a projection type color image receiving apparatus for enlarging and projecting on a screen by using three projection tubes which emit three primary colors, the incident angles of the projection tubes with respect to the screen are different from each other on the screen. Color shift occurs. The so-called convergence, which superimposes these three primary colors, is a method in which a convergence correction waveform is created in an analog manner in synchronization with the horizontal and vertical scanning periods, and the size and shape of this waveform are changed to make adjustments. There is a problem in terms of convergence accuracy. Therefore, a digital convergence device has been proposed as a method capable of handling various signals and having high convergence accuracy.

FIG. 6 shows the configuration of a conventional digital convergence device. In FIG. 6, 1 is a scanning line number determination unit,
2 is an address control unit, 3 is a vertical interpolation calculation unit, 4 is a volatile memory, 5 is a storage element, 6 is a control panel, 7 is a test pattern generation circuit, 8 is a video circuit, 9 is a D / A converter, 10 Is a low-pass filter (hereinafter referred to as LPF), 12 is an output amplifier, 13 is a convergence coil, 29 is a DC detection circuit, 30 is an A / D converter, and 19 is a synchronization signal synchronized with the deflection current cycle. . The operation of the digital convergence device configured as above will be described below.

In FIG. 6, a synchronizing signal 19 synchronized with the deflection current cycle is input to the address control section 2 and the scanning line number determination section 1. Further, the scanning line number discrimination result of the scanning line number discriminating unit 1 is inputted as a control signal of the address control unit 2, and the test pattern generating circuit 7 is operated by this control signal.
And the vertical interpolation calculation unit 3.

First, the test pattern generating circuit 7 is driven by the control signal from the address control section 2, and the video circuit 8 projects a test pattern (for example, a cross hatch pattern) on the projection screen.

Next, a correction amount is written in the storage element 5 while looking at the screen by using a data writing key of a color to be corrected, for example, a red key provided on the control panel 6. Further, in order to correspond to various image signal sources, it is necessary to perform the processing between the adjustment points according to the number of scanning lines, so that the synchronization signal 19 is supplied to the scanning line number determination unit 1 and the address control unit 2. Is added to the vertical interpolation calculation unit 3 via. The vertical interpolation calculation unit 3 obtains the number of scanning lines R, which is the number of adjustment points of R = P / (Q + 1), from the number P of scanning lines in one field and the number Q of adjustment points in the vertical direction, and every R scanning lines. Then, a vertical interpolation calculation operation is performed based on the correction data of the storage element 5, and the vertical interpolation calculation result is written in the volatile memory 4 as needed.

After the convergence correction data stored in the volatile memory 4 is converted into an analog amount by the D / A converter 9, it is smoothed by the LPF 10. The output 34 of the LPF 10 is input to the output amplifier 12, and the convergence correction data amplified here is input to the convergence coil 13.
Apply to.

However, in the process of converting the convergence correction data stored in the volatile memory 4 into an analog amount and transmitting it to the convergence coil 13, it is originally applied to the convergence coil 13 due to the influence of aging, temperature change and the like. There was a problem that a DC drift component was superimposed on the convergence correction waveform and appeared as a static drift on the projection screen. As means for solving this problem, the one described in Japanese Patent Application Laid-Open No. 3-76396 is conventionally known.

In FIG. 6, the convergence coil 13
The convergence correction waveform 31 applied to is input to the DC detection circuit 29, and the DC component causing the static drift is detected. The detection result 32 is converted into a digital amount 33 by the A / D converter 30 and input to the vertical interpolation calculation unit 3.
In the vertical interpolation calculation unit 3, the output 33 of the A / D converter 30 is subtracted from the convergence correction data 20 stored in the volatile memory 4, and the calculation result is stored again in the volatile memory 4 as correction data. By storing it, it is possible to cancel the DC component that causes static drift. The process will be described in detail with reference to FIG.

In FIG. 7, for example, when the number of effective bits of the convergence correction data stored in the volatile memory 4 is 8 bits, the center of the dynamic range of the convergence correction data is "10000000". Here, the output 20 of the volatile memory 4 is “10000.
000 ”, it is assumed that the output voltage 31 of the output amplifier 12 is, for example, + bV (when expressed in 8 bits, assumed to be“ 00001000 ”) when it is assumed to be 0V in the ideal state. This + bV corresponds to the DC component that causes the static drift. In the conventional configuration shown in FIG. 6, in order to cancel the DC component of + bV, the vertical interpolation calculation unit 3 performs a correction calculation as described below.

"10000000"-"0000100"
0 ”=“ 01111000 ”This operation result“ 01111000 ”(corresponding to −bV when converted into an analog amount) is stored in the volatile memory 4 again, so that the convergence coil 13 has (−b) + (+ b). = 0V is applied, and as if to the convergence coil 13,
The DC drift component is not superimposed, and the static drift component can be suppressed.

[0012]

However, in the conventional configuration as described above, the convergence correction data stored in the volatile memory 4 is changed in order to suppress the static drift. As a result, there are the following problems.

In the conventional configuration as shown in FIG. 6, as shown in the example of FIG. 7, the center of the convergence correction data is shifted in order to suppress static drift with respect to the center "10000000" of the dynamic range of the convergence correction data. (“01111000” in this example) is required, resulting in a problem of narrowing the dynamic range of the digital convergence device.

Furthermore, since the DC drift component is detected from the convergence correction waveform 31 applied to the convergence coil 13, the static drift appearing at the output 31 of the output amplifier 12 is canceled in the conventional configuration. However, the DC drift component superimposed on the correction waveform of the input 34 to the output amplifier 12 cannot be canceled. Therefore, the output amplifying unit 12 that operates in a large amplitude
In the digital convergence device in which the circuit and the other circuit are configured on different boards, when performing maintenance for board replacement, in the conventional configuration, the volatile memory 4 is stored in any circuit board when it is replaced. There was a problem that resetting of the stored convergence correction data was necessary in the field.

[0015]

In order to solve the above-mentioned conventional problems, the digital convergence apparatus of the present invention comprises:
After the convergence correction data stored in the volatile memory is converted into an analog amount by the D / A converter, it is passed through the LPF, and the DC drift component generated at the output of the LPF is detected by the A / D converter. Based on the detection result, the calculation unit performs a correction calculation for the purpose of canceling the DC drift component, and the correction calculation result is added to the output of the LPF to obtain the convergence stored in the volatile memory. The LP can be automatically used without changing the correction data.
It is characterized by canceling the DC component generated in F.

According to the present invention, it is possible to provide a digital convergence device that automatically cancels the DC drift component generated in the LPF without impairing the dynamic range of the convergence correction data stored in the volatile memory. The static drift of the entire digital convergence device can be easily suppressed by forming a self-contained DC component canceling circuit in the output amplifier.

Furthermore, in a normal digital convergence device in which the output amplification section and the other blocks are formed on different substrates, the maintainability of substrate exchange can be improved.

[0018]

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION A digital convergence device according to a first aspect of the present invention is a scanning line number discriminating section which receives a synchronization signal synchronized with a deflection current cycle, and a scanning line number discrimination which receives the synchronization signal as an input. An address control unit controlled by a unit, a storage element that stores convergence correction data, and a vertical interpolation calculation unit that performs vertical interpolation calculation based on the convergence correction data that is controlled by the address control unit and stored in the storage element. And storage means for holding the data interpolated by the vertical interpolation computing section, a D / A converter for converting the data in the storage means into an analog signal, and an output of the D / A converter A low-pass filter, an adder having the output of the low-pass filter as one input, an output amplifier having the output of the adder as an input, and the output amplifier Driven by a convergence coil, an A / D converter for converting the output of the adder into a digital signal, and an output of the A / D converter as one input, and a comparison voltage expressed by a digital value as the other input. And a D / A converter for converting the calculation result of the calculation unit into an analog quantity, and the calculation of the calculation unit. The output of the D / A converter for converting the result into an analog amount is used as the other input of the adder so as to cancel the DC drift component input from the adder to the output amplification section, and the output amplification The substrate of the unit includes a scanning line number determination unit, an address control unit, a storage element, a vertical interpolation calculation unit, a storage unit, a D / A converter, a low-pass filter, an adder, and A. Compared with / D converter And, an operation unit,
The block of the D / A converter is configured by a separate substrate with respect to the substrate of any block, and the D / A converter is generated by the low pass filter without impairing the dynamic range of the convergence correction amount in the digital convergence device. It has an effect of canceling the DC drift component and not inputting it to the output amplifier.

[0020]

A digital convergence apparatus according to a second aspect of the present invention is the digital convergence apparatus according to the first aspect, further comprising means for performing a correction operation only during a period when a synchronization signal synchronized with the deflection current cycle is input to the operation unit. It has a function of automatically detecting and offsetting the DC drift component appearing in the output of the low-pass filter only during the period when the interrupt signal is input to the arithmetic unit.

[0022]

A digital convergence apparatus according to a third aspect of the present invention is the digital convergence apparatus according to the first aspect, wherein the storage element having means for storing the correction calculation result of the calculation section and the calculation section are synchronized with the deflection current cycle. The correction operation result stored in the storage element is read only during the period when the synchronizing signal is input, and the operation result is written in the D / A converter. It has the function of being compatible with the device.

(Embodiment 1) Embodiments of the first and second inventions of the present invention will be described below with reference to FIGS.

In FIG. 1, 1 is a scanning line number determination unit, 2 is an address control unit, 3 is a vertical interpolation calculation unit, 4 is a volatile memory, 5 is a storage element, 6 is a control panel, and 7 is a test pattern generation circuit. , 8 is a video circuit, 9 is a D / A converter, 10 is an LPF, 11 is an adder, 12 is an output amplifier,
13 is a convergence coil, 14 is an A / D converter, 1
Reference numeral 5 is a comparison voltage represented by a digital value, 16 is a comparator, 17 is an arithmetic unit, 18 is a D / A converter, and 19 is a synchronizing signal synchronized with the deflection current cycle. The operation of the digital convergence device configured as described above will be described below.

In FIG. 1, a synchronizing signal 19 synchronized with the deflection current cycle is input to the address control section 2 and the scanning line number determination section 1. Further, the scanning line number discrimination result of the scanning line number discriminating unit 1 is inputted as a control signal of the address control unit 2, and the test pattern generating circuit 7 is operated by this control signal.
And the vertical interpolation calculation unit 3.

First, the test pattern generating circuit 7 is driven by the control signal from the address control unit 2, and the video circuit 8 projects a test pattern (for example, a cross hatch pattern) on the projection screen.

Next, the correction amount is written in the storage element 5 while looking at the screen with the data writing key of the color to be corrected, for example, the red data writing key provided on the control panel 6. Further, in order to correspond to various image signal sources, it is necessary to perform the processing between the adjustment points according to the number of scanning lines, so that the synchronization signal 19 is supplied to the scanning line number determination unit 1 and the address control unit 2. Is added to the vertical interpolation calculation unit 3 via. The vertical interpolation calculation unit 3 obtains the number of scanning lines R, which is the number of adjustment points of R = P / (Q + 1), from the number P of scanning lines in one field and the number Q of adjustment points in the vertical direction, and every R scanning lines. Then, a vertical interpolation calculation operation is performed based on the correction data of the storage element 5, and the vertical interpolation calculation result is written in the volatile memory 4 as needed.

The convergence correction data stored in the volatile memory 4 is converted into an analog amount by the D / A converter 9 and then smoothed by the LPF 10. The output 21 of the LPF 10 is input to one of the adders 11 and the output thereof is input to the output amplification unit 12. The convergence correction data amplified by the output amplifier is applied to the convergence coil 13.

Further, the output of the adder 11 is set to the A / D
It is input to the converter 14 and converted into a digital signal. This digital signal is input to one of the comparators 16 and voltage comparison is performed with the comparison voltage 15 represented by a digital value serving as a comparison reference. The result 25 of the voltage comparison by the comparator 16 is input to the calculation unit 17, and the calculation unit 17 performs the calculation for the purpose of canceling the DC drift component generated in the LPF 10 by the voltage comparison result 25. The correction calculation result is input to the D / A converter 18, and the correction calculation result 27 is input to the other side of the adder 11. The operation process of automatically canceling the DC drift component superimposed on the output of the LPF 10 in the digital convergence device of the present invention configured as described above will be described in detail with reference to FIG.

In FIG. 2, for example, when the number of effective bits of the convergence correction data stored in the volatile memory 4 is 8 bits, the center of the dynamic range of the convergence correction data is "10000000". Furthermore, the output 20 of the volatile memory 4 is "100000.
It is assumed that the input voltage 31 of the output amplifying unit 12 is 0 V in the ideal state when "00". Here, the output 20 of the volatile memory 4
The address control unit 2 controls the vertical interpolation calculation unit 3 so that the value becomes “10000000”. At this time, if a DC drift component of, for example, + aV (assumed to be “00001000” when expressed in 8 bits) is superimposed on the input voltage of the output amplification unit 12, the output of the A / D converter 14 is , "10000000" + "00001000" = "10
001000 ". The result of this A / D converter 14 and the comparison voltage 15
By comparing and with the comparator 16, “10000000” − “10001000” = “11
111000 ”, and from this result, the calculation unit 17 determines that the output amplification unit 1
It is determined that the + aV DC drift component is superimposed on the second input voltage 22. From this determination result, the calculation unit 1
A correction signal such that the output of the D / A converter 18 becomes -aV is input to the D / A converter 18, and the output voltage -aV is input to the other of the adder 11. As a result, the output of the adder 11 becomes (the output of the adder 11 when there is no correction) + (correction output of the D / A converter 18) = a + (− a) = 0V, and the input of the output amplifier 12 It is possible to cancel the DC drift component originally superposed on.

As described above, according to the digital convergence device of the present embodiment, the DC drift component generated in the LPF is automatically constructed with a simple circuit configuration without impairing the dynamic range of the convergence correction amount. It is possible to cancel with high precision.

Further, the output of the adder 11, that is, the signal before being input to the output amplifying section 12 is detected to control the DC drift component, and the DC drift component is not superposed on the input of the output amplifying section at all. Since the state is realized, it is not necessary to reset the convergence correction data stored in the memory 4 at the time of exchanging the substrate of the output amplifying unit which is a separate substrate, so that the maintainability of the substrate exchanging is dramatically improved.

(Embodiment 2) Next, an embodiment of the invention described in the third and fourth inventions will be described with reference to FIG. The same components as those in the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 3, the synchronizing signal 19 synchronized with the deflection current period is the scanning line number discriminating unit 1 and the address control unit 2.
Is also input to the arithmetic unit 17 as an interrupt signal. As a result, the address control unit 2 writes the same correction data as the comparison voltage 15 to the volatile memory 4 via the vertical interpolation calculation unit 3 only during the blanking period of the synchronization signal 19 synchronized with the deflection current cycle, and the calculation unit 17 is the output amplifier 12
The DC drift component superimposed on the input 22 of the A / D
It is detected via the converter 14. The calculation unit 17 performs a correction calculation operation based on the detected result and outputs the correction calculation result to the LP.
By adding to the output of F10, the DC drift component superimposed on the input of the output amplification unit 12 is canceled. When the synchronization signal 19 synchronized with the deflection current cycle is not in the blanking period, the correction calculation operation of the calculation unit 17 is stopped, and the D / A converter 18 corrects the calculation unit 17 during the blanking period. Holds the calculation result.

As described above, by controlling the correction calculation operation by the interrupt signal, it is possible to observe the variation due to the secular change or the temperature change of the DC drift component superimposed on the input 22 of the output amplifying section 12 at any time, and to observe the disturbance. D / A converter 1
Even if the output of No. 8 fluctuates, it can be dealt with within one cycle of the synchronizing signal 19 and the reliability is improved.

Further, it is possible to prevent image distortion by performing a correction calculation operation during the blanking period and holding the output of the D / A converter 18 during the image period.

(Embodiment 3) Next, an embodiment of the invention described in the fifth and sixth aspects of the invention will be described with reference to FIGS. The same components as those in the above-described embodiment are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 4, reference numeral 28 is a storage element for storing the correction calculation result of the calculation section 17. In the digital convergence device of the third and fourth inventions, when the output amplifier 12 has multiple channels, a series of circuit operations for canceling the DC drift component input to the output amplifier 12 are performed on all channels during the retrace line period. There is a problem that it cannot be done. Therefore, in the digital convergence apparatus of the fifth and sixth inventions, the correction calculation result of the calculation unit 17 is input to the D / A converter 18 and is written and stored in the storage element 28. As a result, as shown in FIG. 5, when the synchronization signal 19 synchronized with the deflection current cycle is input to the arithmetic unit 17 as an interrupt signal, the arithmetic unit 17 reads the correction arithmetic result stored in the storage element 28, The correction calculation result is input to the D / A converter 18, and its output is supplied to the adder 11. At this time, the length of the blanking period may be such that the calculation unit 17 has a time to read the correction calculation result stored in the storage element 28 and a time to write the correction calculation result to the D / A converter 18.

As described above, the configuration of the present invention makes it possible to cope with the output fluctuation of the D / A converter 18 in which the normal output state is held due to disturbance or the like even when the output amplifier 12 has multiple channels. Furthermore, it is possible to deal with the case where the blanking period of the synchronization signal 19 is short.

Further, when the output amplifier 12 has multiple channels, there is a demand for coping with the secular change of the DC drift component superposed on the input 22 of the output amplifier 12 and the fluctuation due to the temperature characteristic. During the blanking period of the synchronizing signal 19, only one channel performs the series of correction circuit operations described in the second embodiment, and the other channels read the correction calculation result stored in the storage element 28 and re-execute. D
This can be handled by writing in the / A converter 18.
If the series of correction circuit operations described in the second embodiment are completed during the blanking period of the synchronizing signal 19, the same effect can be obtained even if several channels are operated during one blanking period. Needless to say that you get

[0042]

As described above, according to the digital convergence device of the present invention, the DC drift component generated by the low pass filter is automatically and simply configured without impairing the dynamic range of the convergence correction amount. In addition, it is possible to cancel with high accuracy. Furthermore, since the substrate of the output amplifier for large-amplitude operation is separated from the substrate of the other circuit blocks, a state in which no DC drift component is superimposed on the input of the output amplifier is realized. Since it is not necessary to reset the convergence correction data when exchanging the substrate, the maintainability of exchanging the substrate is dramatically improved.

The DC drift component generated by the output amplifying unit itself is suppressed by the output amplifying unit itself by forming a circuit for canceling the self-contained DC drift component, thereby suppressing static drift appearing on the projection screen. Is possible.

Further, by inputting a synchronizing signal synchronized with the deflection current cycle to the arithmetic unit as an interrupt signal, it is possible to observe the variation due to the secular change or temperature change of the DC drift component superimposed on the input of the output amplifying unit at any time. Even if the output of the D / A converter fluctuates due to disturbance or the like, it can be dealt with within one cycle of the synchronization signal, which leads to improvement in reliability. Further, by performing the correction calculation operation during the blanking period and outputting the correction calculation result during the video period, it is possible to prevent the video from being disturbed.

Further, by storing the correction calculation result of the calculation section in the storage element, a series of circuit operations for canceling the DC drift component input to the output amplification section 12 is returned when the output amplification section has multiple channels. Even when all the channels cannot be performed during the line period, it is possible to deal with the fluctuation of the output of the D / A converter. Further, even when the blanking period of the synchronizing signal is short and a series of circuit operations for canceling the DC drift component input to the output amplification unit 12 cannot be performed for all channels during the blanking period, the same measure can be taken. .

[Brief description of drawings]

FIG. 1 is a block diagram of a digital convergence device according to a first embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the digital convergence device according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a digital convergence device according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a digital convergence device according to a third embodiment of the present invention.

FIG. 5 is an operation explanatory diagram of the digital convergence device according to the third embodiment of the present invention.

FIG. 6 is a block diagram of a conventional digital convergence device.

FIG. 7 is an operation explanatory diagram of a conventional digital convergence device.

[Explanation of symbols]

1 Scanning line number determination unit 2 Address control section 3 Vertical interpolation calculation section 4 Volatile memory 5 memory elements 6 control panel 7 Test pattern generation circuit 8 video circuits 9 D / A converter 10 Low pass filter 11 adder 12 Output amplifier 13 Convergence coil 14 A / D converter 15 Digital reference voltage 16 Comparator 17 Operation part 18 D / A converter 19 Sync signal synchronized with deflection current cycle 28 Memory element

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-5-14912 (JP, A) JP-A-64-65992 (JP, A) JP-A-3-76396 (JP, A) JP-A-5- 207487 (JP, A) JP 7-184222 (JP, A) JP 4-47791 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 9/28

Claims (3)

(57) [Claims] 1. A synchronization signal synchronized with a deflection current cycle is input.
And the scanning line number determination unit,
The address control unit controlled by the scanning line number determination unit and the address control unit
A storage element for storing the convergence correction data;
Controlled by the dress control unit and stored in the storage element
Performs vertical interpolation calculation based on convergence correction data
Interpolation calculation by the vertical interpolation calculation unit and the vertical interpolation calculation unit
Storage means for holding the stored data, and the data stored in the storage means.
A D / A converter for converting the data into an analog signal, and the D
A low pass filter with the output of the A / A converter as an input,
Adder with output of low-pass filter as one input
An output amplifying section using the output of the adder as an input;
A convergence coil driven by the output amplifier,
A / D converter for converting the output of the adder into a digital signal
Converter and the output of the A / D converter as one input,
The comparison voltage expressed in digital value is used as the other input.
Control by the comparator that compares users and the comparison result of the comparator.
Control unit and the calculation result of the calculation unit in analog quantity
And a D / A converter for converting into
The output of the D / A converter that converts the
From the adder to the output amplifier as the other input
Configured to cancel the input DC drift component,
And the substrate of the output amplification unit, the scanning line number determination unit,
The address control unit, the storage element, the vertical interpolation calculation unit,
Storage means, D / A converter, low-pass filter, and addition
, A / D converter, comparator, arithmetic unit, D / A converter
For each block board of the converter,
A digital convergence device. 2. The calculation unit is synchronized with the deflection current cycle.
Equipped with means to perform correction calculation only during the period when the signal is input
The digital convergence device according to claim 1, wherein 3. A means for storing the correction calculation result of the calculation section.
The storage element having the
The storage element is written only during the period when the expected synchronization signal is input.
Read the correction calculation result that you remember, and set the calculation result to D
The digital convergence device according to claim 1, further comprising means for writing in the A / A converter .