JPH03127588A - Digital convergence device - Google Patents

Abstract

PURPOSE:To prevent occurrence of write of an erroneous correction data and to attain stable operation by detecting a non-signal time and stopping the convergence operation with the detected signal. CONSTITUTION:A horizontal synchronizing signal from an input terminal 41 is fed to a frequency division counter 58, a frequency division ratio with a clock signal from a clock generator 59 of a CPU is obtained by a CPU section 57 and a horizontal scanning frequency detection signal is obtained at an output terminal 43. A vertical synchronizing signal from an input terminal 40 is directly fed to the CPU section 57 and how many horizontal synchronizing signals from the input terminal 41 are generated in the vertical synchronizing signal, that is, the number of scanning lines in one field is obtained by the CPU section 57 and a scanning line detection signal is obtained at an output terminal 42. Then at the detection of a non-signal, when the scanning line number is detected and the horizontal scanning frequency does not exist within a specific range, a non-signal detection signal is outputted from an output terminal 44. Then the convergence operation is stopped by the detection signal at the non-signal time. Thus, stable operation is attained because no write of erroneous correction data takes place.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a device for correcting convergence in a color television receiver, and more particularly to a digital communication device that operates stably and is compatible with various signal sources. It is something.

Conventional technology In general, in a projection type color receiver that uses three projection tubes that emit three primary colors to project enlarged images onto a screen, the angle of incidence of the projection tubes on the screen is different for each projection tube, which causes color shift on the screen. arise. The superposition of these three primary colors, so-called convergence, is achieved by creating an analog convergence correction waveform in synchronization with the horizontal and vertical scanning cycles, and adjusting the size and shape of this waveform. There is a problem with accuracy. Therefore, as a method that can handle various signals and has high precision, for example,
A digital convergence device is proposed in Japanese Patent No. 88.

The conventional digital convergence device will be explained below. Fig. 12 shows a block diagram of a conventional digital convergence device, in which a convergence correction pattern such as a crosshatch pattern (shown in Fig. 13) is projected on the screen, and the convergence correction amount for each adjustment point is displayed. This data is digitally written into a frame memory, read out, D/A converted, and convergence correction is performed.

FIG. 12 shows a block diagram of a conventional digital convergence device. In the figure, 6 is a crosshatch generator, 7 is a video circuit, 5 is a read address control section, 8 is a write address control section, 12 is a control panel, 1
1 is a reversible counter, 9 is a multiplexer, 10 is one frame memory, 18 is a register, 29 is a vertical adjustment point-to-point processing section, 14 is a D/A conversion circuit, 5 is an LPF, 26 is a scanning line number detection section, Reference numeral 27 designates an adjustment point interval number setting section, 28 a coefficient calculation section, 16 an output amplification section, and 30 a deflection circuit. Horizontal and vertical periodic pulses synchronized with the deflection current period are added as synchronization signals, thereby causing the read address control unit 5
to drive. The pulse from the read address control section 5 is used to drive the crosshatch generator 6 to project a crosshatch pattern on the projection screen. On the other hand, use the address key on the control panel 12 to select a cross point at the location where convergence correction is required, for example, as shown in Fig. 13A>
, and set the position address in the write address control unit 8. Next, using the data write key of the color to be corrected, for example, red provided on the control panel 12, write the correction amount into the one frame memory 10 through the data reversible counter 11 while looking at the screen. Normally, writing to the 1-frame memory 10 is controlled by the multiplexer 9 so that it is performed during the blanking period of the video signal. Therefore, reading is not impaired.

Similar operations are performed at each adjustment point as described above.

Next, the readout of the l frame memory 10 is performed by the readout address control unit 5 for each adjustment point position on the screen, and through the register 18 driven by the readout address control unit 5, processing between vertical adjustment points is performed. Part 28
The correction amount processing is performed in the vertical scanning direction between adjustment points. In order to correspond to various signal sources, it is necessary to perform adjustment point-to-point processing according to the number of each scanning line. Therefore, the input synchronizing signal is supplied to the scanning line number detection section 26, which detects the number of scanning lines in one field, and then adds it to the adjustment point interval number setting section 27. The number of adjustment points setting unit 27 calculates N=M/(L+
1) Find the number N of scanning lines between the adjustment points of the book, and calculate the number N of scanning lines between the adjustment points of the book, and
Added to 8. In addition to the write address control section 8 and the read address control section 5, the operation is switched to N addresses. The output of the vertical adjustment point-to-point processing section 29 operating as described above is converted into an analog signal by the D/A conversion circuit 14 to obtain a signal. The signal between the adjustment points in the horizontal direction is smoothed by a low-pass filter (LPF) 15 according to the correction amount of the adjustment point in each row, and after being amplified by an output amplification section 16, is supplied to a convergence yoke 17. Further, the detection signal from the scanning line number detection section 26 is applied to the deflection circuit 30 as a system switching signal to switch the deflection amplitude, frequency, etc.

As described above, since independent correction can be performed for each adjustment point for each signal source, convergence correction can be performed with high accuracy.

Problems to be Solved by the Invention However, although the digital convergence device configured as described above can accurately adjust the convergence for each signal source, it may malfunction when there is no signal, or it may cause deflection, etc. There was a problem in that the receiver could be damaged due to an abnormality in system switching. Furthermore, since it is necessary to input correction data for various signals, there is a problem in that adjustment takes time. Further, there is a problem in that the signal source having a high horizontal scanning frequency cannot be handled because the calculation speed of the vertical adjustment point-to-point processing section is slow.

In view of this, the present invention detects the time when there is no signal from the synchronization signal, stops the digital convergence operation when there is no signal, operates the receiver by setting it to a specific setting mode, and also operates the receiver by setting it to a specific setting mode. It is an object of the present invention to provide a digital convergence device that operates stably and is compatible with each signal source by writing the same correction data into the means and performing processing between vertical adjustment points using two memories.

Means for Solving the Problems The first aspect of the invention is a means for detecting the presence or absence of a synchronizing signal, a frequency, and the number of scanning lines, a means for creating correction data corresponding to the frequency and the number of scanning lines based on the detection signal, and Means is provided for causing the signal to cease convergence operation and for setting the receiver to a particular mode of operation.

The second aspect of the invention includes means for storing convergence correction amounts for adjustment points in n memory elements, and means for simultaneously writing the same correction data in the n memory elements.

The third aspect of the invention is a means for interpolating between adjustment points in the vertical direction, a first memory for storing correction data for the first adjustment point, and a second memory for storing correction data for the second adjustment point. It is provided with means for creating correction data between adjustment points 1 and 2 using the memory.

According to the first invention, it detects when there is no signal, and uses this detection signal to forcibly set the convergence operation and receiver system switching to a specific mode, and also to stop the human power of the key for control. Therefore, stable display operations can be performed without malfunctions. In addition, since we create correction data corresponding to the frequency and number of scanning lines for the synchronization signal,
Compatible with various signal sources.

According to the second invention, by writing the same correction data into n storage means at the same time, the adjustment time can be shortened because manual input of the correction data into n storage means, that is, only one adjustment is required. Can be shortened.

According to the third invention, by performing time series processing that interpolates between adjustment points in the vertical direction using two memories,
By slowing down the calculation rate, it becomes possible to support signal sources with high horizontal scanning frequencies, and the range of support can be expanded.

EXAMPLE An example of the present invention will be described below with reference to the drawings. 1 to 4 show a block diagram and a display screen diagram of a digital convergence device according to a first embodiment of the present invention.

In FIG. 1, numeral 33 is an address control section for controlling reading and writing of the memory; 35 is a horizontal scanning frequency detection section for detecting the horizontal scanning frequency from a synchronization signal;
36 is a signal detection unit for detecting the presence or absence of a signal from a synchronization signal; 34 is an adjustment point/coefficient setting unit for setting the number of adjustment points in the vertical direction and a coefficient for interpolation according to the number of scanning lines; 32 is L for controlling the cutoff frequency according to the horizontal scanning frequency for smoothing the correction data in the horizontal direction.
FIG. 2 shows a display screen diagram showing the positions of adjustment points, FIG. 3 shows a block diagram of each detection section, and FIG. 4 shows an operation diagram. In this figure, parts that operate in the same way as in the conventional figure 12 are designated by the same numbers and their explanations will be omitted.

The operation of the digital convergence device of this embodiment configured as described above will be described below. A synchronization signal is input to the input terminal, and the address control section 33 generates various address signals for controlling the frame memory 10.The crosshatch generator 6 generates, for example, the horizontal direction 11 as shown in the display screen diagram of FIG. A crosshatch pattern of 9 rows and 9 columns in the vertical direction is generated and displayed on the screen. The synchronization signal is also supplied to a scanning line number detection section 26, a horizontal scanning frequency detection section 35, and a signal detection section 36 to detect the number of scanning lines, frequency, and presence or absence of a signal corresponding to each signal source.

The detection signal from the scanning line number detection unit 26 is supplied to the adjustment point number/coefficient setting unit 34, so that even if the signal source has a different number of scanning lines, the number of adjustment points in the vertical direction is always adjusted as shown in the crosshatch signal shown in FIG. The number of adjustment points and coefficients for interpolation are set so that they are the same. The signal from the adjustment point number/coefficient setting unit 34 is supplied to the vertical adjustment point processing unit 29, which creates correction data corresponding to each scanning line between adjustment points that are not stored in the frame memory 10. The output from the vertical adjustment point processing unit 29 is converted into an analog quantity by the D/A conversion circuit 13 to create a correction waveform.

Next, regarding horizontal processing, in order to set the horizontal adjustment points so that they are always the same even when signal sources with different horizontal scanning frequencies are used, as shown in the crosshatch signal shown in Figure 2, the following procedure is used. This kind of control is being carried out. The signal from the horizontal scanning frequency detection section 35 is sent to the address control section 33.
and generates address signals corresponding to each scanning frequency.

Further, the detection signal is supplied to an LPF 32 for smoothing correction data in the horizontal direction, and the cutoff frequency is controlled in accordance with each scanning frequency to smooth the correction data corresponding to the scanning frequency.

Next, the operation of the signal detection section will be explained. Signal detection section 3
6 detects the presence or absence of a synchronization signal, and this detection signal is supplied to the scanning line number detection section 26, the horizontal scanning frequency detection section 35, the control panel 12, and the crosshatch generator 6. When there is no signal, the signals of each detection unit 26 and 35 are forcibly set to a specific mode, and the control panel 12 stops manual key operation, and the crosshatch generator 6
In this case, the hatch signal output is stopped. As described above, the signals set by each detection unit 26, 35 when there is no signal are supplied to the deflection circuit 30 in the receiver, and the oscillation frequency, amplitude, etc. are controlled.

Next, in order to explain each detection section in detail, the block diagram of FIG. 3 and the operation diagram of FIG. 4 will be used. Scanning line number detection unit 26, horizontal scanning frequency detection unit 35, and signal detection unit 3 in FIG.
6 is composed of a CPU section 57 as shown in FIG. An input terminal 40 is supplied with a vertical synchronization signal, and an input terminal 41 is supplied with a horizontal synchronization signal. The horizontal synchronization signal from the input terminal 41 is supplied to a frequency division counter 58, and the frequency division ratio with respect to the clock signal from the CPU clock generator 59 is calculated by the CPU.
A horizontal scanning frequency detection signal is obtained at the output terminal 43.

The vertical synchronizing signal from the input terminal 40 is directly supplied to the CPU section 57, and the CPU section 57 determines how many times the horizontal synchronizing signal from the input terminal 41 occurs in the vertical synchronizing signal, that is, the number of scanning lines in the l field. As a result, a scanning line number detection signal is obtained at the output terminal 42. Next, to detect no signal, a no signal detection signal is output from the output terminal 44 when the scanning line number detection and the horizontal scanning frequency are not within a specific range. Fourth
As shown in the diagram of operation when there is no signal, key operations on the control panel 12 are stopped and the scanning line/frequency detection section is set to specific mode, and the operation of the convergence receiver is controlled by this signal.

As described above, according to this embodiment, by detecting a no-signal period and stopping the convergence operation using this detection signal, it is possible to perform stable operation because incorrect correction data is not written. . Furthermore, when a detection signal or the like is used to switch the receiver's system, the receiver is forced to operate in a specific operating mode without causing any abnormal operation when there is no signal, so the receiver can always operate stably. In addition, since correction data corresponding to the frequency and number of scanning lines is created for the synchronization signal, it can be used with various signal sources.

5 to 8 show a second embodiment of the invention.

First, the configuration is different from that of the embodiment in that the same correction data is written into n storage means at the same time. In FIG. 5, 39 is the same data write operation unit for writing the same correction data to n frame memories 38, 38 is a frame memory configured with n memory planes, and 37 is the number of scanning lines from the synchronization signal. and a scanning line number/frequency detection section 37 for detecting the scanning frequency. In FIG. 5, components that perform the same operations as those in the first embodiment are designated by the same numbers and their explanations will be omitted.

In order to explain the digital convergence device of this embodiment in detail, the display screen diagram in FIG. 6, the correction data diagram in FIG. 7, and the memory layout diagram in FIG. 8 will be used.

In order to accommodate various aspects as shown in the display screen diagram shown in FIG. 6, a plurality of memory planes are required, and correction data must be written or adjusted for each memory plane. When the correction data at ASI (solid line) in FIG. 6 is as shown in FIG. 7, the correction amount in FIG. 7 is D2 for aspect AS2 (broken line) in FIG. - dot-dashed line), the correction amount in Fig. 7 is D
3 would be good. After the correction data shown in FIG. 7 is input into the selected memory 40 shown in FIG. The data is written to the memories 41 to 45 of. For this operation, a key for writing the same data is provided on the control panel 12,
After this key operation is determined by the same data write operation unit 39, the address control unit 33 selects a memory address based on this operation signal, and correction data is written in a memory area that is not written in the frame memory 38. Therefore, the correction data (actual L'71) written in the memory 40 in FIG. 8 is written in the remaining memories 41 to 45 as the correction data (s line). This operation is performed using, for example, CPtJ.

Next, the CPU operation will be explained. Control panel 12, same data writing operation section 39, number of scanning lines/frequency detection section 37, number of adjustment points/coefficient setting section 34 shown in FIG.
The operation can be performed by CPU processing. Control panel 12 key discrimination and same data writing scanning section 39
address control and data transfer, the scanning line/frequency detection section and the adjustment point/coefficient setting section 3 described in the first embodiment.
7 is also capable of arithmetic processing. These processes are performed by V-BLK
Since it is done during a period, there is no problem on the screen.

As described above, according to this embodiment, by writing the same correction data to n storage means at the same time, it is only necessary to input the correction data to n storage means, that is, to make adjustments once, thereby shortening the adjustment time. can be shortened. In addition, even when making fine adjustments, the amount of change in the correction data may be small, so
Adjustment time can be significantly shortened.

9 to 11 show a third embodiment of the present invention. The first difference from the configuration of the embodiment is that two memories are used to perform time-series processing for interpolating between adjustment points in the vertical direction. In FIG. 9, 46 and 47 are first and second memories for interpolating between adjustment points in the vertical direction, and 48 is a vertical calculation section for interpolating between adjustment points in the vertical direction. . In FIG. 4, components that perform the same operations as those in the first embodiment are designated by the same numbers and their explanations will be omitted.

In order to explain the digital convergence device of this embodiment in detail, the block diagram of FIG. 10 and the display screen diagram of FIG. 11 will be used. The correction data at the adjustment point A in the display screen diagram shown in FIG. 11 from the frame memory 10 is stored in the first memory 46.
The correction data for the adjustment point B in the figure is stored in the second memory 47. The vertical adjustment point correction data from the first and second memories 46 and 47 is sent to the vertical calculation unit 48.
The correction data corresponding to each scanning line between the adjustment points is calculated using the calculation data from the adjustment point number/coefficient setting section 34. The subsequent operation is the same as that in the first embodiment, so a description thereof will be omitted. By performing interpolation through time-series processing as described above, the calculation rate is lowered and the configuration is made compatible with signal sources having a high horizontal scanning frequency.

Next, the block diagram of FIG. 10 will be used to explain the vertical interpolation in detail. In FIG. 11, the amount of correction for each scanning line between A and B and between C and D can be obtained from the equation (A-B)+. Here, the value of K obtained by linear approximation is written into the coefficient generator 51. The address control unit 33 in FIG.
Data 1 in Figure O contains the correction data for the adjustment point C in Figure 11, and data 2 contains the correction data for the adjustment point C in Figure 11 in Figure 1.
- Each correction data is input to the second memory 46, 47 and stored therein. The data from the first and second memories 46 and 47 is subjected to the calculation (A-B) by the subtracter 48, and is input to the multiplier 49, where it is multiplied by the coefficient for each scanning line from the coefficient generator 51. (A-B) Find K and adder 50 (
A-B) K0A is calculated. As a result of the above calculation, interpolation between adjustment points C and D has been performed.

In addition, similar to the configuration described in Example 2, the number of scanning lines and frequency are detected and interpolation between adjustment points in the vertical direction is performed.
Since the O cutoff frequency is controlled, it is possible to deal with various signal sources.

As described above, according to this embodiment, by performing time series processing that interpolates between adjustment points in the vertical direction using two memories, the calculation rate is slowed down and the signal source with a high horizontal scanning frequency is This makes it possible to expand the range of support.

In the first to fourth embodiments, a projection type color receiver has been described for ease of understanding, but it goes without saying that the present invention is also effective for a shadow mask type direct view receiver.

Further, in the first to fourth embodiments, the calculation method using linear approximation was explained as the interpolation means, but other calculations may be performed using non-linear approximation.

Further, in the first and second embodiments, the case where the presence or absence of a signal is detected has been described, but the detection may also be used to detect the number of scanning lines or the horizontal scanning frequency.

Furthermore, in the third embodiment, the case where the CPU is used as the writing means for the same correction data has been explained.
Other methods may also be used.

Effects of the Invention As explained above, according to the present invention, by detecting the no-signal period and stopping the convergence operation using this detection signal, stable operation can be performed because incorrect correction data is not written. It becomes possible. Furthermore, when a detection signal or the like is used to switch the receiver's system, the receiver is forced to operate in a specific operating mode without causing any abnormal operation when there is no signal, so the receiver can always operate stably.

In addition, since correction data corresponding to the frequency and number of scanning lines is created for the synchronization signal, it can be used with various signal sources.

Furthermore, by controlling the interpolation between vertical adjustment points using the scanning line number detection signal and the address and LFP using the horizontal scanning frequency detection signal, it is possible to correspond to various different signal sources and expand the range of applications.

Furthermore, by writing the same correction data into n storage means at the same time, it is only necessary to input the correction data to the n storage means, that is, adjust it once, so that the adjustment time can be shortened. Further, even in the case of fine adjustment, the amount of change in the correction data may be small, so that the adjustment time can be significantly shortened.

Additionally, when performing interpolation between adjustment points in the vertical direction using two memories, by performing serial processing, the calculation rate is slowed down and it is possible to handle signal sources with high horizontal scanning frequencies, increasing the compatible range. can be expanded.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital convergence device according to an embodiment of the present invention, FIG. 2 is a display screen diagram for explaining the operation of the embodiment, and FIG. 3 is a block diagram of a detection means of the embodiment. FIG. 4 is an operational diagram of the same embodiment, FIG. 5 is a block diagram of a digital convergence device according to a second embodiment of the present invention, FIG. 6 is a display screen diagram for explaining the operation of the same embodiment, and FIG. 7 is an operation diagram of the embodiment, FIG. 8 is a detection data diagram of each memory of the embodiment, FIG. 9 is a block diagram of the digital convergence device of the third embodiment of the present invention, and FIG. FIG. 11 is a block diagram of the processing means between adjustment points in the vertical direction of the same embodiment. FIG. 11 is a display screen diagram for explaining the operation of the same embodiment. FIG. 12 is a block diagram of a conventional digital convergence device. The figure is a display screen diagram for explaining the operation of the device. 26...Scanning line number detection unit, 35...Horizontal scanning frequency detection unit, 36...Signal detection unit, 3
4...Adjustment point/coefficient setting section, 29...
・Vertical direction adjustment point processing unit, 10...Frame memory, 32...LPF, 6...Cross hand F-generation L 12...Control panel, 30...Deflection circuit, 57...C
PtJ section, 58... Frequency division counter, 59...
... Clock generator, 39 ... Same data write operation section, 38 ... n frame memories, 46 ... First memory, 47 ... . . . second memory, 48 . . . vertical direction calculation section, 51.
... Coefficient generator, 48 ... Subtractor, 49
...Multiplier, 50...Adder.

Claims (4)

[Claims] (1) means for generating and displaying a plurality of convergence adjustment points in the horizontal and vertical directions on the screen of a color television receiver; means for digitally storing convergence correction amounts for the adjustment points; means for detecting the presence or absence, frequency, and number of scanning lines of an input synchronizing signal; means for creating correction data corresponding to the frequency and number of scanning lines of the detection signal; and stopping the correction operation based on the no-signal detection signal. and means for forcing a receiver into a particular operating mode by means of the no-signal detection signal. (2) Claim (1) characterized in that the correction data creation means creates the correction data by controlling interpolation in the vertical direction depending on the number of scanning lines and smoothing in the horizontal direction depending on the frequency.
) Digital convergence device. (3) means for generating and displaying a plurality of convergence adjustment points in the horizontal and vertical directions on the screen of a color television receiver, and n storage means for digitally storing convergence correction amounts for the adjustment points; means for detecting the frequency and number of scanning lines input to the receiver, means for creating correction data corresponding to the frequency and number of scanning lines of the detection signal, and storing the same correction data in the n storage means. A digital convergence device comprising a writing means. (4) means for generating and displaying a plurality of convergence adjustment points in the horizontal and vertical directions on the screen of a color television receiver; and a first storage means for digitally storing convergence correction amounts for the adjustment points; means for interpolating between adjustment points in the vertical direction; and the interpolation means comprises a first memory that stores correction data for the first adjustment point and a second memory that stores correction data for the second adjustment point. A digital convergence device comprising means for creating correction data between adjustment points.