JPH1013762A - Wide screen television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wide image in which a sense of incongruity is less by configuring a read control signal with a count of different clocks in response to a position on a horizontal scanning line. SOLUTION: Let an extension rate of a picture element in the middle for each horizontal scanning line be 1 and picture elements are read and displayed so that the extension rate is continuously changed in the horizontal direction. A 1st adder section 1 adds a count X of clock signals and a prescribed constant (-b) for each horizontal scanning line and provides an output of a sum, and an absolute section 2 of a next stage generates and outputs an absolute value |X-b|. A multiplier section 3 receives the absolute value |X-b| and a prescribed constant (a) and provides an output of a|X-b≫. A 2nd adder section 4 receives the output a|X-b| and a prescribed constant (c) and adds them and provides an output of characteristic equation Y=c-a|X-b|. The characteristic equation is added to a 3rd adder section 5 as Y=ΔX, then an address K based on the count is obtained and the address K is fed to a memory section, from which picture elements are read to obtain an image whose extension rate is changed continuously in the horizontal direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television having a display screen with a wide aspect ratio (16: 9), and more particularly, to a circuit for expanding and displaying a picture in a non-linear manner in a horizontal direction.

[0002]

2. Description of the Related Art In recent years, a television receiver having an aspect ratio of 16: 9 (hereinafter referred to as a wide screen television).
Is becoming popular. In this wide screen TV,
For example, NTSC sent with an aspect ratio of 4: 3
(National Television System Committee) In the case of receiving and displaying a television broadcast of the system, for example, the center of the image is relatively shortened and the image is extended toward the periphery, so that the image is 16: 9.
Is used to display 4: 3 images with as little discomfort as possible.

FIG. 4 shows an example of a screen display when a crosshatch pattern signal, which is a 4: 3 image, is displayed on a display screen having an aspect ratio of 16: 9.

In FIG. 4, (a) shows a mode in which a 16: 9 video signal is displayed, and a 4: 3 video signal is entirely extended in the horizontal direction and displayed. (B) is a mode in which the 4: 3 video signal is displayed as it is, and the 4: 3 video signal is displayed with a correct aspect ratio. However, blank portions without signals are displayed on the left and right sides of the screen.
(C) is a mode in which the central portion of the screen is relatively expanded and displayed as it approaches the periphery, and the most important central portion does not become a horizontally elongated image and is relatively important. The low-periphery peripheral portion extends horizontally and is displayed so as to fill the entire 16: 9 screen, so that even a 4: 3 television broadcast can utilize the entire wide screen.

As is well known, in a television using a CRT (cathode ray tube), the movement amount (deflection speed) of the electron beam on the phosphor screen of the CRT is larger in the peripheral portion than in the central portion, so that the amount of deflection in the peripheral portion is reduced. The so-called S-shape correction is performed on the horizontal deflection current so as to reduce it compared with the central portion. Therefore, by using the S-shaped correction, the correction amount is switched to a required value, thereby realizing the screen display mode for a wide screen shown in FIG. 4C.

When a digital display type PDP (plasma display panel), LCD (liquid crystal), or the like is used instead of the CRT as the display means, the screen display mode is changed using the S-character correction used in the CRT. Since no method is available, a new method for widening the image has been required.

FIG. 3 is a basic block diagram of a circuit using a memory for expanding an image by digital signal processing.
The AD converter 31 converts a video signal having an aspect ratio of 4: 3 into a digital signal, and sequentially writes and stores the digital signal in the memory 32. On the other hand, digital signals are sequentially read out from the memory unit 32 by a required read control signal, and the DA converter 33 converts the digital signal into an analog video signal, supplies it to a display unit (not shown), and displays it. The memory control unit 34 supplies a required read control signal and the like to the memory unit 32. For example, as the read control signal, the pixel is read at a required timing such that the mode of FIG. 4A can be realized by adjusting the timing of the read address to the display of 16: 9. To extend the pixels horizontally,
Each mode of FIG. 4 can be realized.

The read control signal will be specifically described below. FIG. 5 is a block diagram (a) showing an embodiment of a basic circuit for generating an address for reading a pixel from a memory, and a diagram showing examples (b) and (c) of a read address. As shown in the block diagram of FIG.
The initial value ΔX expressed in bits and the carry-in 1 and the output expressed in 16 bits of the delay unit 52 are added to the adder 51.
The output represented by 16 bits from the adder 51 is supplied to the delay unit 52, the output represented by 16 bits of the delay unit 52 is supplied to the adder 51, and the upper 8 bits Is a read address. If this address is K, then K = 256 / (1 + ΔX).

In the example of the address shown in FIG. 5B, when "11111111", that is, 255 in decimal, is supplied as the initial value .DELTA.X in FIG. In the second clock, the address consisting of the ninth bit or more is “0”, in the second clock, the address is “1” to which the carry-in 1 is added, and in the third clock, the initial value ΔX and the carry 1 and the address “1” of the output of the delay unit 52 are added, and the address is “2”, and a read address that increases by one for each clock, such as.

The example shown in FIG. 5C has an initial value Δ
When a decimal 127 (“01111111”) is supplied as X, the address is “0” for both the first clock and the second clock, and the third clock and the fourth clock Are both "1",
In the fifth clock and the sixth clock, both are “2”, and a read address that is incremented by one every two clocks, such as..., Is generated.

In the above-described first example, an address which is increased by one for each clock is generated. One pixel is read for each clock by using this address as a read signal. Therefore, for example, the stored image as shown in FIG. 4B can be displayed as it is.
In the second example, an address that increases by one every two clocks is generated. Therefore, by using this address as a read signal, one pixel is read every two clocks. Therefore, for example, as shown in FIG. 4A, an image obtained by expanding the stored image twice in the horizontal direction can be displayed.

As can be seen from the above example, FIG.
In order to realize the screen display mode in which the screen is wide as shown in FIG. 5, for example, in the block diagram of FIG. By switching to apply the second example described above, a wide screen can be realized. However, in the method of switching the initial value ΔX, the state of image expansion changes abruptly at the switching point, so that an unnatural feeling occurs in the image.

Therefore, as a condition for obtaining a wide screen with less discomfort as shown in FIG. 4 (c), continuous expansion is performed by continuously changing the initial value ΔX little by little. It needs to be changed. For example, the characteristic of the image expansion rate in the horizontal scanning line direction is 1 at the center of the horizontal scanning line, and 2
With the following curve, the above condition can be satisfied. In order to realize such a quadratic curve characteristic of the elongation rate, a value based on the quadratic curve is supplied to the initial value ΔX. By doing this,
Since the extension near the center of the screen is small and the extension ratio on the left and right peripheral portions is large and the extension ratio continuously changes over the entire screen, an image as shown in FIG. 4C can be obtained. .

However, in general, in order to provide the characteristic of the elongation rate by a quadratic curve, the count value of a different clock corresponding to the position of the horizontal scanning line becomes a quadratic function as an initial value of the above equation. And for example, K = 256 /
(1 + ΔX) = a (x−b) (x−b) + c and Δ
By solving this equation for X, ΔX = 256 / ｛a (x−
b) The function of (x−b) + c｝ −1 is given as the initial value ΔX. However, in order to realize ΔX, at least two multiplication circuits and one division circuit are required as digital signal processing circuits. In general,
In order to realize the multiplication circuit and the division circuit with the required accuracy, the circuit becomes a large-scale circuit in which the number of operation bits is doubled for each operation, and thus there is a problem of cost increase.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and provides a memory read control circuit for realizing a wide-screen television such as a PDP capable of obtaining a wide image with little discomfort. The purpose is to:

[0016]

To achieve the above object, an A / D converter for converting a video signal into a digital signal,
A memory unit for sequentially writing and storing the digital signal in accordance with a required write control signal and sequentially reading in accordance with a required read control signal, a DA converter for converting a digital signal into an analog video signal, and a required write control signal and read control signal And a memory control unit that supplies a digital signal from the memory unit to the memory unit using a read control signal generated by the memory control unit. , And the pixels are read out based on the count values.

Further, the memory control unit generates a first adder for adding a count value obtained by counting clock signals for each horizontal scanning line and a required constant, and an absolute value of an output of the first adder. An absolute value part, a multiplying part for multiplying the absolute value by inputting a required constant to the other input to one input, and adding the output of the multiplying part to one input and a required constant to the other input A second adding unit, a third adding unit that adds the current output of the second adding unit and a one-clock delayed output of the addition result, and a delay unit that delays the output of the third adding unit by one clock. When a pixel is read by supplying a required count value output from the delay unit to the memory unit and reading out a pixel, the count value is decreased in the left-right direction with respect to a center point on a horizontal scanning line as a symmetric center. It has a substantially convex characteristic.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS With the above-described configuration, 1
In an image which is displayed so as to fill the entire screen of 6: 9, the expansion ratio of the pixel at the center is 1 for each horizontal scanning line, the expansion ratio at the left and right peripheral portions is, for example, twice, and the expansion ratio is horizontal. Since the pixels are read out and displayed so as to change continuously in the direction, a wide screen with less discomfort can be realized.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A wide screen television according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a circuit for generating a control signal for reading pixels from a memory of a wide-screen television according to the present invention.
1 is the number of clock signals X for each horizontal scanning line and the required constant (−
b), 2 is an absolute value section for generating an absolute value of the output of the first adding section 1, and 3 is an absolute value | X-b Is a multiplication unit that multiplies | by inputting a required constant a to the other input. 4 is a second addition for generating a count value Y of the clock signal by adding the output a | Xb | of the multiplier 3 to one input (negative) and inputting the required constant c to the other input. Department. 5
Is the current output of the second adder 4 (Y = ca | X-
b |) and a one-clock delayed output of the addition result, and a third adder 6 delays the output of the third adder 5 by one clock in synchronization with a clock signal,
This is a delay unit that outputs a memory read address.

The operation of generating a control signal for a wide-screen television according to the present invention will be described with reference to FIGS. FIG.
Are the display (a), the relationship between the number of clocks and the count value (b), (c), (d), the horizontal position and the expansion of pixels when generating a read control signal for a wide screen television according to the present invention. It is an image figure showing relation (e) with a rate. FIG. 2A shows a display screen (display).
(B) shows a characteristic graph of the clock and the count value when the display clock is taken on the horizontal axis X and the count value of the same clock is taken on the vertical axis Y. The characteristic formula is Y = aX, Shows the linear characteristic that rises to the right.

The characteristics of the clock and the count value shown in (c) of FIG. 2 include a characteristic having the screen center point b (break point) as the axis of symmetry, and having the above-mentioned upward slope a from the center point to the right end of the screen. This is a characteristic having a symmetrical right-down slope (-a) on the symmetry axis, and the characteristic expression is Y = a | X-b |. The characteristic of the clock and the count value shown in FIG. 4D is obtained by multiplying the characteristic of FIG. 2C by (−1) and moving in parallel by a positive constant C. It shows a substantially convex characteristic that decreases in the left-right direction with the point as the center of symmetry. The characteristic equation is Y = ca | Xb |.

The count value (Y) in the above-mentioned characteristic equation is made to correspond to the initial value in FIG. 5 (a) for generating a read address. Assuming that Y = ΔX, K = 256 / (1 + Δ) in the above equation.
When the count value (Y) obtained by the equation is substituted into ΔX of X), the address K becomes K = 256 / (c + 1−a | X−b)
|) And K = B / (A− | X−b |)... However, B = 256 / a and A = (c + 1) / a. In the graph of FIG. 2E, the clock count value is small in the left and right portions of the display screen shown in FIG. When the pixel is read out from the memory based on the K obtained by using the count value of the above-mentioned characteristic expression as an initial value such that the count value becomes approximately 1 as an initial value, the displayed pixels are on the left and right sides of the display screen. In the middle part, the elongation characteristic changes such that the elongation rate changes as it is and the elongation rate changes continuously.

By reading the pixel from the memory at the address K obtained by giving the count value (Y) indicated by the above-mentioned characteristic equation to the third adder 5 in FIG.
As shown in the graph of (e), a substantially concave, non-linearly changed elongation characteristic is obtained in which the center point on the horizontal scanning line is symmetrical and minimized, for example, is set to a value of 1, and increases in the left-right direction. Therefore, the smooth pixel expansion, which had to be conventionally applied with the quadratic curve characteristic, is replaced by the characteristic equation Y = c−
can be realized by applying a | X-b |.

The operation of the circuit shown in the block diagram of FIG. 1 will be described. The first adder 1 adds a count value X obtained by counting clock signals for each horizontal scanning line and a required constant (−b), and outputs the result to the above-mentioned characteristic formula Y = ca | X−b | · The expression (Xb) inside the absolute value symbol of... Is output, and the absolute value part 2 at the next stage generates and outputs the absolute value | Xb | of the output (Xb). The multiplication unit 3 inputs the absolute value | X to one input.
−b | is multiplied by inputting a required constant a to the other input;
The a | Xb | portion of the characteristic equation is output. The second adder 4 applies one output (negative) to the output a | X−
By adding the required constant c to the other input and adding the same, the characteristic formula Y = ca | Xb |... is generated and output.

The third adding unit 5 and the delay unit 6
This corresponds to a block diagram of a basic circuit that generates an address based on the count value shown in (a). By supplying the above-mentioned characteristic equation to the third adding unit 5 assuming that Y = ΔX, an address based on the K, in other words, the count value is obtained.

By supplying this K to the memory unit and reading out the pixels, an image as shown in FIG. 4C is obtained. In addition to the method of giving K to a memory address,
The same effect can be obtained by supplying the read permission signal to the memory. Although the above description has been made in the horizontal direction, the present invention is not limited to the horizontal direction, and a similar method can be applied in the vertical direction. By extending in the vertical direction, for example, captions and the like displayed outside the screen can be displayed.

[0027]

As described above, the present invention provides a memory readout control circuit for realizing a wide-screen television such as a PDP, which can obtain a wide image with less discomfort. Since the decompression process can be performed without using a divider, there is an advantage that it can be realized with a simple circuit having a small circuit scale.

By changing each of the constants a, b, and c of the possible characteristic equation Y = ca | Xb |..., The expansion ratio of the image can be easily changed. There is a merit that adjustment and optimization of can be easily performed. It can also be used for vertical extension.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a circuit for generating a control signal for reading a pixel from a memory of a wide screen television according to the present invention.

FIG. 2 shows the relationship between the display (a), the number of clocks and their counts (b), (c), (d), and the horizontal position when generating a read control signal for a wide screen television according to the present invention. FIG. 7 is an image diagram showing a relationship (e) with a pixel expansion rate.

FIG. 3 is a basic block diagram of a circuit using a memory for expanding an image by digital signal processing.

FIG. 4 shows a 4: 4 aspect ratio display screen.
FIG. 14 is a diagram illustrating a screen display example when a cross hatch pattern signal as the image of No. 3 is displayed.

FIGS. 5A and 5B are a block diagram showing an embodiment of a basic circuit for generating an address for reading a pixel from a memory, and diagrams showing examples of read addresses (B) and (C).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st addition part 2 Absolute value part 3 Multiplication part 4 2nd addition part 5 3rd addition part 6 Delay part 31 AD conversion part 32 Memory part 33 DA conversion part 34 Memory control part

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication H04N 5/66 H04N 5/66 D 7/01 7/01 G (72) Inventor Hidetoshi Ota Kawasaki-shi 1116 Suenaga, Takatsu-ku Within Fujitsu General Limited

Claims (6)

[Claims] An AD converter for converting a video signal into a digital signal.
A conversion unit, a memory unit for sequentially writing and storing the digital signal with a required write control signal and sequentially reading the digital signal with a required read control signal, a DA conversion unit for converting the digital signal into an analog video signal, and a required write control signal And a memory control unit that supplies a read control signal to the memory unit. When reading a digital signal from the memory unit using a read control signal generated by the memory control unit, the read control signal is horizontally A wide-screen television comprising count values of different clocks corresponding to positions on a scanning line, and reading out pixels based on the count values. 2. The wide-screen television according to claim 1, wherein the count value of the clock is changed non-linearly. 3. The wide-screen television according to claim 1, wherein the count value of the clock has a substantially convex characteristic that decreases in the left-right direction with respect to a center point on a horizontal scanning line as a center of symmetry. 4. The wide-screen television according to claim 2, wherein the count value of the clock is substantially 1 at the center on the horizontal scanning line. 5. A memory control unit comprising: a first adder for adding a count value obtained by counting clock signals for each horizontal scanning line and a required constant; and an absolute value of an output of the first adder. An absolute value part, a multiplier that inputs the absolute value to one input and multiplies the other input by a required constant, and inputs a required constant to one input and the output of the multiplier to the other input. A second adding section for adding, a third adding section for adding a current output of the second adding section and a one-clock delayed output of the addition result, and a delay section for delaying an output of the third adding section by one clock. When a required count value output from the delay unit is supplied to the memory unit and pixels are read out, the count value decreases in the horizontal direction with respect to a center point on a horizontal scanning line as a symmetric center. The wide-screen television according to claim 1, wherein the wide-screen television has a substantially convex characteristic. 6. The wide-screen television according to claim 1, wherein a required count value output from said delay section is supplied to a memory of a memory section as a read permission signal.