KR100296276B1 - Digital convergence circuit - Google Patents

Abstract

PURPOSE: A digital convergence circuit is provided to optimize the capacity of a memory by interpolating convergence correction data, inserting a line between scanning lines, and adjusting a convergent correction rate in real time. CONSTITUTION: A digital convergence circuit comprises a clock generating unit(1) for generating a clock corresponding to on a horizontal blanking signal, an address generating unit(2) for generating an address by detecting a vertical blanking signal corresponding to the clock, a memory(3) for outputting convergence correction data corresponding to the address, a signal interpolating unit(10) for interpolating the convergence correction data of the memory, a signal processing unit(4) for converting RGB(Red, Green, and Blue) signals into parallel data, a digital/analog converting unit(5) for converting the output of the signal processing unit into analog signals, a low band pass filter(6) for waveform shaping the output of the digital/analog converting unit after removing high band elements, a deflection unit(7) for amplifying the output of the low band pass filter and outputting the amplified output to a yoke coil(CY), and a central processing unit(8) for outputting convergence correction data by operating the convergence adjusting point data and correcting the prior convergence correction data.

Description

Digital convergence circuit

1 is a block diagram of a conventional digital convergence circuit.

2 is a block diagram of a digital convergence circuit, which is an embodiment of the invention.

3 is an exemplary view showing a configuration state of a memory in FIG.

4 is a detailed block diagram of a signal interpolation unit in FIG.

* Explanation of symbols for main parts of the drawings

1: Clock generator 2: Address generator

3: memory 4: signal processor

5: Digital / Analog Converter 6: Low Pass Filter

7: deflection portion 8: central processing unit

9: ROM 10: Signal Interpolator

11: adder 12: signal switching unit

CY: Yoke Coil

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital convergence, and more particularly, to a digital convergence circuit that improves the screen resolution by processing convergence correction data in real time by optimizing memory capacity in a TV.

Conventionally, as shown in FIG. 1, the digital convergence circuit includes a clock generator 1 for detecting the horizontal blanking signal HBLK and generating a reference clock CLK. An address generator 2 for generating an address Addr by calculating the vertical blanking signal VBLK on the basis of the output CLK, and outputting correction data in accordance with the output Addr of the address generator 2; A signal processor (4) for processing the memory (3) and correction data of the memory (3), separating the algibi signals (R, G, and B), converting them into parallel data, and outputting the parallel data; The digital / analog converter 5 for converting the output of the analog signal to analog, the low pass filter 6 for removing the high pass component from the output of the digital / analog converter 5 and shaping the waveform, and the low pass filter ( A deflection section 7 for amplifying the output of 6) by a predetermined level and outputting it to the yoke coil CY, and according to key selection. It consists of a central processing unit (8) for performing the control program of the La ROM (9) to modify the convergence correction data and to store in the memory (3), the clock generator 1 has a built-in PLL circuit It is composed.

Referring to the operation of the conventional circuit as follows.

Based on the horizontal blanking signal HBLK, the clock generator 1 generates a reference clock CLK necessary for digital convergence correction for improving the resolution of the screen, and based on the clock CLK, the vertical blanking signal VBLK. ), The address generator 2 generates a horizontal address for reading the correction data, and generates a vertical address for accessing the correction data.

At this time, when the memory 3 outputs the correction data stored in accordance with the output Addr of the address generator 2, the signal processor 4 separates the algibi signals R, G, and B and performs serial data. The data is converted into parallel data and output to the digital / analog converter 5.

Accordingly, when the digital / analog converter 5 performs analog conversion on the correction data output from the signal processor 4, the low pass filter 6 inputs the analog correction data which is the output of the digital / analog converter 5. After receiving a predetermined high frequency component, the waveform is shaped and output to the deflection section 7.

Therefore, when the deflection unit 7 amplifies the output of the low pass filter 6 by a predetermined level and outputs it to the yoke coil CY, a correction magnetic field is formed as a current flows in the yoke coil CY, thereby providing a path for the electron beam. Will change to correct the screen resolution.

Then, when the user selects a specific key to correct the convergence correction data, the central processing unit 8 executes the control program of the ROM 9 to recalculate the correction data and calculate the convergence correction calculated by the calculation. The data is stored in the memory 3.

Accordingly, the convergence is adjusted by using the modified convergence correction data of the memory 3.

However, in the related art, as the TV becomes higher and larger in size, the memory capacity increases and the data volume increases, making it difficult to process the convergence correction data in real time, thereby reducing the resolution of the screen.

Therefore, the present invention improves the resolution of the screen by performing line convergence in real time by interpolating the convergence correction data to solve the conventional problems, and also by processing line convergence in real time. It is an object of the present invention to provide a digital convergence circuit designed to optimize memory capacity.

The present invention interpolates the convergence correction data output from the memory (3) by inserting a signal interpolator (10) between the memory (3) and the signal processor (4) to achieve the above object. (4) is configured to achieve real-time convergence correction and memory capacity optimization.

Hereinafter, described in detail with reference to the accompanying drawings of the present invention.

2 is a block diagram of a digital convergence circuit according to an embodiment of the present invention. As shown therein, a clock generator 1 for generating a clock CLK based on a horizontal blanking signal HBLK, and the clock generation The address generator 2 detects the vertical blanking signal VBLK on the basis of the output CLK of the unit 1 to generate an address Addr, and according to the output Addr of the address generator 2 In the memory 3 for outputting the convergence correction data, the signal interpolation unit 10 for interpolating the convergence correction data in the memory 3, and the output of this myth interpolation unit 10, A signal processor 4 for separating the RB signals R, G, and B into parallel data, a digital / analog converter 5 for converting the output of the signal processor 4 into analog, and this digital signal; A low pass filter 6 for removing the high frequency component from the output of the analog converter 5 and shaping the waveform; A deflection section 7 for amplifying the output of the low pass filter 6 by a predetermined level and outputting it to the yoke coil CY, and when the convergence adjustment point is changed by the user's key input, the convergence adjustment stored in the ROM 9 Comprising a central processing unit (8) that calculates the convergence correction data by calculating the point data, and stores the calculated convergence correction data in the memory (3) to correct the previous convergence correction data, The clock generator 1 is constructed by incorporating a PLL circuit.

As shown in FIG. 4, the signal interpolator 10 includes an adder 11 that sums and averages convergence correction data A _n and A _{(n + 1)} , and the convergence correction data. And a signal switching section 12 for selectively outputting (A _n ) and the output ((A _n + A _{(n + 1)} ) / 2) of the adder 11.

The operation and the effect of the embodiment of the present invention configured as described above will be described in detail with reference to FIG.

Based on the horizontal blanking signal HBLK, the clock generator 1 generates a reference clock CLK necessary for digital convergence correction for improving the resolution of the screen, and based on the clock CLK, the vertical blanking signal VBLK. ), The address generator 2 generates a horizontal address for reading the correction data, and generates a vertical address for accessing the correction data.

At this time, when the memory 3 outputs the correction data stored in accordance with the output Addr of the address generator 2, the signal interpolator 10 interpolates the correction data to scan line lines of the correction data. Scan lines of different pixel values are inserted in between.

Here, the memory 3 is the third help gatneunde the same map (MAP) _{configuration, A 00, A 02, A} 04, A 06, A 08, ‥‥‥‥ ( Ibn first line in the first row), A _20, A ₂₂ , A ₂₄ , A ₂₆ , A ₂₈ , ‥‥‥‥ (second even line in column 3) ‥‥‥‥ (n-th even line in column 2n) and the data sent to the actual scan line is interpolated. Will be sent.

When the input data is inputted as A _n , A _{(n + 1)} , the signal interpolator 10 adds the sums by the adder 11 and averages them by 1/2 to output an average value equal to the original value and the number of digits. Data that does not require calculation is printed as is.

To explain this operation in detail, the first line is A ₀₀ , (A ₀₀ + A ₀₂ ) / 2, A ₀₂ , (A ₀₂ + A ₀₄ ) / 2, A ₀₄ , (A ₀₄ + A ₀₆ ) / 2, A ₀₆ , (A ₀₆ + A ₀₈ ) / 2, A ₀₈ , ‥‥, second line (odd) is A ₀₀ , (A ₀₀ + A ₂₀ ) / 2, (A ₀₀ + A ₂₂ ) / 2, (A ₀₂ + A ₂₄ ) / 2, (A ₂₂ + A ₀₄ ) / 2 (= (A ₀₂ + A ₂₄ ) / 2), (A ₀₄ + A ₂₄ ) / 2, (A ₀₄ + A ₂₆ ) / 2 (= (A ₂₄ + A ₀₆ ) / 2), (A ₀₆ + A ₂₆ ) / 2, (A ₀₆ + A ₂₈ ) / 2 (= (A ₂₆ + A ₀₈ ) / 2, (A ₀₈ + A ₂₈ ) / 2, ‥‥, the third line (even) is A ₂₀ , (A ₂₀ + A ₂₂ ) / 2, A ₂₂ , (A ₂₂ + A ₂₄ ) / 2, A ₂₄ , (A ₂₄ + A ₂₆ ), 2, A ₂₆ , (A ₂₆ + A ₂₈ ), an address is generated to read and write data stored in the memory 3 to operate as (2 ₂₆ , A ₂₈ , ...), and the data of the memory 3 is read. An interpolation operation is performed to achieve the line value.

Therefore, when the signal interpolator 10 interpolates and outputs the convergence correction data, the signal processor 4 processes the output of the signal interpolator 10 to separate the algibi signals R, G, and B. In addition, the serial data is converted into parallel data and then output to the digital / analog converter 5.

Accordingly, the digital / analog converter 5 converts the correction data output from the signal processor 4 and the low pass filter 6 receives the analog correction data which is the output of the digital / analog converter 5. After removing the predetermined high frequency component, the waveform is shaped and output to the deflection unit 7. The deflection unit 7 amplifies the output of the low pass filter 6 by a predetermined level and outputs it to the yoke coil CY.

Therefore, the correction magnetic field is formed as the current flows in the yoke coil CY, so that the path of the electron beam is changed to correct the screen resolution.

Then, when the user changes the convergence adjustment point with a key input to correct the convergence correction data, the central processing unit 8 executes the control program stored in the ROM 9 and the cone stored in the ROM 9. The convergence correction data is calculated by calculating the convergence correction point data, and the calculated convergence correction data is stored in the memory 3 to correct the previous convergence correction data.

Accordingly, the convergence is adjusted by using the modified convergence correction data stored in the memory 3.

As described in detail above, the present invention can perform convergence correction in real time by interpolating convergence correction data and inserting a line between scan lines, thereby reducing the amount of stored data and thereby reducing memory. This has the effect of optimizing the dose.

Claims (2)

A clock generating means for generating a clock CLK with respect to the horizontal blanking signal HBLK, and an address for generating an address Addr by detecting a vertical blanking signal VBLK with respect to the output CLK of the clock generating means. Interpolation between the generating means, the data storing means for outputting the convergence correction data in accordance with the output Addr of the address generating means, and the average pixel value between lines by interpolating the convergence correction data in the data storing means. A signal interpolation means for inserting a line having a signal, a signal processing means for separating the R-G signals (R, G, B) from the output of the signal interpolation means, and converting them into parallel data; Digital / analog converting means for converting, a low pass filter for shaping a waveform after removing high frequency components from the output of the digital / analog converting means, and outputting the low pass filter Deflection means for amplifying a predetermined level and outputting the result to the yoke coil CY, and controlling convergence correction operation, calculating convergence adjustment point data stored in a ROM according to a change of a user's adjustment point. And a central processing unit which calculates correction data and stores the calculated convergence correction data in the data storage means to correct previous convergence correction data. 2. The signal interpolation means according to claim 1, wherein the signal interpolation means includes an adder (11) that sums and averages convergence correction data (A _n , A _{(n + 1)} ) in the data storage means, and the convergence correction data (A ₎ . _n ) and a signal switching section (12) for selectively outputting the output ((A _n + A _{(n + 1)} ) / 2) of the adder (11).