KR100196695B1 - Digital convergence compensation apparatus and method thereof - Google Patents

Abstract

The present invention provides a convergence correction device and a version for correcting image distortion due to different angles of incidence on a screen in a color TV, especially a projection TV using three RGB CRTs. It is about a correction method.

A conventional digital convergence correction device reads the complementary data in memory using an address synchronized with a synchronous signal, converts the correction data into an analog waveform using a D / A converter, and then shapes the waveform with a low pass filter. It is a technique of changing the correction data of the memory by operating the central iron device while obtaining the convergence boss waveform and adjusting the test pattern during the adjustment. There are problems such as difficulty in adjustment and deterioration in the accuracy of convergence adjustment.

According to the present invention, by adjusting a horizontal or vertical section to be adjusted by using a sub cursor, there is no influence of other positions where the adjustment has already been completed, and also when performing curve interpolation for the entire screen in the adjusted state. The adjustment can be made by higher-order interpolation to eliminate changes in the screen, to reduce the adjustment time by reducing the number of adjustments, and to make extrapolation adjustments to improve the convergence accuracy of the peripheral area as well as to adjust the adjustment range of the subcus. It is possible to precisely adjust the convergence even for difficult-to-adjust blocks by storing them in a separate operation process for this adjustment section and to secure effects such as block adjustment by simultaneously generating horizontal and vertical cursors.

Description

Method of digital convergence correction device

The present invention provides a convergence correction device and a convergence correction device for correcting image distortion due to different angles of incidence of a screen in a color TV, especially a projection TV using three RGB CRTs. The present invention relates to a correction method, and more particularly, to a digital convergence correction device and method for performing convergence adjustment by setting a horizontal or vertical section to be adjusted as a sub-cursor.

Conventional digital convergence correction apparatus performs convergence correction using a central processing unit (CPU), a memory, a test pattern generator, an address generator, a D / A converter, a low pass filter, and the like. Read the calibration data in memory, convert the calibration data into an analog waveform using a D / A converter, and then shape the waveform with a lowpass filter to obtain a convergence correction waveform. As a technique of changing the correction data in the memory by the operation of the central processing unit, various examples of such a conventional digital convergence correction apparatus are shown in FIGS.

Here, the method of creating correction data inside the screen is called interpolation, and the method of creating correction data outside the screen is called extrapolation.

1 is a circuit diagram showing a first example of a conventional digital convergence correction apparatus. Referring to the configuration, the write address control unit 101 and the read address control unit 102 which generate addresses for writing and outputting data, respectively, A write signal and a read address to select a frame memory 104, a dot signal generator 105 generating a dot signal under the control of the read address control unit 102, and outputting the generated dot signal A control panel panel 107 for inputting an operation signal, a data reversible counter 108 between the control panel panel 107, the one-frame memory 104 and the register 109, and the one-frame memory A register 109 that stores the output of 104, a vertical interpolation processor 110 that performs interpolation in the vertical direction by inputting the data output from the register 109, and the interpolated data To a D / A converter 111 for converting a signal into an analog signal, a low pass filter 112 for waveform shaping the analog signal, and an output of the low pass filter 112 to be supplied to the convergence yoke 114. The amplifier 113 and a convergence yoke 114 to which a signal of the amplified correction waveform is applied.

The correction operation according to the first example of the conventional digital convergence correction device configured as described above is as follows.

The write and read addresses generated by the write address control unit 101 and the read address control unit 102 are selectively supplied to the one frame memory 104 through the multiplexer 103 so that the control points store data and output the data. .

Under the control of the read address controller 102, a dot signal is generated by the dot signal generator 105 and output through the image circuit 106.

By the operation of the control panel 107, the multiplexer 103 is operated to read or change the contents of the one-frame memory 104, and only to read in the normal mode.

The data reversible counter 108 is operated by the operation of the control panel 107, and the adjustment point correction data read out from the one-frame memory 104 is vertical through the register 109 under the control of the read address control unit 102. It is supplied to the direction interpolation processing unit 110, and the linear interpolation equation ((BA) / n * K + A, n is the number of lines between A and B, A and B is the adjustment point, K Is an integer 0, 1, 2, ..., n)].

Here, the value of K is stored in advance in the ROM, and the above calculation is performed to obtain the correction data of the entire screen, and the correction data is converted into the analog correction waveform by the D / A converter 111 and then converted to the low range. It is applied to the convergence yoke 114 via the pass filter 112 and the amplifier 113.

In the first example of such a conventional digital convergence correction device, it is very difficult for the interpolation section (interpolation calculation section) to perform curve interpolation circuitally, and thus, most of the time, linear interpolation is performed.

Therefore, as shown in FIG. 6, an inconsistency between scanning line intervals in which bright and black blocks appear on the screen is generated, and memory data can be reduced because only data of adjustment points are stored, but a separate interpolation circuit is provided. As a result, most of the current trends are to remove the interpolation unit and perform interpolation of the curves in the CPU.

In addition, in order to obtain correction data outside the screen (overscan portion), as shown in FIG. 10, the convergence between the Z point and the A point can be improved, but there is a fear that the convergence between the G and X points may be released. However, forcibly converting the correction data at the X, Y, and Z points to the A point data in synchronization with the horizontal blanking signal is a bad method for convergence correction and image quality improvement because it ignores the delay caused by the digital convergence system.

2 shows a second example of a conventional digital convergence correction device.

Referring to the configuration of the arc of FIG. 2, the control panel 200 for the operation, the data reversible counter 201 operating under the control of the control panel 200, and the count value of the data reversible counter 201 are set to 1. The multiplexer 202 supplied to the frame memory 203, the one-frame memory 203 for storing correction data by the output of the multiplexer 202, and the extrapolation of the memory output are calculated and input to the multiplexer 202. An extrapolation calculation circuit 204, a 1H register 205 connected to the data reversible counter 201 for storing 1H data, and a subtraction circuit for subtracting the output of the 1H register 205 and the data reversible counter output ( 206, a multiplication circuit 207 for multiplying the output of the subtraction circuit 206 by the count value of the coefficient 208, a coefficient 208 for supplying a coefficient value to the multiplication circuit 207, The output of the multiplication circuit 207 and the data reversible counter output An addition circuit 209 for adding an output, a D / A converter 210 for converting an output of the addition circuit 209 into an analog signal, and an output of the D / A converter 210 to an image amplifier. It consists of a low pass filter (211).

In the second example of the conventional convergence correction device configured as described above, the extrapolation calculation circuit 204 is set aside, and the correction data of the X, Y, and Z points is linearly interpolated using the correction data of the G and A points in FIG. Is an example characterized in that is obtained and stored in the one-frame memory 203.

In this circuit, the data reversible counter 201 is operated by the operation of the control panel 200 and the extrapolated correction data is stored in the extrapolation calculation circuit 204 in the one frame memory 203 through the multiplexer 202. The 1H register 205 stores correction data of 1H and inputs it to the subtraction circuit 206. The subtraction circuit 206 subtracts this data from the output value of the data reversible counter 201 and inputs the multiplication circuit 207. do.

The multiplication circuit 207 multiplies the count value of the coefficient 208 with the output of the subtraction circuit 206 and inputs it to the addition circuit 209, which adds the data value of the data reversible counter 201. And the output of the multiplication circuit 207 is added, and this added value is converted into an analog signal through the D / A converter 210, and then amplified by the amplification unit through the low pass filter 211 to the convergence yoke. It is a technology to supply.

However, since the second example of such a conventional digital convergence correction device requires a separate extrapolation calculation unit 204, and this data is obtained by linear interpolation using neighboring adjustment points, it exhibits sufficient capability necessary for convergence correction. It's a technology you can't.

FIG. 3 is a circuit diagram showing a third example of a conventional digital convergence correction device, including an address encoder 300 for inputting a synchronization signal, a keyboard 301 for moving an adjustment point cursor, and a keyboard command in the center. A buffer 302 input to the processing unit (CPU) 303, a central processing unit 303 for controlling adjustment point data creation in response to a command input through the buffer 3020, and the central processing unit 303 Control of the address encoder 300 to select the address of the address encoder 300 or the output of the central processing unit, and the output of the address control switch 304 is inputted to the data of the data control switch 306. A memory 305 for storing or outputting, a data control switch for storing and outputting correction data in the memory 305 under the control of the central processing unit 303, and the data control switch 306. An interpolation unit 307 for interpolating output data, a D / A converter 308 for converting the interpolated data into an analog signal, and a low pass filter for inputting the analog converted interpolation data to a convergence yoke via an amplification unit. 309, an I / O buffer 310 for inputting / outputting the control signal of the CPU 303 to the test pattern generator 311, and a test pattern generator for generating a test pattern by the buffer signal. 311, an I / O buffer 312 for inputting / outputting the control signal of the central processing unit 303 to the adjustment point generator 313, and an adjustment point generator for generating an adjustment point by the buffer signal. 313, a synthesis unit 314 for adding the test pattern and the control point signal to the image circuit unit, and a plurality of ROMs for storing data for correcting screen distortion and inputting the data to the central processing unit 303. (315).

In the third example of the conventional digital convergence correction device configured as described above, the central processing unit 303 corrects the adjustment point by receiving the command input through the cursor key and the up, down, left, and right arrow keys of the keyboard 301 through the buffer 302. Write the data.

That is, when the data ROM 315 is placed and there are portions (Bow, Shew, Pin Cusion, Size, etc.) that are distorted to a certain shape on the screen, the data ROM 315 is selected to correct the data ROM. Using the data and the data in the memory 305, the central processing unit 303 performs an addition and subtraction operation to generate correction data, and stores the data in the memory 305 to make adjustments.

In addition, the ROUGH MODE can be used to change the correction data of one control block simultaneously and proportionally.

The data storage and output of the memory 305 is performed by the switching operation of the address control switch 304 and the data control switch 306, and the memory output data is interpolated by the interpolator 307 and the D / A converter 308. The analog signal is converted into an analog signal and supplied to the converged yoke through the low pass filter 309 through the amplifier.

The test pattern and the adjustment point (cursor) generated by the test pattern generation unit 311 and the adjustment point generation unit 313 by the buffers 310 and 312 are synthesized by the synthesis unit 314 to be combined with the image circuit unit. By being supplied, the screen of the test pattern and the adjustment point is represented, and the adjustment point is moved to an appropriate position by the corresponding key operation of the keyboard 301.

However, in the third example of such a conventional digital convergence correcting apparatus, it is very difficult for the interpolation section (interpolation calculation section) to make the interpolation of the grain roots circuitally, and thus, most of the time, linear interpolation is performed.

Therefore, as shown in FIG. 6, an inconsistency between scanning line intervals in which bright and black blocks appear on the screen is generated, and memory data can be reduced because only data of adjustment points are stored, but a separate interpolation circuit is provided. There is an added disadvantage.

In addition, although the rough mode and the data ROM are set to shorten the adjustment time, a separate data ROM 315 is required, and in the rough adjustment mode, the correction data of one adjustment block is moved simultaneously and proportionally. As shown in the pattern pattern of unadjusted convergence, the size (length) of 'ga' point, 'e' point, or 'me', 'bar' point, etc. should be moved horizontally and vertically. Since they are different, moving them proportionately would only result in longer adjustments.

FIG. 4A is a circuit diagram showing a fourth example of a conventional digital convergence correction apparatus, which includes a keyboard 400, a central processing unit 401 in charge of controlling correction data creation according to a key command, and a central portion. A memory 402 in which the processing device is controlled to store and output correction data, a memory address counter 403, a D / A converter 404 for converting memory output data into an analog signal, and an amplifying unit for the analog signal. The low pass filter 405 supplied to the convergence yoke 406 through 406, and the amplification part 406 which amplifies the output of the low pass filter and supplies to the conversion yoke 407 are comprised.

In the fourth example of the conventional digital convergence correction device having such a configuration, as shown in FIGS. 4A and 4B, the memory 402 stores the full-screen correction data without providing an extra interpolation unit. In the case of adjustment (change of adjustment point data), the central processing unit 401 calculates the value between the adjustment point and the adjustment point by linear interpolation in order to improve the adjustment speed by receiving a control command of the keyboard 400. When there is no keyboard input (or adjustment completion), (n-1) difference curve interpolation is performed in the horizontal and vertical directions using the data of the adjustment point, and the calculated correction data is stored in the memory 402.

Where n represents the number of adjustment points.

The address of the memory 402 is supplied from the address counter 403, and the memory output data is converted into an analog signal through the D / A converter 404, and then the low pass filter 405 and the amplifier 406 are transferred. It is input to the convergence yoke 407 via this.

However, this conventional fourth example is shown as (a) in the form of change in adjustment as shown in FIG. 7 when the correction data of the other position at the time of adjustment is obtained by linear interpolation.

If the curve is interpolated, it is difficult to get the point (a) exactly because of the characteristics of the low pass filter, and the best way to do it is to have a gentle curve like the shape (b).

In addition, when interpolating the entire screen by the (n-1) -difference curve, if only one adjustment point is wrong, this effect causes the convergence of the other parts to be distorted, making adjustment difficult.

This is because it is difficult to distinguish which part should be adjusted when the convergence adjustment of a part is wrong and the convergence of the neighboring part is out of order, and the interpolation is continued while adjusting because it performs linear interpolation with little influence on the neighboring part. There is a disadvantage in that the convergence of neighboring parts should be checked.

The first, third, and fourth examples described above relate to a method (interpolation) for obtaining correction data in the screen in FIG. 10, and in the case of the first and second examples, extrapolation is considered. Corresponding.

The importance of extrapolation is that, as shown in Fig. 10, when there is no data of the X, Y, and Z points, the horizontal line between the Z point and the A point is difficult to become a straight line (because when the interpolation is performed in the horizontal direction, This is because the characteristics of the low pass filter, which do not allow for the abrupt change of the waveform], for this reason, the horizontal line between the Z and A points is not bent or adjusted well.

This violates the digital convergence, which is an advantage of precisely adjusting the periphery. To solve this problem, in the first example, the X, Y, and Z points after the correction data of the G points in the raster scan scan in FIG. In this case, data at point A is forced to be synchronized with the horizontal blanking signal.

As described above, the conventional digital convergence correction devices shown in Figs. 1 to 4 are affected by the parts which have already been adjusted, increase in the number of adjustments, difficulty in adjustment, or accuracy of convergence adjustment. It has a problem such as deterioration.

According to the present invention, by adjusting the horizontal or vertical section to be adjusted by using a sub cursor, there is no influence of other positions where the adjustment is already completed, and also when the curve interpolation is performed for the entire screen in the adjusted state. By adjusting the interpolation method, the screen eliminates the change, reduces the number of adjustments, thereby reducing the adjustment time, and enables extrapolation adjustments to improve the convergence accuracy of the periphery, as well as memorizing the adjustment range of the subcus. The digital convergence correction device and the digital convergence enable to achieve precise convergence adjustment even for blocks that are difficult to adjust by performing arithmetic processing for this adjustment section separately, and to secure effects such as block adjustment by simultaneously generating horizontal and vertical cursors. It is an object to provide a correction method.

1 is a circuit diagram showing a first drawing of a conventional digital convergence correction device.

2 is a circuit diagram showing a second example of a conventional digital convergence correction device.

3 is a circuit diagram showing a third example of a conventional digital convergence correction device.

FIG. 4A is a circuit diagram showing a fourth example of a conventional digital convergence correction device, and FIG. 4B is a flowchart showing an operation process of the conventional third example.

5 is a diagram showing the shape of the G test pattern when the convergence is not adjusted.

6 is a diagram showing scanning line spacing during linear interpolation and curve interpolation.

FIG. 7 is a diagram illustrating a centrally changing shape when adjusting linear interpolation and curve interpolation. FIG.

8 is a circuit diagram of an embodiment of a digital convergence correction device of the present invention.

9 is a diagram showing an example of the keyboard configuration of the digital convergence corrected autonomy of the present invention.

10 is a view showing an example of the Chinese character test pattern of the present invention.

11 is a flowchart of the digital convergence correction method of the present invention at power on.

12 is a flowchart of the present invention digital convergence correction method at interpolation.

Fig. 13 is a flowchart of the present invention digital convergence correction method at extrapolation.

The digital convergence correction device of the present invention, which achieves the above object, includes a memory in which correction data is stored and output, a test pattern generator for generating a test pattern by the memory and address generator, the address generator, A D / A converter that converts correction data output from the memory into an analog signal, a low pass filter that filters the output signal of the D / A converter and supplies it to the convergence yoke through an amplifying unit, and controls each component. A digital convergence correction device comprising: a central processing unit configured to perform arithmetic operation; and reading a memory content in synchronization with a synchronous signal and obtaining a convergence correction waveform through D / A conversion and low pass filtering. A cursor generator for generating a cursor (adjustment point) under control of the central processing unit A sub-cursor generation unit for generating a flat or vertical sub-cursor, a synthesis unit for synthesizing the test pattern and the cursor signals on a screen, and an input unit connected to a central processing unit to adjust the generation and position movement of the cursor The digital convergence correction device is characterized by obtaining other correction data by curve interpolating only a designated section designated by a horizontal or vertical sub-cursor during convergence adjustment.

8 shows a circuit configuration of an embodiment of the digital convergence correction device of the present invention which achieves the above object.

As shown in FIG. 8, the digital convergence correcting apparatus of the present invention comprises a central processing unit which performs cursor (adjustment point) and horizontal subcursor generation, vertical subcursor generation and correction data calculation, and storage control of cursor position data ( 800, a keyboard 801 for adjusting cursor generation and position, an adjustment point memory 802 for storing the control point data, a subcursor position memory 803 for designating position data of the subcursor, A cursor generating unit 804 generating a cursor (adjustment point) under control of the central processing unit 800 and a horizontal sub cursor generating unit generating a horizontal sub cursor under control of the central processing unit 800 ( 805, a vertical subcursor generator 806 for generating a vertical subcursor under the control of the central processing unit 800, a phase locked loop circuit 807 forming a phase locked loop of a synchronization signal, and the phase Of the fixed loop circuit 807 An address generator 808 which generates a memory address by output and inputs it to the memory 812 through an address selection switch 811, and generates a test pattern which generates a test pattern by the output of the address generator 808. The unit 809 combines the output of the cursor generator 804, the output of the horizontal subcursor generator 805, the output of the vertical subcursor generator 806, and the output of the test pattern generator 809. A synthesizing unit 810 for outputting to an image circuit unit and the output of the address generator 808 or the address data of the central processing unit 800 under the control of the central processing unit 800 into the memory 812. An address selection switch 811, a memory 812 in which correction data is stored and output, and output data of the memory 812 or output data of the central processing unit 800 under the control of the CPU 800. In memory 812 or D A data selection switch 813 for outputting to the / A converter 814, a D / A converter 814 for converting data output from the data selection switch 813 into an analog signal, and the D / A converter 814 And a low pass filter 815 for waveform shaping the output signal of the PSA to the amplifier 816 and an amplifier 816 for amplifying the output signal of the low pass filter 815 and supplying it to the convergence yoke. .

In the digital convergence correction device of the present invention configured as described above, the keyboard 801 is an input means, and as shown in FIG. 9, a direction key 801A for inputting a cursor movement direction, and a position of the cursor is changed. Input cursor keys 801B, horizontal subcursor keys 801C and 801D for changing the positions of the two subcursors in the horizontal direction, an adjustment mode key 801E for inputting an adjustment mode, and an extrapolation adjustment mode. An extrapolation adjustment key 801F and vertical subcursor keys 801G and 801H for changing the positions of the two subcursors in the vertical direction. The displayed test pattern and the screen of the various adjustment points are configured and displayed as shown in FIG. 10, in which the operator can visually check the image corresponding to the inside of the screen.

In the convergence correction operation by the digital convergence correction device of the above configuration, the adjustment method is as follows.

First, when the adjustment mode key 801E of the keyboard 801 is inputted, the central processing unit 800 enters the adjustment mode, presses the cursor key 801B of the keyboard 801, and uses the direction key 801A to select a portion to be adjusted. Position the cursor (adjustment point), press the subcursor keys 801C, 801D, 801G, and 801H and position the sub-adjustment point using the direction keys 801A.

That is, the central processing unit 800 controls the cursor generating unit 804 to generate a cursor (adjustment point) according to each key input of the keyboard 801, and the horizontal sub cursor generating unit 805 and the vertical sub. The cursor generator 806 is controlled to generate a vertical subcursor, and the test pattern generator 809 is generated according to the address generated by the address generator 808 by inputting the locked synchronization signal of the phase locked loop circuit 807. ) Generates a test pattern, and the cursor (adjustment point) and two sub-cursors are synthesized in the synthesis unit 810, respectively, horizontally and vertically, and the cursors corresponding to the test pattern and each adjustment point are shown in FIG. These cursors are displayed on the screen, and the positions of these cursors are set in response to the key operation of the keyboard 801 as described above.

When the adjustment mode key 801E is pressed at the control point located as described above and the direction key 801A is pressed, the central processing unit 800 receives the input of these keys and performs curve interpolation within the section designated by the sub control point.

Such curve interpolation is performed in the horizontal or vertical direction, and the horizontal and vertical directions can be adjusted simultaneously.

For example, to adjust the horizontal direction, place the cursor at the 'D' point as shown in FIG. 10, and place the horizontal subcursor 1 and the horizontal subcursor 2 at the 'I' and 'L' points, respectively. Since the adjustment points between the 'L' points are 'J', 'D' and 'K', the central processing unit 800 adjusts the correction data of the 'D' points during operation (I, J, D). The correction data is changed by performing (n-1) th order curve interpolation (fourth order curve interpolation) using the K, L 'points (five points).

The data thus calculated (corrected) is switched to the central processing unit 800 by switching the address selection switch 811 to the central processing unit 800 with the chip select signal CS low (L) in the central processing unit 800. After switching 813 to the central processing unit 800 side, an address output from the central processing unit 800 is applied to the memory 812 through the address selection switch 811, and output from the central processing unit 800. The correction data is applied to the memory 812 through the data selection switch 813 and written to the memory 812.

When data recording is completed, the central processing unit 800 outputs the chip select signal CS again as a high (H) signal, so that the address selection switch 811 is switched to the address generator 808, and the data selection switch 813 ) Is switched to the D / A converter 814 side and placed in the normal mode.

In the normal mode, an address designated by the address generator 808 is applied to the memory 812 through the address selection switch 811, and output data of the memory 812 is transferred through the data selection switch 813 to the D / A converter. 814, the operation in this normal mode is as usual.

The interpolation in the vertical direction is also similar to the above-described horizontal case. If the cursor is at the 'D' point as in FIG. 10, the vertical subcursor 1 is placed at the 'B' point, and the vertical subcursor 2 is placed at the 'F' point. In the vertical adjustment of the 'D' point, the fourth-order curve interpolation is performed.

Here, the 'A' and 'G' points outside the subcursor have no effect when the 'D' point is moved vertically.

If the sub-cursor adjustment points are present at the points' C 'and' D ', the CPU 800 performs the second curve interpolation using the points' C, D, and E', where 'A, B, There is no change in convergence of F and G 'points.

On the other hand, if the user wants to perform the adjustment by looking at the full screen during the initial adjustment, do not determine the position of the horizontal subcursor, but specify the subcursor by performing the interpolation by performing the nth order already designated by the central processing unit 800 to adjust the convergence. This can shorten the time to do.

The above-described sequence of convergence adjustment procedures includes determining whether or not the position of the sub-cursor is made as shown in FIG. 12, and if the position is determined by the sub-cursor as a result of the determination of the step, the position of the two sub-cursors. Determining and interpolating the (n-1) th order curve, storing the interpolated operation data and the position data of the subcursor in a memory, and n-th order curve interpolation previously offset if not determined by the subcursor as a result of the determination of the step And storing the interpolated calculation data in a memory.

That is, when the sub-cursor positioning is performed at the time of key input, two sub-cursor intervals are determined to perform (n-1) -order curve interpolation, and the interpolation data is stored in the memory 812. The position data is stored in the subcursor position memory 803. If there is no position designation of the subcursor at the time of key input, the offset n-th order curve interpolation is performed, and the interpolation data is stored in the memory 812.

If the adjusted sub-cursor position is stored as shown in FIG. 11, the contents of the sub-cursor position memory 803 are read from the central processing unit 800 at the first power-on, and the adjustment point correction data at the position is read. By searching in the adjustment point memory 802, the portion already adjusted using the subcursor performs separate curve interpolation within a designated section.

That is, reading the position data of the sub-cursor stored in the memory at the first power-on and the correction data of the adjustment point of the sub-cursor section, and determining whether or not it is the adjustment section using the sub-cursor based on the read data. And determining, by the determination result of the step, the sub-cursor position by interpolating the two sub-cursor positions by (n-1) order and storing the interpolated calculation data in a memory. If it is not the adjustment section using the result subcursor, the control is performed by performing the offset n-th order curve interpolation and storing the interpolated calculation data in the memory.

In this way, a block that is not well adjusted can be managed separately, and when performing full-scale correction data calculation using the convergence correction data stored in the adjustment point memory 802 at the initial power-on, the sub cursor is used. The precision can be increased by searching for separate finely tuned sections and calculating them separately from other parts.

Although the above described convergence correction operation is divided into horizontal and vertical, the operator uses the keyboard 801 to cause the central processing unit 800 and the sub-cursor generator 805 and 806 to move the horizontal sub-cursor and the vertical sub. If all cursors are generated and adjusted, a block adjustment that performs curve interpolation within a given block is also possible.

On the other hand, as shown in FIG. 13, when the cursor is not specified and only the sub cursor is assigned to the 'F, B' point, the extrapolation adjustment key 801F is input, and then the direction key 801A is input, the central processing unit ( 800) changes the correction data of the 'Y' point (assuming 'Y' point and the external control point among the 'X, Y, Z' points) while changing the correction data of the 'X' point and the 'Z' point. Use F, G, Y, A, and B 'points to obtain (n-1) th order curve interpolation (fourth order interpolation because the number of adjustment points is n = 5).

Of course, the 'X, Y, Z' point can also be obtained by using only the 'F, G, A, B' points.

That is, determining whether the extrapolation adjustment mode is performed by searching for a key input; determining whether the positioning is performed by two sub-cursors when the extrapolation adjustment mode is determined as the result of the determination; In case of positioning by cursor, the position of cursor (adjustment point) is ignored, two sub-cursor positions are discriminated and (n-1) order curve interpolation is performed, and the interpolated operation data and the position data of sub-cursor are stored in memory. It is controlled by memorizing steps.

In this way, the convergence at the periphery of the screen can be precisely measured, such as 'G' and 'X', 'Z' and 'A', 'S' and 'H', 'T' and 'M'. By adjusting, the accuracy of the adjustment can be increased.

The data interpolated once is stored in the memory 812 by controlling the address selection switch 811 and the data selection switch 813 in the central processing unit 800 as described above, and the subcursor position data at this time is also a subcursor. This is stored in the position memory 803.

As described above, the interpolated data is converted into an analog correction waveform by the D / A converter 814 and then amplified by the amplifier 816 via the low pass filter 815 and applied to the convergence yoke.

In addition, in the above-described digital convergence correction apparatus of the present invention, an embodiment in which there is no sub cursor generation unit 805 or 806 is also implemented.

That is, in such a case, the operator inputs to the central processing unit 800 how many times the curve is interpolated by the operator at an arbitrary adjustment point determined by the cursor (adjustment point) generating unit 804. The value n is stored in the sub-cursor position memory 803 so that the central processing unit 800 adjusts the convergence by the adjustment points by performing interpolation of orders different from other adjustment points at any position from this data. Make it manageable.

As described above, according to the present invention, since the horizontal or vertical section to be adjusted is set as the sub cursor, the other parts that have already been adjusted are not affected, and when performing curve interpolation for the entire screen in the adjusted state, Since we have already made adjustments to the curve interpolation of the intersection, there is no big change in the screen.

Therefore, according to the present invention, the number of adjustments can be reduced as much as possible, and the adjustment time is also shortened.

In addition, according to the digital convergence correction device and the method of the present invention, it is possible to extrapolate the outside of the screen so that the convergence accuracy of the peripheral portion can be greatly improved, and the adjustment section of the subcursor is stored in the memory, and the adjustment section Because it is managed separately, it is possible to precisely adjust the convergence of blocks that are difficult to adjust.

Furthermore, in the present invention, the horizontal and vertical sub-cursors can be simultaneously generated to achieve effects such as block adjustment.

Claims (6)

A memory for storing and outputting correction data, an address generator of the memory, a test pattern generator for generating a test pattern by the address generator, and a D / conversion for converting the correction data output from the memory into an analog signal; The A converter, a low pass filter for filtering the output signal of the D / A converter and supplying them to the convergence yoke through an amplifier unit, and a central processing unit that controls each component and performs calculation of correction data are used. A digital convergence correction device which obtains a convergence correction waveform through D / A conversion and low pass filtering by synchronizing with a synchronous signal, comprising: a cursor generator for generating a cursor (adjustment point) under the control of the central processing unit; A sub-cursor generator for generating a horizontal or vertical sub-cursor under the control of the CPU; A synthesizing unit for synthesizing the text patterns and the cursor signals and outputting them to the screen, and input means connected to a central processing unit for adjusting the generation and the positional movement of the cursor. A digital convergence correction apparatus, characterized by obtaining correction data by interpolating a specified section separately. The digital convergence correction apparatus according to claim 1, wherein the subcursor generating unit simultaneously generates horizontal or vertical subcursors so that the convergence of blocks divided into the subcursors can be adjusted. The memory of claim 1, further comprising a memory for storing position data of a sub-cursor corresponding to a section adjusted by the sub-cursor so that the central processing unit creates separate interpolation calculation data even when the initial power-on is turned on. Digital convergence correction device, characterized in that. Reading the position data of the sub-cursor stored in the memory at the first power-on and the correction data of the adjustment point of the sub-cursor section, and determining whether or not it is the adjustment section using the sub-cursor based on the read data; In the case of the adjustment section using the sub-cursor as a result of the determination of the step, determining the position of the two sub-cursors and interpolating the (n-1) order curve and storing the interpolated calculation data in the memory; and And performing an offset n-th order curve interpolation, if not, using the cursor, and storing the interpolated calculation data in a memory. Judging whether or not the position of the subcursor has been specified; and in the case of the position designation for the subcursor, the position of the two subcursors is determined and interpolated by (n-1) difference curves, and the interpolated calculation data Storing the position data of the sub-cursor in a memory, and performing the n-th order curve interpolation which is offset in advance if not determined by the sub-cursor, and storing the interpolated calculation data in the memory. Digital convergence correction method, characterized in that. Determining whether it is in the extrapolation adjustment mode by searching a key input; determining whether the positioning is performed by two subcursors in the extrapolation adjustment mode; and as a result of the determination, In case of positioning by ignoring the position of cursor (adjustment point), two sub-cursor positions are discriminated and (n-1) order curve interpolation, and interpolated operation data and position data of sub-cursor are stored in memory. Digital convergence correction method, characterized in that the control in steps.